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JP3753218B2 - Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus - Google Patents

Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus Download PDF

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Publication number
JP3753218B2
JP3753218B2 JP07528299A JP7528299A JP3753218B2 JP 3753218 B2 JP3753218 B2 JP 3753218B2 JP 07528299 A JP07528299 A JP 07528299A JP 7528299 A JP7528299 A JP 7528299A JP 3753218 B2 JP3753218 B2 JP 3753218B2
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JP
Japan
Prior art keywords
intermediate layer
conductive foil
semiconductor device
electrode
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP07528299A
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Japanese (ja)
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JPH11340369A (en
Inventor
伸晃 橋元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to US09/272,244 priority Critical patent/US6333565B1/en
Priority to JP07528299A priority patent/JP3753218B2/en
Priority to TW088104498A priority patent/TW404027B/en
Publication of JPH11340369A publication Critical patent/JPH11340369A/en
Priority to US09/985,074 priority patent/US6583516B2/en
Priority to US10/383,530 priority patent/US6900548B2/en
Priority to US11/115,205 priority patent/US7038323B2/en
Priority to US11/348,470 priority patent/US7271499B2/en
Application granted granted Critical
Publication of JP3753218B2 publication Critical patent/JP3753218B2/en
Priority to US11/889,467 priority patent/US7420285B2/en
Priority to US12/219,833 priority patent/US7659142B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置及びその製造方法、回路基板並びに電子機器に関する。
【０００２】
【発明の背景】
半導体装置の高密度実装を追求すると、ベアチップ実装が理想的である。しかしながら、ベアチップは、品質の保証及び取り扱いが難しい。そこで、ＣＳＰ（Chip Scale/Size Package）が適用された半導体装置が開発されている。ＣＳＰについては正式な定義はないが、一般に、パッケージサイズがＩＣチップと同じか、ＩＣチップよりわずかに大きいＩＣパッケージと解されている。高密度実装を推進するためには、ＣＳＰ技術の開発が重要である。ＣＳＰに関する従来例を開示する刊行物として、国際公開ＷＯ９５／０８８５６号公報がある。
【０００３】
これによれば、外部電極を有する基板と半導体チップとの間にギャップが形成され、このギャップに樹脂が注入される。この樹脂は、硬化したときに弾力性を有するものである。この弾力性を有する樹脂によって、外部電極に加えられた応力（熱ストレス）が吸収される。なお、この応力は、半導体装置と、この半導体装置が実装される回路基板との熱膨張率の差によって生じる。
【０００４】
しかしながら、半導体チップの基板との間に注入される樹脂は、極めて薄いために十分な熱ストレスの吸収がなされていなかった。
【０００５】
本発明は、この問題点を解決するものであり、その目的は、熱ストレスを効果的に吸収することができる半導体装置及びその製造方法、回路基板並びに電子機器を提供することにある。
【０００６】
【課題を解決するための手段】
（１）本発明に係る半導体装置は、電極を有する半導体素子と、
それぞれの電極の少なくとも一部を避けて前記半導体素子の表面上に設けられるパッシベーション膜と、
前記パッシベーション膜が形成された面の上方において、厚み方向に所定の間隔をあけて設けられる導電箔と、
前記導電箔上に形成される外部電極と、
前記パッシベーション膜と前記導電箔との間に形成されるとともに前記導電箔を支持する中間層と、
前記電極と前記導電箔とを電気的に接続する配線と、を有し、
前記中間層には、前記導電箔における前記外部電極との接合部を含む領域の下方に、前記パッシベーション膜と前記導電箔側との間に開口領域となる凹部が形成されている。
【０００７】
本発明に係る「半導体素子」は、半導体チップにとどまらず、個片になっていないウエーハ状のものを指す場合もある。すなわちここでいう半導体素子とは、例えばシリコンからなるベース基板状に切り離したとしても使える所定の回路が形成されていれば良く、切り離されて個片となっているかそれとも一体となっているかについては特に限定する必要はない。
【０００８】
本発明によれば、外部電極が導電箔に形成され、導電箔は中間層にて支持されている。中間層には凹部が形成され、凹部の上方に外部電極が位置している。すなわち、外部電極が中間層に直接支持されずに、中間層から浮いた状態になっている。このことによって、外部電極は比較的自由に動くことができるので、回路基板との熱膨張率の差によって生じた応力（熱ストレス）を吸収することができる。
【０００９】
（２）前記凹部内には、前記中間層よりもヤング率が低い樹脂が充填されていてもよい。
【００１０】
こうすることで、凹部の空間を埋めることができるので、リフロー工程などの加熱時に、水蒸気の膨張によるクラックを防止することができる。
【００１１】
（３）前記配線は、前記パッシベーション膜が形成された面上に形成されるとともに前記中間層の凹部の底面に位置し、
前記樹脂は、導電フィラーが添加されたものであって、前記配線と前記導電箔とを電気的に接続されていてもよい。
【００１２】
（４）前記中間層は、前記電極と前記導電箔との間に傾斜面を有し、
前記配線は、前記傾斜面を通って前記電極と前記導電箔とを電気的に接続してもよい。
【００１３】
（５）前記中間層は、柔軟性を有する材料から形成されてもよい。
【００１４】
こうすることで、中間層自体によっても応力を緩和することができる。
【００１５】
（６）前記導電箔は、前記凹部の開口領域の内側の位置であって前記外部電極との接続部を避ける位置に、穴を有してもよい。
【００１６】
こうすることで、導電箔が変形しやすくなり、導電箔によって応力を吸収することができる。
【００１７】
（７）本発明において、前記導電箔が形成された基板が、前記導電箔が形成された面を前記中間層に向けて設けられており、
前記基板は、前記凹部の上方に貫通穴を有し、
前記貫通穴を介して前記導電箔に前記外部電極が形成されてもよい。
【００１８】
これによれば、導電箔上が基板にて覆われて保護される。
【００１９】
（８）本発明において、前記中間層と前記導電箔との間に、柔軟性を有する材料から形成される基板が設けられ、
前記基板は、前記凹部の上方を除く領域に貫通穴を有し、
前記貫通穴を介して前記配線と前記導電箔とが電気的に接続されてもよい。
【００２０】
（９）前記導電箔と前記配線とは、一体的に形成されていてもよい。
【００２１】
（１０）前記導電箔と前記配線とは、別体であってもよい。
【００２２】
（１１）本発明に係る半導体装置の製造方法は、電極を有し、それぞれの電極の少なくとも一部を避けて表面上にパッシベーション膜が設けられた半導体素子を用意する工程と、
前記パッシベーション膜が形成された面の上方に、厚み方向に所定の間隔をあけて導電箔を設け、前記パッシベーション膜と前記導電箔との間に前記導電箔を支持する中間層を形成し、前記中間層に、前記電極を避ける位置でくぼむ凹部を形成する工程と、
前記電極と前記導電箔とを電気的に接続する配線を形成する工程と、
前記導電箔における前記凹部の上方位置に外部電極を形成する工程と、
を含む。
【００２３】
本発明によって製造される半導体装置によれば、外部電極が導電箔に形成され、導電箔は中間層にて支持されている。中間層には凹部が形成され、凹部の上方に外部電極が位置している。すなわち、外部電極が中間層に直接支持されずに、中間層から浮いた状態になっている。このことによって、外部電極は比較的自由に動くことができるので、回路基板との熱膨張率の差によって生じた応力（熱ストレス）を吸収することができる。
【００２４】
（１２）本発明において、貫通穴を有し、かつ、前記貫通穴上を含めて前記導電箔が貼り付けられた基板を用意し、
前記パッシベーション膜が形成された面上に前記中間層を形成し、前記中間層に前記凹部を形成し、
その後、前記貫通穴を前記凹部の上方に位置させて、かつ、前記導電箔を前記凹部に対向させて、前記基板を前記中間層に載せ、
前記貫通穴を介して前記導電箔に前記外部電極を形成してもよい。
【００２５】
これによれば、導電箔が基板に貼り付けられているので、導電箔を形成する工程を簡単に行うことができる。
【００２６】
（１３）本発明において、柔軟性を有する材料から形成されて貫通穴を有する基板を用意し、
前記パッシベーション膜が形成された面上に前記中間層を形成し、前記中間層に前記凹部を形成し、かつ、前記中間層に前記配線を形成し、
前記配線上に前記貫通穴を位置させて前記基板を前記中間層に載せ、前記基板に前記導電箔を形成し、前記貫通穴を介して前記配線と前記導電箔とを電気的に接続してもよい。
【００２７】
これによれば、導電箔が基板に貼り付けられているので、導電箔を形成する工程を簡単に行うことができる。
【００２８】
（１４）前記パッシベーション膜が形成された面上に前記中間層を形成し、前記中間層に前記導電箔を形成し、前記導電箔に穴を形成し、前記穴を介して前記中間層をエッチングして前記凹部を形成してもよい。
【００２９】
（１５）前記中間層は、前記半導体素子のエッチングが不可能な条件下で、エッチング可能な材料で形成されてもよい。
【００３０】
こうすることで、中間層をエッチングするときに、半導体素子の表面もエッチングされることを防止できる。
【００３１】
（１６）前記パッシベーション膜は、前記中間層のエッチング条件下でエッチングされるものであり、
前記パシベーション膜上に、前記中間層のエッチング条件下でエッチングされにくい材料からなる被覆層を形成し、前記被覆層に前記中間層を形成し、前記中間層に前記導電箔を形成し、前記導電箔に穴を形成し、前記穴を介して前記中間層をエッチングして前記凹部を形成してもよい。
【００３２】
このように、パシベーション膜に被覆層を形成することで、パシベーション膜のエッチングを防止することができる。
【００３３】
（１７）前記パッシベーション膜は、前記中間層のエッチング条件下でエッチングされるものであり、
前記パシベーション膜上に、前記中間層のエッチング条件下でエッチングされにくい材料からなる第１の被覆層を形成し、
前記第１の被覆層上に前記中間層を形成し、
前記中間層上に前記導電箔及び配線を形成するとともに前記導電箔に穴を形成し、
前記配線上にソルダレジスト層を形成し、
前記ソルダレジスト層上に、前記中間層のエッチング条件下でエッチングされにくい材料からなる第２の被覆層を形成し、
前記導電箔の穴を介して前記導電箔の下に至るまで前記中間層をエッチングしてもよい。
【００３４】
（１８）前記中間層をエッチングする工程の前に、前記導電箔に前記外部電極を形成し、前記外部電極に、前記中間層のエッチング条件下でエッチングされにくい材料からなる電極被覆層を形成する工程を含んでもよい。
【００３５】
これによれば、外部電極を形成してから、中間層をエッチングして凹部を形成する。したがって、外部電極の形成により生じる残渣を除去してからエッチングを行えるので、残渣が凹部に残らない。
【００３６】
（１９）本発明では、前記凹部に、前記中間層よりもヤング率が低い樹脂を充填する工程を含んでもよい。
【００３７】
（２０）本発明に係る回路基板には、上記半導体装置が実装される。
【００３８】
（２１）本発明に係る電子機器は、上記回路基板を有する。
【００３９】
【発明の実施の形態】
以下、本発明の好適な実施の形態について図面を参照して説明する。
【００４０】
なお、各図面は説明を分かりやすくするために一部を拡大して示したものである。以下の説明においては、最終的に個片にしたときの１つの半導体装置を想定して説明しているため、用いている用語や形状等において若干実際と異なる箇所がある。以下の説明では、半導体チップと記載してあり、その意味の通り個片（すなわちチップ状）のものを指しているが、本発明に係る「半導体素子」は、半導体チップにとどまらず、個片になっていないウエーハ状のものを指す場合もある。すなわちここでいう半導体素子とは、例えばシリコンからなるベース基板状に切り離したとしても使える所定の回路が形成されていれば良く、切り離されて個片となっているかそれとも一体となっているかについては特に限定する必要はない。また配線等の説明に必要な個所の代表的な箇所のみを取り上げているので、各図にはその他の箇所に同様のものやその他の構造が省略されている。
【００４１】
（第１実施形態）
図１は、第１実施形態に係る半導体装置を示す断面図である。同図に示す半導体装置１０は、パッケージサイズが半導体チップ１２とほぼ同じであるＣＳＰ型のものである。
【００４２】
半導体チップ１２の能動面１２ａには、例えばアルミニウム（Ａｌ）から電極１４が形成されている。また、それぞれの電極１４の少なくとも一部を避けて半導体チップ１２には、パッシベーション膜１１が形成されている。ここで、少なくとも一部を避けるとは、電極１４から電気的信号等を導き出す必要があるからである。したがって、電極１４から電気的信号等が導き出せる程度に、パッシベーション膜１１が電極１４を避ける必要がある。パッシベーション膜１１は、例えば、ＳｉＯ2、ＳｉＮ、ポリイミド樹脂などで形成することができる。電極１４を避けて能動面１２ａに中間層１６が形成されている。詳しくは、パッシベーション膜１１上に中間層１６が形成されている。また、中間層１６には、凹部１６ａが形成されており、凹部１６ａ内では能動面１２ａが露出している。もっとも、凹部１６ａは、へこんだ形状であれば足り、能動面１２ａが露出していなくてもよい。また、中間層１６には、電極１４から傾斜する傾斜面１６ｂが形成されており、電極１４から傾斜面１６ｂを経て中間層１６上にかけて、配線１８が形成されている。図１に示す凹部１６ａの開口端部は、外部電極２６の根本の部分の大きさよりもかなり大きいが、これに限定されず、外部電極２６の根本の部分の大きさとほぼ等しいかあるいはそれ以上であればよい。さらに、外部電極２６の根本の一部に、凹部１６ａの開口が位置しても良く、この場合は、この開口が中間層の変形を許し、応力緩和効果を発揮できる。また、凹部１６ａは、中間層１６を貫通してその下のパッシベーション膜１１を露出させてもよいが、中間層１６を貫通しないように凹部１６ａの底部に中間層１６の一部を残しても良い。
【００４３】
ここで、中間層１６は、絶縁樹脂、例えばポリイミド樹脂からなり、半導体装置１０が回路基板（図示せず）に実装されたときに、半導体チップ１２と実装される回路基板との熱膨張係数の差によって生じる応力を緩和することができる。なお、中間層１６が応力緩和機能を有することは、本発明の必須要件ではない。応力緩和機能は、凹部１６ａが形成されていることでも達成される（詳しくは後述する）。
【００４４】
また、絶縁樹脂は、配線１８に対して絶縁性を有し、半導体チップ１２の能動面１２ａを保護することができ、実装時のハンダを溶融するときの耐熱性も有する。後述する応力緩和機能を付加させることを考慮すると、ポリイミド樹脂等が一般的に用いられ、中でもヤング率が低いもの（例えばオレフィン系のポリイミド樹脂や、ポリイミド樹脂以外としてはダウケミカル社製のＢＣＢ等）を用いることが好ましく、特にヤング率が３００ｋｇ／ｍｍ2 以下程度であることが好ましい。中間層１６は、厚いほど応力緩和力が大きくなるが、半導体装置の大きさや製造コスト等を考慮すると、１〜１００μｍ程度の厚みとすることが好ましい。ただし、ヤング率が３００ｋｇ／ｍｍ2 程度のポリイミド樹脂を用いた場合には、１０μｍ程度の厚みで足りる。
【００４５】
あるいは、中間層１６として、例えばシリコーン変性ポリイミド樹脂、エポキシ樹脂やシリコーン変性エポキシ樹脂等を用いても良く、さらに、ヤング率が低く応力緩和の働きを果たせる材質を用いてもよい。また、中間層１６として、パシベーション層（ＳｉＮ、ＳｉＯ2 、ＭｇＯなど）を形成し、応力緩和自体は、後述するように凹部１６ａが形成されることで行われてもよい。
【００４６】
配線１８は、例えば銅（Ｃｕ）やクロム（Ｃｒ）、チタン（Ｔｉ）、ニッケル（Ｎｉ）、チタンタングステン（Ｔｉ−Ｗ）から又はこれらのうちの複数を積層して形成され、その上に導電箔２２が形成されている。導電箔２２は、予め基板２０に形成されたもので、接着剤２４を介して、基板２０とともに配線１８上に貼り付けられる。なお、導電箔２２も、例えば銅（Ｃｕ）から形成されている。
【００４７】
導電箔２２は、中間層１６に形成された凹部１６ａの開口端部よりも大きく形成されて、この凹部１６ａの上方を覆うように配置されている。また、導電箔２２の一部は、配線１８の上に接触して電気的に接続されている。なお、導電箔２２と配線１８とは、熱及び圧力を加えて溶着されることが好ましい。導電箔２２と配線１８との電気的な接続は、上述のような、接着剤２４による機械的圧接によっても良いし、配線１８及び導電箔２２上にＡｕ、Ｓｎ、ハンダ等をメッキして両者をロウ付けしても良く、超音波熱等による拡散接合で接続しても良い。そのために、導電箔２２及び配線１８の双方の接合面のうち少なくとも一方に、低温ろうが設けられていることが好ましい。
【００４８】
基板２０は、柔軟性を有する樹脂等で形成されたフィルム状のもので、凹部１６ａの上方の位置に、貫通穴２０ａを有する。なお、導電箔２２は、基板２０の下面において、貫通穴２０ａを覆うように形成されている。そして、貫通穴２０ａを介して、導電箔２２に外部電極２６が形成されている。外部電極２６は、例えば、ハンダのみで形成してもよいし、銅（Ｃｕ）又はニッケル（Ｎｉ）の表面にハンダ又は金のメッキを施して形成してもよい。
【００４９】
なお、導電箔２２付きの基板２０として、２層（Ｃｕ箔＋ポリイミド基板）又は３層（Ｃｕ箔＋接着剤＋ポリイミド基板）のＴＡＢ技術で用いられるフィルムキャリアテープ又はＦＰＣ（Flexible Printed Circuit）を使用してもよい。
【００５０】
本実施形態は、上記のように構成されており、以下その作用を説明する。半導体装置１０において、外部電極２６が形成された導電箔２２は、中間層１６によって支持されている。ただし、中間層１６には、外部電極２６の直下を含む領域に、凹部１６ａが形成されている。凹部１６ａによって、導電箔２２の下には空間が形成される。つまり、外部電極２６との接合部付近において、導電箔２２は浮いた状態となって変形しやすくなっている。このように構成されているので、外部電極２６に応力が加えられると、導電箔２２及び基板２０が変形することで、その応力を吸収することができる。こうして、半導体装置を回路基板に実装する際や、実装された回路基板や電子機器が温度変化による半導体装置（又はシリコンから形成される半導体チップ）と回路基板との熱膨張係数差によるストレスや、外部応力によって曲げられた際に発生する機械的ストレスを吸収することができる。以下、ストレスとは、このことを言う。
【００５１】
次に、図２に、本実施形態に係る半導体装置の平面図を示す。同図において、半導体チップ１２の電極１４から、能動面１２ａの中央方向に配線１８が形成され、各配線１８は導電箔２２に接続され、導電箔２２には外部電極２６が設けられている。外部電極２６を除く領域は、基板２０によって覆われて保護されている。
【００５２】
電極１４は、半導体チップ１２の周辺部に位置する、いわゆる周辺電極型の例であるが、半導体チップの周辺領域よりも内側領域に電極が形成されたエリアアレイ配置型の半導体チップを用いても良い。
【００５３】
なお、同図に示されるように、外部電極２６は半導体チップ１２の電極１４上ではなく半導体チップ１２の能動領域（能動素子が形成されている領域）に設けられている。中間層１６を能動領域に設け、更に配線１８を能動領域内に配設する（引き込む）ことで、外部電極２６を能動領域内に設けることができる。すなわち、ピッチ変換をすることができる。従って外部電極２６を配置する際に能動領域内、すなわち一定の面としての領域が提供できることになり、外部電極２６の設定位置の自由度が非常に増すことになる。
【００５４】
そして、配線１８を必要な位置で屈曲させることにより、外部電極２６は格子状に並ぶように設けられている。なお、これは、本発明の必須の構成ではないので、外部電極２６は必ずしも格子状に並ぶように設けなくても良い。
【００５５】
また、図２には、電極１４と配線１８との接合部において、電極１４の幅と配線１８の幅が、
配線１８＜電極１４
となっているが、実際には、
電極１４≦配線１８
とすることが好ましい。特に、
電極１４＜配線１８
となる場合には、配線１８の抵抗値が小さくなるばかりか、強度が増すので断線が防止される。
【００５６】
なお、本実施形態では、中間層１６が応力緩和機能を有するが、凹部１６ａが形成されることだけでも、ストレスを吸収することが可能である。したがって、中間層１６として、応力緩和機能を有しない材質からなる層（例えば単なる絶縁層又は保護層）を形成した構造であっても、ストレスの吸収が可能となる。
【００５７】
次に、図３（Ａ）〜図３（Ｅ）は、本実施形態に係る半導体装置の製造方法を説明する図である。まず、図３（Ａ）に示すように、例えばアルミニウム（Ａｌ）からなる電極１４を有する半導体チップ１２を用意する。なお、電極１４を避けて半導体チップ１２には、図示しないパッシベーション膜が形成されている。ウエーハ状の半導体素子に対して、本発明に係る工程を行うときでも、市販されているウエーハを用意すればよい。そして、半導体チップ１２の能動面１２ａに、図示しないポリイミド樹脂をスピンコートなどの方法で設ける。あるいは、予めフィルム状にされたポリイミド樹脂等を、能動面１２ａに貼り付けてもよい。
【００５８】
そして、フォトリソグラフィの工程を経て、図３（Ｂ）に示すように、凹部１６ａを有する中間層１６を形成する。なお、凹部１６ａをフォトリソグラフィにより形成する場合には、それに適した材料を中間層１６の材料として選ぶことが好ましい。
【００５９】
続いて、図３（Ｃ）に示すように、電極１４から中間層１６上に至る配線１８を形成する。例えば、スパッタリングにより１００オングストローム（１０-10 ｍ）のチタンタングステン（Ｔｉ−Ｗ）層を形成し、その上に同様にスパッタリングにより１μｍの銅（Ｃｕ）層を形成し、こうして得られた金属膜を、所定のパターンにエッチングして配線１８を形成する。
【００６０】
そして、図３（Ｄ）に示すように、接着剤２４を介して、基板２０を貼り付ける。基板２０には、予め貫通穴２０ａが形成されているとともに、貫通穴２０ａを覆う位置に導電箔２２が設けられている。
【００６１】
なお、導電箔２２及び配線１８の双方の接合面のうち少なくとも一方に、例えば、スズ（Ｓｎ）、金（Ａｕ）又はハンダ等をメッキして、低温ろうを設けることが好ましい。
【００６２】
そして、導電箔２２が配線１８上に接触するように基板２０を載せて、基板２０の上から熱及び圧力を加える。こうして、低温ろうが溶融して導電箔２２と配線１８とが電気的に接続される。この接続は、超音波等を印加して行われても良い。
【００６３】
次に、図３（Ｅ）に示すように、基板２０の貫通穴２０ａを介して、導電箔２２に外部電極２６を形成する。例えば、導電箔２２上に、ハンダボールを載せたり、ハンダメッキを積み上げたり、ハンダペーストを印刷したり、銅（Ｃｕ）又はニッケル（Ｎｉ）あるいはその両方のメッキを施してさらにハンダ又は金（Ａｕ）のメッキを施したりすることで、外部電極２６を形成する。
【００６４】
以上の工程によって、半導体装置１０を得ることができる。なお、半導体チップ１２がウエーハ状のものである場合には、ダイシングを行って個片に切断することで半導体装置１０が得られる。半導体装置１０は、その後、品質検査を行ってトレイ詰めされる。
【００６５】
なお、本実施形態では、配線１８は傾斜面１６ｂ上に形成されているが、凹部１６ａ側の傾斜面に形成されてもよい。このことは、以下の実施形態でも同様である。こうすれば、配線１８の大部分は、中間層１６を通り、保護されるため、装置信頼性が向上する。
【００６６】
（第２実施形態）
図４は、第２実施形態に係る半導体装置を示す図である。同図に示す半導体装置３０は、図１に示す半導体装置１０の凹部１６ａに、樹脂３２が充填されたことを特徴としており、それ以外の構成は半導体装置１０と同様である。図４に示す凹部１６ａの開口端部は、外部電極２６の根本の部分の大きさよりもかなり大きいが、これに限定されず、外部電極２６の根本の部分の大きさとほぼ等しいかあるいはそれ以上であればよい。さらに、外部電極２６の根本の一部に、凹部１６ａの開口が位置しても良く、この場合は、この開口が中間層の変形を許し、応力緩和効果を発揮できる。また、凹部１６ａは、中間層１６を貫通してその下のパッシベーション膜（図示せず）を露出させてもよいが、中間層１６を貫通しないように凹部１６ａの底部に中間層１６の一部を残しても良い。
【００６７】
樹脂３２として、例えば感光性レジストとして使用されるポリイミド樹脂、シリコンゲル又はゴム等のうち、中間層１６よりもヤング率が低くて柔らかいものを使用することが好ましい。こうすることで、凹部１６ａにより形成される空間を埋めることができるので、リフロー工程などの加熱時に、空気や水蒸気の膨張によるクラックを防止することができる。
【００６８】
樹脂３２は、基板２０を貼り付ける前に充填してもよいし、基板２０に穴を形成しておき基板２０を貼り付けてから穴を介して充填してもよい。
【００６９】
また、本実施形態のように凹部に樹脂を充填することは、以下の全ての実施形態においても適用することができる。
【００７０】
（第３実施形態）
図５は、第３実施形態に係る半導体装置を示す図である。同図に示す半導体装置４０は、図１に示す半導体装置１０と同様に、半導体チップ１２、電極１４、中間層１６及び配線１８を有し、中間層１６には凹部１６ａが形成されている。
【００７１】
中間層１６上には接着剤２４を介して基板４２が貼り付けられている。基板４２は、例えば、第１実施形態で中間層１６の材料として挙げたポリイミド樹脂等のヤング率の低い材料から形成された膜である。基板４２上には、配線状にパターン化された導電箔４４が形成され、導電箔４４上に外部電極４６が形成されている。基板４２には、配線１８のうち中間層１６の上に位置する部分上に、貫通穴４２ａが形成されている。貫通穴４２ａには、電気的接合部４８が形成されて、導電箔４４と配線１８とが電気的に接続されている。また、導電箔４４の上にはソルダレジスト層４９が、外部電極４６を避けて設けられて、導電箔４４を保護している。
【００７２】
次に、半導体装置４０の製造方法を説明する。まず、図３（Ａ）〜図３（Ｃ）に示す工程を経て、半導体チップ１２に、中間層１６及び配線１８を形成し、中間層１６には凹部１６ａを形成する。
【００７３】
そして、中間層１６上に、接着剤２４を介して基板４２を貼り付け、基板４２に貫通穴４２ａを形成する。なお、予め基板４２に貫通穴４２ａを形成してから、これを貼り付けてもよい。
【００７４】
次に、基板４２に導電箔４４を形成する。導電箔４４は、例えば、スパッタリング、電解メッキ、無電解メッキ等によって形成することができる。導電箔４４のパターン化にはフォトリソグラフィの技術を使用してもよい。あるいは、予め基板４２にパターン化された導電箔４４を設けておいてから、これを中間層１６上に貼り付けてもよい。
【００７５】
そして、例えば、無電解メッキにより、あるいはこれに電解メッキを加えるなどの方法で、基板４２の貫通穴４２ａを含む領域に電気的接合部４８を設ける。
【００７６】
次に、導電箔４４上に、外部電極４６の形成領域を避けてソルダレジスト層４９を設けてから、外部電極４６を形成する。外部電極４６の形成方法は、第１実施形態の外部電極２６の形成方法と同様である。
【００７７】
以上のようにして製造される半導体装置４０によっても、中間層１６に凹部１６ａが形成されているので、外部電極２６に加えられるストレスを吸収することができる。
【００７８】
（第４実施形態）
図６は、第４実施形態に係る半導体装置を示す図である。同図に示す半導体装置５０は、図１に示す半導体装置１０と同様に、電極５４を有する半導体チップ５２に中間層５６が形成され、中間層５６には凹部５６ａが形成されている。また、電極５４から中間層５６上にかけて配線５８が形成され、配線５８と一体的に導電箔６０が中間層５６上に形成されている。導電箔６０には、少なくとも一つの穴６０ａが形成されている。そして、導電箔６０における凹部５６ａ上の領域に、外部電極６２が形成されている。また、外部電極６２を避けて、配線５８及び導電箔６０上にソルダレジスト層６４が形成されて、これらが保護されている。
【００７９】
本実施形態は、その製造方法に特徴がある。図７（Ａ）〜図８（Ｃ）は、本実施形態に係る半導体装置の製造方法を説明する図である。
【００８０】
本実施形態では、基板を使用しないのでウエーハに対して中間層５６や外部電極６２等を形成してから、これを切断することが好ましい。これに対して、基板を使用する形態（第１〜第３実施形態）では、テープ状の基板を個片の半導体チップに貼り付けることができる。
【００８１】
まず、図７（Ａ）に示すように、半導体チップ５２の能動面５２ａに、電極５４を避けて中間層５６を形成する。中間層５６は、図１に示す中間層１６と同様の材料で形成される。中間層５６がヤング率の低い材料で形成される場合には、中間層５６によっても応力緩和機能を果たす。あるいは、応力緩和機能を果たさないような硬い材料（例えば、酸化マグネシウム（ＭｇＯ）等の無機物）で中間層５６を形成してもよい。
【００８２】
なお、中間層５６が後の工程でエッチングされるときに、半導体チップ５２の能動面５２ａがエッチングされないように、中間層５６は、半導体パシベーション膜と材質において異なることが好ましい。そのためには、中間層５６は、半導体チップ５２の表面に露出する物質がエッチングされない条件下で、エッチング可能な材料で形成されることが好ましい。
【００８３】
次に、図７（Ｂ）に示すように、電極５４から中間層５６上にかけて、金属膜６６を形成する。その製造方法は、第１実施形態の配線１８を形成するための金属膜の形成方法と同様である。この場合、後述する外部端子６２のストレスが配線５８に直接かかるので、配線５８の厚さは５〜２０μｍ程度とすることが好ましい。金属膜６６は、後述する工程でエッチングされて配線５８及び導電箔６０を形成するものである。
【００８４】
次に、図７（Ｃ）に示すように、金属膜６６における導電箔６０となる部分に、穴６０ａを形成し、この穴６０ａを介して、中間層５６をエッチング液又はエッチングガス（エッチャント）にさらす。例えば、中間層５６をポリイミド等の樹脂で形成した場合、エッチャントとしては、Ｋ０Ｈ等の強アルカリ水溶液や、Ｏ2 又はＣＦ4 等のドライエッチングガスが好ましく、中間層５６を酸化マグネシウム（ＭｇＯ）等で形成した場合には、熱リン酸水溶液等が好ましい。その後、必要に応じて、エッチャントを除去する。特に、ウエットプロセスの場合は、水洗、リンス工程を加えることが好ましい。こうして、図７（Ｄ）に示すように、中間層５６がエッチングされて凹部５６ａが形成される。
【００８５】
続いて、図８（Ａ）に示すように、金属膜６６をパターニングして、配線５８及び導電箔６０を形成する。そして、図８（Ｂ）に示すようにソルダレジスト層６４を形成して、図８（Ｃ）に示すように外部電極６２を形成する。ソルダレジストとしては、感光性のポリイミド樹脂やエポキシ樹脂ドライフィルム等が用いられることが多い。外部電極６２の形成方法は、第１実施形態と同様である。こうして、半導体装置５０が得られる。本実施形態においても、第１実施形態と同様の効果を達成することができる。
【００８６】
さらに、本実施形態によって製造された半導体装置５０は、導電箔６０に穴６０ａが形成されているので、導電箔６０が変形しやすくなっている。したがって、凹部５６ａ上で浮いた状態となった導電箔６０によるストレスの吸収効果が一層高められている。
【００８７】
（第５実施形態）
図９（Ａ）〜図９（Ｃ）は、第５実施形態に係る半導体装置の製造方法を示す図である。
【００８８】
本実施形態では、図９（Ａ）に示すように、電極７４を有する半導体チップ７２に中間層７６を形成する。中間層７６上には導電箔８０を形成し、導電箔８０から電極７４に至るように配線７８を形成する。配線７８及び導電箔８０上には、ソルダレジスト層８４を形成する。また、導電箔８０には、穴８０ａを形成する。
【００８９】
なお、中間層７６の形成方法は図７（Ａ）に示す方法と同じであり、配線７８及び穴８０ａ並びに導電箔８０の形成方法は図７（Ｂ）〜図８（Ａ）に示す方法と同じである。また、ソルダレジスト層８４は、外部電極８２（図９（Ｂ）参照）を避ける領域に形成される。
【００９０】
そして、導電箔８０上に外部電極８２を形成し、これに伴って生じる残渣を除去してから、外部電極８２及びソルダレジスト層８４上に、被覆層８６を形成する（図９（Ｂ）参照）。被覆層８６は、中間層７６のエッチング条件下では、エッチングされにくい材料から形成される。
【００９１】
続いて、導電箔８０の穴８０ａを介して、図７（Ｄ）の工程と同様にして、中間層７６に凹部７６ａを形成し、被覆層８６を除去して、図９（Ｃ）に示す半導体装置７０が得られる。
【００９２】
本実施形態によれば、外部電極８２を形成するときに生じる残渣を除去してから、中間層７６に凹部７６ａを形成するので、凹部７６ａに残渣が残らない。また、本実施形態により製造された半導体装置７０の特徴は、第４実施形態と同様である。
【００９３】
（第６実施形態）
図１０（Ａ）〜図１０（Ｃ）は、第６実施形態に係る半導体装置の製造方法を示す図である。
【００９４】
本実施形態では、図１０（Ａ）に示すように、電極１０４を避けて能動面１０２ａ上にパシベーション膜１０６が形成された半導体チップ１０２が使用される。パシベーション膜１０６は、図１０（Ｃ）に示す中間層１０８と共通する性質を有する材料で形成される。すなわち、パシベーション膜１０６は、中間層１０８のエッチング条件下で、エッチングされる材料で形成されている。例えば、中間層１０８及びパシベーション膜１０６をいずれもポリイミド樹脂で形成した場合が該当する。
【００９５】
このような場合、図１０（Ｂ）に示すように、パシベーション膜１０６上において、少なくとも凹部１０８ａ（図１０（Ｃ）参照）の下の位置に、被覆層１１８を形成する。被覆層１１８は、中間層１０８及びパシベーション膜１０６のエッチング条件下ではエッチングされない材料で形成されている。例えば、中間層１０８及びパシベーション膜１０６がポリイミド樹脂から形成される場合には、被覆層１１８を、Ｃｒ、Ｔｉ−Ｗ、Ｔｉ等の金属薄膜とすればよい。
【００９６】
その後、図７（Ａ）〜図８（Ｃ）に示すのと同様の工程により、図１０（Ｃ）に示すように、凹部１０８ａを有する中間層１０８、配線１１０、穴１１２ａを有する導電箔１１２、外部電極１１４及びソルダレジスト層１１６を形成する。
【００９７】
本実施形態によれば、被覆層１１８によってパシベーション膜１０６が覆われているので、中間層１０８をエッチングして凹部１０８ａを形成するときに、パシベーション膜１０６までもエッチングされることを防止できる。こうして、凹部１０８ａ内に能動素子が露出することを防止できる。応力緩和機能に関する特徴は、上述した実施形態と同様である。
【００９８】
（第７実施形態）
図１１（Ａ）及び図１１（Ｂ）は、第７実施形態に係る半導体装置の一部を示す図である。なお、図１１（Ｂ）は、図１１（Ａ）のＢ−Ｂ線断面図である。本実施形態に係る半導体装置１２０は、図１に示す半導体装置１０における基板２０及び導電箔２２に、穴１２２、１２４が形成されたものである。
【００９９】
本実施形態によれば、穴１２２、１２４が形成されたことで、基板２０及び導電箔２２が変形しやすくなり、応力緩和機能が高められている。
【０１００】
（第８実施形態）
図１２は、第８実施形態に係る半導体装置を示す図である。同図に示す半導体装置１３０は、半導体チップ１３２の能動面１３２ａ上に、電極１３４から配線１３６が形成されている。配線１３６の上には中間層１３８が形成されている。そして、中間層１３８には、配線１３６上の位置で配線１３６が露出するように、凹部１３８ａが形成されている。中間層１３８の上には、接着剤１４２を介して、基板１４６が設けられている。この基板１４６には、凹部１３８ａの上方の位置で、かつ、この凹部１３８ａに対向する面に、導電箔１４４が形成されている。また、基板１４６には、凹部１３８ａの上方において、貫通穴１４６ａが形成されており、導電箔１４４が反対側の面から露出するようになっている。そして、貫通穴１４６ａを介して、外部電極１４８が形成されている。
【０１０１】
さらに、凹部１３８ａには、導電ペースト１４０が充填されている。導電ペースト１４０は、図４に示す凹部１６ａに充填された樹脂３２と同様に柔らかい樹脂に、銀（Ａｇ）、銅（Ｃｕ）、銀メッキ銅又は金（Ａｕ）などの導電フィラーが添加されたものである。この導電ペースト１４０によって、配線１３６と導電箔１４４とが電気的に接続される。
【０１０２】
本実施形態においても、中間層１３８に凹部１３８ａが形成されていることで、応力緩和機能を果たすことができる。
【０１０３】
（第９実施形態）
図１３（Ａ）〜図１４（Ｂ）は、第９実施形態に係る半導体装置の製造方法を示す図である。本実施形態では、図１０（Ａ）に示す半導体チップ１０２と同様に、パシベーション膜（図示せず）が能動面１５２ａに形成された半導体チップ１５２が使用される。このパシベーション膜は、中間層１５８のエッチング条件下で、エッチングされる材料から形成される。
【０１０４】
図１３（Ａ）に示すように、能動面１５２ａにおけるパシベーション膜上に被覆層１５６を形成する。被覆層１５６は、中間層１５８のエッチング条件下ではエッチングされない材料（例えば、クローム（Ｃｒ）、チタン（Ｔｉ）、チタンタングステン（Ｔｉ−Ｗ）又は銅（Ｃｕ）など）から形成される。被覆層１５６は、例えばスパッタリングにより形成される。
【０１０５】
次に、図１３（Ｂ）に示すように、被覆層１５６上を含み電極１５４を避けて、中間層１５８を形成する。中間層１５８の材料は、第１実施形態と同様である。
【０１０６】
そして、図１３（Ｃ）に示すように、電極１５４から中間層１５８にかけて配線１６０を形成し、配線１６０に電気的に接続するように導電箔１６２を形成する。具体的には、スパッタリングにて、クローム（Ｃｒ）、チタン（Ｔｉ）、チタンタングステン（Ｔｉ−Ｗ）又は銅（Ｃｕ）、あるいはこれらのうち複数が積層された金属膜を形成し、これをエッチングによりパターン化して、配線１６０及び導電箔１６２を一体的に形成する。また、導電箔１６２には、穴１６２ａを形成する。
【０１０７】
続いて、図１３（Ｄ）に示すように、導電箔１６２の上に外部電極１６４を形成する。具体的には、導電箔１６２上に、電解メッキ又は無電解メッキによって、銅（Ｃｕ）、ニッケル（Ｎｉ）又は金（Ａｕ）、あるいはこれらのうち複数が積層されたバンプを形成して、外部電極１６４を形成する。
【０１０８】
そして、図１４（Ａ）に示すように、配線１６０上にソルダレジスト層１６６を形成し、ソルダレジスト層１６６上に被覆層１６８を形成する。被覆層１６８も、中間層１５８のエッチング条件下ではエッチングされない材料（例えば、クローム（Ｃｒ）、チタン（Ｔｉ）、チタンタングステン（Ｔｉ−Ｗ）又は銅（Ｃｕ）など）から形成される。
【０１０９】
そして、図１４（Ｂ）に示すように、中間層１５８に凹部１５８ａを形成する。その工程は、図７（Ｄ）に示す工程と同様である。また、被覆層１６８をエッチングによって除去する。この例では、外部電極１６４の中央部に開口があるが、第７実施形態のような開口設計でもよい。
【０１１０】
以上の工程によって、半導体装置１５０を得ることができる。この半導体装置１５０も、中間層１５８に凹部１５８ａが形成されていることで、応力緩和機能を果たす。
【０１１１】
なお、図１４（Ｂ）に示す半導体装置１５０のバンプ状の外部電極１６４の代わりに、図１５に示すように、導電箔１６２における穴１６２ａを形成する端部上に、ハンダボールからなる外部電極１７０を形成してもよい。
【０１１２】
なお、本発明は、ＣＳＰ型の半導体装置に限定されるものではない。例えば、半導体チップの電極上に直接変形部を積層すれば、フリップチップと同等のサイズでありながら、応力緩和機能も有する半導体装置が得られる。
【０１１３】
図１６には、上述した実施形態に係る方法によって製造された半導体装置１１００を実装した回路基板１０００が示されている。回路基板１０００には例えばガラスエポキシ基板等の有機系基板を用いることが一般的である。回路基板１０００には例えば銅からなる配線パターンが所望の回路となるように形成されるとともに、この回路基板１０００にハンダボールが設けられている。そして、配線パターンのハンダボールと半導体装置１１００の外部電極とを機械的に接続することでそれらの電気的導通が図られる。
【０１１４】
この場合、半導体装置１１００には外部との熱膨張差により生じる歪みを吸収する構造が設けられているため、本半導体装置１１００を回路基板１０００に実装しても接続時及びそれ以降の信頼性を向上できる。
【０１１５】
なお、実装面積もベアチップにて実装した面積にまで小さくすることができる。このため、この回路基板１０００を電子機器に用いれば電子機器自体の小型化が図れる。また、同一面積内においてはより実装スペースを確保することができ、高機能化を図ることも可能である。
【０１１６】
そして、この回路基板１０００を備える電子機器として、図１７には、ノート型パーソナルコンピュータ１２００が示されている。
【０１１７】
なお、能動部品か受動部品かを問わず、種々の面実装用の電子部品に本発明を応用することもできる。電子部品として、例えば、抵抗器、コンデンサ、コイル、発振器、フィルタ、温度センサ、サーミスタ、バリスタ、ボリューム又はヒューズなどがある。
【図面の簡単な説明】
【図１】図１は、第１実施形態に係る半導体装置を示す断面図である。
【図２】図２は、第１実施形態に係る半導体装置を示す平面図である。
【図３】図３（Ａ）〜図３（Ｅ）は、第１実施形態に係る半導体装置の製造方法を示す図である。
【図４】図４は、第２実施形態に係る半導体装置を示す図である。
【図５】図５は、第３実施形態に係る半導体装置を示す図である。
【図６】図６は、第４実施形態に係る半導体装置を示す図である。
【図７】図７（Ａ）〜図７（Ｄ）は、第４実施形態に係る半導体装置の製造方法を説明する図である。
【図８】図８（Ａ）〜図８（Ｃ）は、第４実施形態に係る半導体装置の製造方法を説明する図である。
【図９】図９（Ａ）〜図９（Ｃ）は、第５実施形態に係る半導体装置の製造方法を示す図である。
【図１０】図１０（Ａ）〜図１０（Ｃ）は、第６実施形態に係る半導体装置の製造方法を示す図である。
【図１１】図１１（Ａ）及び図１１（Ｂ）は、第７実施形態に係る半導体装置を示す図である。
【図１２】図１２は、第８実施形態に係る半導体装置を示す図である。
【図１３】図１３（Ａ）〜図１３（Ｄ）は、第９実施形態に係る半導体装置の製造方法を示す図である。
【図１４】図１４（Ａ）及び図１４（Ｂ）は、第９実施形態に係る半導体装置の製造方法を示す図である。
【図１５】図１５は、第９実施形態の変形例を示す図である。
【図１６】図１６は、本実施形態に係る半導体装置が実装された回路基板を示す図である。
【図１７】図１７は、本実施形態に係る半導体装置が実装された回路基板を備える電子機器を示す図である。
【符号の説明】
１０ 半導体装置
１１ パッシベーション膜
１２ 半導体チップ
１２ａ 能動面
１４ 電極
１６ 中間層
１６ａ 凹部
１８ 配線
２０ 基板
２０ａ 貫通穴
２２ 導電箔
２６ 外部電極[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, a manufacturing method thereof, a circuit board, and an electronic device.
[0002]
BACKGROUND OF THE INVENTION
In pursuit of high-density mounting of semiconductor devices, bare chip mounting is ideal. However, bare chips are difficult to guarantee quality and handle. Therefore, a semiconductor device to which CSP (Chip Scale / Size Package) is applied has been developed. Although there is no formal definition of CSP, it is generally understood that the package size is the same as or slightly larger than the IC chip. In order to promote high-density mounting, development of CSP technology is important. As a publication disclosing a conventional example related to CSP, there is International Publication No. WO95 / 08856.
[0003]
According to this, a gap is formed between the substrate having the external electrode and the semiconductor chip, and resin is injected into this gap. This resin has elasticity when cured. Stress (heat stress) applied to the external electrode is absorbed by the resin having elasticity. This stress is caused by a difference in coefficient of thermal expansion between the semiconductor device and the circuit board on which the semiconductor device is mounted.
[0004]
However, since the resin injected between the semiconductor chip and the substrate is extremely thin, sufficient heat stress has not been absorbed.
[0005]
The present invention solves this problem, and an object thereof is to provide a semiconductor device capable of effectively absorbing thermal stress, a manufacturing method thereof, a circuit board, and an electronic apparatus.
[0006]
[Means for Solving the Problems]
(1) A semiconductor device according to the present invention includes a semiconductor element having an electrode;
A passivation film provided on the surface of the semiconductor element avoiding at least a part of each electrode;
Above the surface on which the passivation film is formed, a conductive foil provided at a predetermined interval in the thickness direction;
An external electrode formed on the conductive foil;
An intermediate layer formed between the passivation film and the conductive foil and supporting the conductive foil;
A wiring for electrically connecting the electrode and the conductive foil;
In the intermediate layer, the passivation film is provided below a region including a joint portion with the external electrode in the conductive foil. When The conductive foil side Between Opening area Become A recess is formed.
[0007]
The “semiconductor element” according to the present invention is not limited to a semiconductor chip, and may refer to a wafer-like one that is not separated. In other words, the semiconductor element here may be a predetermined circuit that can be used even if it is separated into a base substrate made of silicon, for example. There is no particular limitation.
[0008]
According to the present invention, the external electrode is formed on the conductive foil, and the conductive foil is supported by the intermediate layer. A recess is formed in the intermediate layer, and the external electrode is located above the recess. That is, the external electrode is not directly supported by the intermediate layer, but is floated from the intermediate layer. As a result, the external electrode can move relatively freely, so that the stress (thermal stress) caused by the difference in the coefficient of thermal expansion from the circuit board can be absorbed.
[0009]
(2) The recess may be filled with a resin having a Young's modulus lower than that of the intermediate layer.
[0010]
By doing so, the space of the concave portion can be filled, so that cracks due to the expansion of water vapor can be prevented during heating such as a reflow process.
[0011]
(3) The wiring is formed on the surface on which the passivation film is formed and located on the bottom surface of the recess of the intermediate layer,
The resin is a resin to which a conductive filler is added, and the wiring and the conductive foil may be electrically connected.
[0012]
(4) The intermediate layer has an inclined surface between the electrode and the conductive foil,
The wiring may electrically connect the electrode and the conductive foil through the inclined surface.
[0013]
(5) The intermediate layer may be formed of a flexible material.
[0014]
By doing so, the stress can be relaxed also by the intermediate layer itself.
[0015]
(6) The conductive foil may have a hole at a position inside the opening region of the concave portion and avoiding a connection portion with the external electrode.
[0016]
By doing so, the conductive foil is easily deformed, and the stress can be absorbed by the conductive foil.
[0017]
(7) In the present invention, the substrate on which the conductive foil is formed is provided with the surface on which the conductive foil is formed facing the intermediate layer,
The substrate has a through hole above the recess,
The external electrode may be formed on the conductive foil through the through hole.
[0018]
According to this, the conductive foil is covered and protected by the substrate.
[0019]
(8) In the present invention, a substrate formed of a flexible material is provided between the intermediate layer and the conductive foil.
The substrate has a through hole in a region excluding the upper portion of the recess,
The wiring and the conductive foil may be electrically connected through the through hole.
[0020]
(9) The conductive foil and the wiring may be integrally formed.
[0021]
(10) The conductive foil and the wiring may be separate.
[0022]
(11) A method of manufacturing a semiconductor device according to the present invention includes a step of preparing a semiconductor element having electrodes, and avoiding at least a part of each electrode and having a passivation film on the surface;
Above the surface on which the passivation film is formed, a conductive foil is provided at a predetermined interval in the thickness direction, and an intermediate layer that supports the conductive foil is formed between the passivation film and the conductive foil, Forming a recess recessed in the intermediate layer at a position avoiding the electrode;
Forming a wiring for electrically connecting the electrode and the conductive foil;
Forming an external electrode at a position above the recess in the conductive foil;
including.
[0023]
According to the semiconductor device manufactured by the present invention, the external electrode is formed on the conductive foil, and the conductive foil is supported by the intermediate layer. A recess is formed in the intermediate layer, and the external electrode is located above the recess. That is, the external electrode is not directly supported by the intermediate layer, but is floated from the intermediate layer. As a result, the external electrode can move relatively freely, so that the stress (thermal stress) caused by the difference in the coefficient of thermal expansion from the circuit board can be absorbed.
[0024]
(12) In the present invention, a substrate having a through hole and having the conductive foil attached thereto including the through hole is prepared,
Forming the intermediate layer on the surface on which the passivation film is formed, forming the recess in the intermediate layer;
Then, the through hole is positioned above the recess, and the conductive foil is opposed to the recess, and the substrate is placed on the intermediate layer,
The external electrode may be formed on the conductive foil through the through hole.
[0025]
According to this, since the conductive foil is affixed to the substrate, the step of forming the conductive foil can be easily performed.
[0026]
(13) In the present invention, a substrate formed of a flexible material and having a through hole is prepared,
Forming the intermediate layer on the surface on which the passivation film is formed, forming the recess in the intermediate layer, and forming the wiring in the intermediate layer;
The through hole is positioned on the wiring, the substrate is placed on the intermediate layer, the conductive foil is formed on the substrate, and the wiring and the conductive foil are electrically connected through the through hole. Also good.
[0027]
According to this, since the conductive foil is affixed to the substrate, the step of forming the conductive foil can be easily performed.
[0028]
(14) forming the intermediate layer on the surface on which the passivation film is formed, forming the conductive foil in the intermediate layer, forming a hole in the conductive foil, and etching the intermediate layer through the hole; And you may form the said recessed part.
[0029]
(15) The intermediate layer may be formed of an etchable material under conditions where the semiconductor element cannot be etched.
[0030]
By doing so, the surface of the semiconductor element can be prevented from being etched when the intermediate layer is etched.
[0031]
(16) The passivation film is etched under the etching conditions of the intermediate layer,
On the passivation film, a coating layer made of a material that is difficult to be etched under the etching conditions of the intermediate layer is formed, the intermediate layer is formed on the coating layer, the conductive foil is formed on the intermediate layer, and the conductive layer is formed. A hole may be formed in the foil, and the recess may be formed by etching the intermediate layer through the hole.
[0032]
Thus, by forming a coating layer on the passivation film, etching of the passivation film can be prevented.
[0033]
(17) The passivation film is etched under the etching conditions of the intermediate layer,
Forming a first covering layer made of a material that is difficult to be etched under the etching condition of the intermediate layer on the passivation film;
Forming the intermediate layer on the first coating layer;
Forming the conductive foil and wiring on the intermediate layer and forming a hole in the conductive foil;
Forming a solder resist layer on the wiring;
On the solder resist layer, a second coating layer made of a material that is difficult to be etched under the etching conditions of the intermediate layer is formed,
You may etch the said intermediate | middle layer through the hole of the said conductive foil until it reaches under the said conductive foil.
[0034]
(18) Before the step of etching the intermediate layer, the external electrode is formed on the conductive foil, and an electrode covering layer made of a material that is difficult to be etched under the etching condition of the intermediate layer is formed on the external electrode. A process may be included.
[0035]
According to this, after forming the external electrode, the intermediate layer is etched to form the recess. Therefore, since the etching can be performed after removing the residue generated by the formation of the external electrode, the residue does not remain in the recess.
[0036]
(19) The present invention may include a step of filling the recess with a resin having a Young's modulus lower than that of the intermediate layer.
[0037]
(20) The semiconductor device is mounted on a circuit board according to the present invention.
[0038]
(21) An electronic device according to the present invention includes the circuit board.
[0039]
DETAILED DESCRIPTION OF THE INVENTION
Preferred embodiments of the present invention will be described below with reference to the drawings.
[0040]
In addition, each drawing is shown partially enlarged for easy understanding. In the following description, the description is made on the assumption that one semiconductor device is finally made into individual pieces, and therefore terms and shapes used are slightly different from actual ones. In the following description, the term “semiconductor chip” is used to indicate an individual piece (ie, a chip shape), but the “semiconductor element” according to the present invention is not limited to a semiconductor chip. It may also refer to a wafer-like one that is not. In other words, the semiconductor element here may be a predetermined circuit that can be used even if it is separated into a base substrate made of silicon, for example. There is no particular limitation. Further, since only representative portions necessary for the description of the wiring and the like are taken up, the same components and other structures are omitted in other portions in each drawing.
[0041]
(First embodiment)
FIG. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment. The semiconductor device 10 shown in the figure is a CSP type whose package size is substantially the same as that of the semiconductor chip 12.
[0042]
An electrode 14 is formed on the active surface 12a of the semiconductor chip 12 from, for example, aluminum (Al). A passivation film 11 is formed on the semiconductor chip 12 avoiding at least a part of each electrode 14. Here, the reason for avoiding at least a part is that an electrical signal or the like needs to be derived from the electrode 14. Therefore, it is necessary for the passivation film 11 to avoid the electrode 14 to such an extent that an electrical signal or the like can be derived from the electrode 14. For example, the passivation film 11 is made of SiO. 2 , SiN, polyimide resin, or the like. An intermediate layer 16 is formed on the active surface 12a avoiding the electrode 14. Specifically, the intermediate layer 16 is formed on the passivation film 11. The intermediate layer 16 has a recess 16a, and the active surface 12a is exposed in the recess 16a. However, it is sufficient that the concave portion 16a has a concave shape, and the active surface 12a may not be exposed. The intermediate layer 16 has an inclined surface 16b inclined from the electrode 14, and a wiring 18 is formed on the intermediate layer 16 from the electrode 14 through the inclined surface 16b. The opening end of the recess 16a shown in FIG. 1 is considerably larger than the size of the root portion of the external electrode 26, but is not limited to this, and is substantially equal to or larger than the size of the root portion of the external electrode 26. I just need it. Furthermore, an opening of the recess 16a may be located at a part of the root of the external electrode 26. In this case, the opening allows deformation of the intermediate layer and can exert a stress relaxation effect. The recess 16a may penetrate the intermediate layer 16 and expose the passivation film 11 thereunder, but may leave a part of the intermediate layer 16 at the bottom of the recess 16a so as not to penetrate the intermediate layer 16. good.
[0043]
Here, the intermediate layer 16 is made of an insulating resin, for example, a polyimide resin, and has a coefficient of thermal expansion between the semiconductor chip 12 and the circuit board to be mounted when the semiconductor device 10 is mounted on a circuit board (not shown). The stress caused by the difference can be relaxed. Note that it is not an essential requirement of the present invention that the intermediate layer 16 has a stress relaxation function. The stress relaxation function is also achieved by forming the recess 16a (details will be described later).
[0044]
Further, the insulating resin is insulative with respect to the wiring 18, can protect the active surface 12a of the semiconductor chip 12, and also has heat resistance when melting solder during mounting. In consideration of adding a stress relaxation function to be described later, a polyimide resin or the like is generally used, and among them, a material having a low Young's modulus (for example, an olefin-based polyimide resin or BCB manufactured by Dow Chemical Co., Ltd. other than polyimide resin) ) Is preferable, and Young's modulus is particularly 300 kg / mm. 2 It is preferable that it is about the following. The thicker the intermediate layer 16 is, the greater the stress relaxation force becomes. However, considering the size of the semiconductor device, the manufacturing cost, etc., the thickness is preferably about 1 to 100 μm. However, Young's modulus is 300 kg / mm 2 When about a polyimide resin is used, a thickness of about 10 μm is sufficient.
[0045]
Alternatively, as the intermediate layer 16, for example, a silicone-modified polyimide resin, an epoxy resin, a silicone-modified epoxy resin, or the like may be used, and a material having a low Young's modulus and capable of relaxing stress may be used. Further, as the intermediate layer 16, a passivation layer (SiN, SiO 2 , MgO, etc.), and the stress relaxation itself may be performed by forming the recess 16a as will be described later.
[0046]
The wiring 18 is formed of, for example, copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), titanium tungsten (Ti-W) or a plurality of these layers, and a conductive layer thereon. A foil 22 is formed. The conductive foil 22 is formed on the substrate 20 in advance, and is attached to the wiring 18 together with the substrate 20 via an adhesive 24. The conductive foil 22 is also made of, for example, copper (Cu).
[0047]
The conductive foil 22 is formed to be larger than the opening end portion of the recess 16a formed in the intermediate layer 16, and is disposed so as to cover the upper portion of the recess 16a. A part of the conductive foil 22 is in contact with and electrically connected to the wiring 18. The conductive foil 22 and the wiring 18 are preferably welded by applying heat and pressure. The electrical connection between the conductive foil 22 and the wiring 18 may be performed by mechanical pressure welding with the adhesive 24 as described above, or Au, Sn, solder or the like is plated on the wiring 18 and the conductive foil 22. May be brazed, or may be connected by diffusion bonding using ultrasonic heat or the like. Therefore, it is preferable that a low temperature brazing is provided on at least one of the joint surfaces of both the conductive foil 22 and the wiring 18.
[0048]
The board | substrate 20 is a film-like thing formed with the resin etc. which have a softness | flexibility, and has the through-hole 20a in the position above the recessed part 16a. The conductive foil 22 is formed on the lower surface of the substrate 20 so as to cover the through hole 20a. An external electrode 26 is formed on the conductive foil 22 through the through hole 20a. The external electrode 26 may be formed of, for example, only solder, or may be formed by plating solder or gold on the surface of copper (Cu) or nickel (Ni).
[0049]
In addition, as the substrate 20 with the conductive foil 22, a film carrier tape or FPC (Flexible Printed Circuit) used in the TAB technology of two layers (Cu foil + polyimide substrate) or three layers (Cu foil + adhesive + polyimide substrate) is used. May be used.
[0050]
This embodiment is configured as described above, and the operation thereof will be described below. In the semiconductor device 10, the conductive foil 22 on which the external electrode 26 is formed is supported by the intermediate layer 16. However, in the intermediate layer 16, a recess 16 a is formed in a region including directly under the external electrode 26. A space is formed under the conductive foil 22 by the recess 16a. That is, in the vicinity of the joint with the external electrode 26, the conductive foil 22 is in a floating state and easily deforms. Since it is configured in this manner, when stress is applied to the external electrode 26, the conductive foil 22 and the substrate 20 are deformed to absorb the stress. Thus, when the semiconductor device is mounted on the circuit board, when the mounted circuit board or electronic device is subjected to stress due to a difference in thermal expansion coefficient between the semiconductor device (or a semiconductor chip formed from silicon) and the circuit board due to temperature change, Mechanical stress generated when bent by external stress can be absorbed. Hereinafter, stress refers to this.
[0051]
Next, FIG. 2 shows a plan view of the semiconductor device according to the present embodiment. In the figure, wirings 18 are formed from the electrodes 14 of the semiconductor chip 12 toward the center of the active surface 12a, each wiring 18 is connected to a conductive foil 22, and the conductive foil 22 is provided with an external electrode 26. The region excluding the external electrode 26 is covered and protected by the substrate 20.
[0052]
The electrode 14 is an example of a so-called peripheral electrode type located in the peripheral portion of the semiconductor chip 12, but an area array arrangement type semiconductor chip in which an electrode is formed in an inner region than the peripheral region of the semiconductor chip may be used. good.
[0053]
As shown in the figure, the external electrode 26 is provided not on the electrode 14 of the semiconductor chip 12 but in an active region of the semiconductor chip 12 (region where active elements are formed). By providing the intermediate layer 16 in the active region and further arranging (withdrawing) the wiring 18 in the active region, the external electrode 26 can be provided in the active region. That is, pitch conversion can be performed. Therefore, when the external electrode 26 is disposed, an active region, that is, a region as a fixed surface can be provided, and the degree of freedom of the setting position of the external electrode 26 is greatly increased.
[0054]
Then, by bending the wiring 18 at a necessary position, the external electrodes 26 are provided so as to be arranged in a lattice pattern. Since this is not an essential configuration of the present invention, the external electrodes 26 do not necessarily have to be arranged in a lattice pattern.
[0055]
Further, in FIG. 2, the width of the electrode 14 and the width of the wiring 18 at the junction between the electrode 14 and the wiring 18 are
Wiring 18 <electrode 14
In fact,
Electrode 14 ≦ Wiring 18
It is preferable that In particular,
Electrode 14 <Wiring 18
In this case, not only the resistance value of the wiring 18 is decreased, but also the strength is increased, so that disconnection is prevented.
[0056]
In the present embodiment, the intermediate layer 16 has a stress relaxation function, but it is possible to absorb the stress only by forming the recess 16a. Therefore, even if the intermediate layer 16 has a structure in which a layer made of a material having no stress relaxation function (for example, a simple insulating layer or protective layer) is formed, stress can be absorbed.
[0057]
Next, FIG. 3A to FIG. 3E are views for explaining a method for manufacturing a semiconductor device according to the present embodiment. First, as shown in FIG. 3A, a semiconductor chip 12 having an electrode 14 made of, for example, aluminum (Al) is prepared. A passivation film (not shown) is formed on the semiconductor chip 12 avoiding the electrodes 14. Even when the process according to the present invention is performed on a wafer-like semiconductor element, a commercially available wafer may be prepared. A polyimide resin (not shown) is provided on the active surface 12a of the semiconductor chip 12 by a method such as spin coating. Or you may affix the polyimide resin etc. which were previously made into the film form on the active surface 12a.
[0058]
Then, through a photolithography process, as shown in FIG. 3B, an intermediate layer 16 having a recess 16a is formed. In addition, when forming the recessed part 16a by photolithography, it is preferable to select the material suitable for it as the material of the intermediate | middle layer 16. FIG.
[0059]
Subsequently, as shown in FIG. 3C, a wiring 18 extending from the electrode 14 to the intermediate layer 16 is formed. For example, 100 angstroms (10 -Ten m) a titanium tungsten (Ti—W) layer, and a 1 μm copper (Cu) layer is similarly formed thereon by sputtering, and the metal film thus obtained is etched into a predetermined pattern to form a wiring 18. Form.
[0060]
Then, as illustrated in FIG. 3D, the substrate 20 is attached through the adhesive 24. A through hole 20a is formed in the substrate 20 in advance, and a conductive foil 22 is provided at a position covering the through hole 20a.
[0061]
Note that it is preferable to provide a low-temperature brazing by plating, for example, tin (Sn), gold (Au), or solder on at least one of the joint surfaces of both the conductive foil 22 and the wiring 18.
[0062]
Then, the substrate 20 is placed so that the conductive foil 22 is in contact with the wiring 18, and heat and pressure are applied from above the substrate 20. In this way, the low temperature solder is melted and the conductive foil 22 and the wiring 18 are electrically connected. This connection may be performed by applying ultrasonic waves or the like.
[0063]
Next, as illustrated in FIG. 3E, the external electrode 26 is formed on the conductive foil 22 through the through hole 20 a of the substrate 20. For example, solder balls are placed on the conductive foil 22, solder plating is stacked, solder paste is printed, copper (Cu) or nickel (Ni) or both are plated, and solder or gold (Au The external electrode 26 is formed by performing plating.
[0064]
Through the above steps, the semiconductor device 10 can be obtained. When the semiconductor chip 12 has a wafer shape, the semiconductor device 10 is obtained by performing dicing and cutting into pieces. Thereafter, the semiconductor device 10 is quality-inspected and tray-packed.
[0065]
In the present embodiment, the wiring 18 is formed on the inclined surface 16b, but may be formed on the inclined surface on the concave portion 16a side. The same applies to the following embodiments. In this way, most of the wiring 18 passes through the intermediate layer 16 and is protected, so that the device reliability is improved.
[0066]
(Second Embodiment)
FIG. 4 is a diagram illustrating a semiconductor device according to the second embodiment. The semiconductor device 30 shown in the figure is characterized in that the recess 16 a of the semiconductor device 10 shown in FIG. 1 is filled with a resin 32, and the other configuration is the same as that of the semiconductor device 10. The opening end of the recess 16a shown in FIG. 4 is considerably larger than the size of the root portion of the external electrode 26, but is not limited to this, and is substantially equal to or larger than the size of the root portion of the external electrode 26. I just need it. Furthermore, an opening of the recess 16a may be located at a part of the root of the external electrode 26. In this case, the opening allows deformation of the intermediate layer and can exert a stress relaxation effect. The recess 16a may penetrate the intermediate layer 16 and expose a passivation film (not shown) below the intermediate layer 16, but a part of the intermediate layer 16 is formed at the bottom of the recess 16a so as not to penetrate the intermediate layer 16. You may leave.
[0067]
As the resin 32, it is preferable to use a soft resin having a Young's modulus lower than that of the intermediate layer 16 among, for example, a polyimide resin, silicon gel, or rubber used as a photosensitive resist. By doing so, the space formed by the recess 16a can be filled, and therefore, cracking due to expansion of air or water vapor can be prevented during heating such as a reflow process.
[0068]
The resin 32 may be filled before the substrate 20 is attached, or a hole may be formed in the substrate 20 and the substrate 20 may be attached and then filled through the hole.
[0069]
Moreover, filling the resin into the recess as in the present embodiment can also be applied to all the following embodiments.
[0070]
(Third embodiment)
FIG. 5 is a diagram illustrating a semiconductor device according to the third embodiment. Similar to the semiconductor device 10 shown in FIG. 1, the semiconductor device 40 shown in FIG. 1 includes the semiconductor chip 12, the electrode 14, the intermediate layer 16, and the wiring 18, and the intermediate layer 16 has a recess 16 a.
[0071]
A substrate 42 is attached on the intermediate layer 16 via an adhesive 24. The substrate 42 is a film formed of a material having a low Young's modulus such as a polyimide resin mentioned as the material of the intermediate layer 16 in the first embodiment. A conductive foil 44 patterned in a wiring shape is formed on the substrate 42, and an external electrode 46 is formed on the conductive foil 44. In the substrate 42, a through hole 42 a is formed on a portion of the wiring 18 located on the intermediate layer 16. An electrical joint 48 is formed in the through hole 42a, and the conductive foil 44 and the wiring 18 are electrically connected. Also, a solder resist layer 49 is provided on the conductive foil 44 so as to avoid the external electrode 46 to protect the conductive foil 44.
[0072]
Next, a method for manufacturing the semiconductor device 40 will be described. First, through the steps shown in FIGS. 3A to 3C, the intermediate layer 16 and the wiring 18 are formed in the semiconductor chip 12, and the recess 16 a is formed in the intermediate layer 16.
[0073]
Then, the substrate 42 is bonded onto the intermediate layer 16 via the adhesive 24 to form a through hole 42 a in the substrate 42. In addition, after forming the through-hole 42a in the board | substrate 42 previously, this may be affixed.
[0074]
Next, a conductive foil 44 is formed on the substrate 42. The conductive foil 44 can be formed by, for example, sputtering, electrolytic plating, electroless plating, or the like. Photolithographic techniques may be used for patterning the conductive foil 44. Alternatively, a patterned conductive foil 44 may be provided on the substrate 42 in advance, and this may be pasted on the intermediate layer 16.
[0075]
Then, for example, the electrical joint 48 is provided in the region including the through hole 42a of the substrate 42 by electroless plating or by a method of adding electrolytic plating thereto.
[0076]
Next, a solder resist layer 49 is provided on the conductive foil 44 so as to avoid the formation region of the external electrode 46, and then the external electrode 46 is formed. The method for forming the external electrode 46 is the same as the method for forming the external electrode 26 of the first embodiment.
[0077]
Also in the semiconductor device 40 manufactured as described above, since the recess 16a is formed in the intermediate layer 16, the stress applied to the external electrode 26 can be absorbed.
[0078]
(Fourth embodiment)
FIG. 6 is a diagram illustrating a semiconductor device according to the fourth embodiment. As in the semiconductor device 10 shown in FIG. 1, the semiconductor device 50 shown in FIG. 1 has an intermediate layer 56 formed on a semiconductor chip 52 having electrodes 54, and a concave portion 56 a is formed in the intermediate layer 56. A wiring 58 is formed from the electrode 54 to the intermediate layer 56, and a conductive foil 60 is formed on the intermediate layer 56 integrally with the wiring 58. At least one hole 60 a is formed in the conductive foil 60. An external electrode 62 is formed in a region on the concave portion 56 a in the conductive foil 60. Further, avoiding the external electrode 62, a solder resist layer 64 is formed on the wiring 58 and the conductive foil 60 to protect them.
[0079]
This embodiment is characterized by its manufacturing method. FIG. 7A to FIG. 8C are views for explaining a method for manufacturing a semiconductor device according to this embodiment.
[0080]
In this embodiment, since no substrate is used, it is preferable to form the intermediate layer 56, the external electrode 62, and the like on the wafer and then cut the wafer. On the other hand, in the form using the substrate (first to third embodiments), the tape-like substrate can be attached to the individual semiconductor chip.
[0081]
First, as shown in FIG. 7A, an intermediate layer 56 is formed on the active surface 52a of the semiconductor chip 52 while avoiding the electrodes 54. The intermediate layer 56 is formed of the same material as the intermediate layer 16 shown in FIG. When the intermediate layer 56 is formed of a material having a low Young's modulus, the intermediate layer 56 also performs a stress relaxation function. Alternatively, the intermediate layer 56 may be formed of a hard material that does not perform the stress relaxation function (for example, an inorganic material such as magnesium oxide (MgO)).
[0082]
The intermediate layer 56 is preferably different in material from the semiconductor passivation film so that the active surface 52a of the semiconductor chip 52 is not etched when the intermediate layer 56 is etched in a later step. For this purpose, the intermediate layer 56 is preferably formed of a material that can be etched under the condition that the substance exposed on the surface of the semiconductor chip 52 is not etched.
[0083]
Next, as illustrated in FIG. 7B, a metal film 66 is formed from the electrode 54 to the intermediate layer 56. The manufacturing method is the same as the metal film forming method for forming the wiring 18 of the first embodiment. In this case, since the stress of the external terminal 62 described later is directly applied to the wiring 58, the thickness of the wiring 58 is preferably about 5 to 20 μm. The metal film 66 is etched in a process described later to form the wiring 58 and the conductive foil 60.
[0084]
Next, as shown in FIG. 7C, a hole 60a is formed in a portion of the metal film 66 to be the conductive foil 60, and the intermediate layer 56 is removed from the intermediate layer 56 through the hole 60a as an etching solution or etching gas (etchant). Expose to. For example, when the intermediate layer 56 is formed of a resin such as polyimide, the etchant may be a strong alkaline aqueous solution such as K0H, O 2 2 Or CF Four In the case where the intermediate layer 56 is formed of magnesium oxide (MgO) or the like, a hot phosphoric acid aqueous solution or the like is preferable. Thereafter, the etchant is removed as necessary. In particular, in the case of a wet process, it is preferable to add a water washing and rinsing step. Thus, as shown in FIG. 7D, the intermediate layer 56 is etched to form the recesses 56a.
[0085]
Subsequently, as shown in FIG. 8A, the metal film 66 is patterned to form the wiring 58 and the conductive foil 60. Then, a solder resist layer 64 is formed as shown in FIG. 8B, and an external electrode 62 is formed as shown in FIG. 8C. As the solder resist, a photosensitive polyimide resin or an epoxy resin dry film is often used. The method for forming the external electrode 62 is the same as in the first embodiment. Thus, the semiconductor device 50 is obtained. Also in the present embodiment, the same effect as in the first embodiment can be achieved.
[0086]
Furthermore, in the semiconductor device 50 manufactured according to the present embodiment, since the hole 60a is formed in the conductive foil 60, the conductive foil 60 is easily deformed. Therefore, the effect of absorbing stress by the conductive foil 60 that has floated on the recess 56a is further enhanced.
[0087]
(Fifth embodiment)
FIG. 9A to FIG. 9C are views showing a method for manufacturing a semiconductor device according to the fifth embodiment.
[0088]
In the present embodiment, as shown in FIG. 9A, an intermediate layer 76 is formed on a semiconductor chip 72 having electrodes 74. A conductive foil 80 is formed on the intermediate layer 76, and a wiring 78 is formed so as to reach the electrode 74 from the conductive foil 80. A solder resist layer 84 is formed on the wiring 78 and the conductive foil 80. Further, a hole 80 a is formed in the conductive foil 80.
[0089]
The formation method of the intermediate layer 76 is the same as the method shown in FIG. 7A, and the formation method of the wiring 78, the hole 80a, and the conductive foil 80 is the same as the method shown in FIG. 7B to FIG. The same. The solder resist layer 84 is formed in a region that avoids the external electrode 82 (see FIG. 9B).
[0090]
Then, after forming the external electrode 82 on the conductive foil 80 and removing the residue generated along with this, the covering layer 86 is formed on the external electrode 82 and the solder resist layer 84 (see FIG. 9B). ). The covering layer 86 is formed of a material that is difficult to be etched under the etching conditions of the intermediate layer 76.
[0091]
Subsequently, a recess 76a is formed in the intermediate layer 76 through the hole 80a of the conductive foil 80, and the covering layer 86 is removed, as shown in FIG. A semiconductor device 70 is obtained.
[0092]
According to the present embodiment, since the recess 76a is formed in the intermediate layer 76 after removing the residue generated when the external electrode 82 is formed, no residue remains in the recess 76a. The features of the semiconductor device 70 manufactured according to the present embodiment are the same as those of the fourth embodiment.
[0093]
(Sixth embodiment)
FIG. 10A to FIG. 10C are views showing a method for manufacturing a semiconductor device according to the sixth embodiment.
[0094]
In this embodiment, as shown in FIG. 10A, a semiconductor chip 102 in which a passivation film 106 is formed on an active surface 102a avoiding the electrode 104 is used. The passivation film 106 is formed using a material having properties common to those of the intermediate layer 108 illustrated in FIG. That is, the passivation film 106 is formed of a material that is etched under the etching conditions of the intermediate layer 108. For example, the case where both the intermediate layer 108 and the passivation film 106 are formed of polyimide resin is applicable.
[0095]
In such a case, as shown in FIG. 10B, the covering layer 118 is formed on the passivation film 106 at least below the recess 108a (see FIG. 10C). The covering layer 118 is formed of a material that is not etched under the etching conditions of the intermediate layer 108 and the passivation film 106. For example, when the intermediate layer 108 and the passivation film 106 are formed of a polyimide resin, the coating layer 118 may be a metal thin film such as Cr, Ti—W, or Ti.
[0096]
Thereafter, by the same process as shown in FIGS. 7A to 8C, as shown in FIG. 10C, the intermediate layer 108 having the recess 108a, the wiring 110, and the conductive foil 112 having the hole 112a. Then, the external electrode 114 and the solder resist layer 116 are formed.
[0097]
According to the present embodiment, since the passivation film 106 is covered with the covering layer 118, it is possible to prevent the passivation film 106 from being etched when the intermediate layer 108 is etched to form the recess 108a. Thus, the active element can be prevented from being exposed in the recess 108a. The characteristic regarding the stress relaxation function is the same as that of the above-described embodiment.
[0098]
(Seventh embodiment)
FIG. 11A and FIG. 11B are diagrams illustrating a part of the semiconductor device according to the seventh embodiment. Note that FIG. 11B is a cross-sectional view taken along line BB in FIG. In the semiconductor device 120 according to the present embodiment, holes 122 and 124 are formed in the substrate 20 and the conductive foil 22 in the semiconductor device 10 shown in FIG.
[0099]
According to the present embodiment, since the holes 122 and 124 are formed, the substrate 20 and the conductive foil 22 are easily deformed, and the stress relaxation function is enhanced.
[0100]
(Eighth embodiment)
FIG. 12 is a diagram illustrating a semiconductor device according to the eighth embodiment. In the semiconductor device 130 shown in the figure, a wiring 136 is formed from an electrode 134 on an active surface 132 a of a semiconductor chip 132. An intermediate layer 138 is formed on the wiring 136. A recess 138 a is formed in the intermediate layer 138 so that the wiring 136 is exposed at a position on the wiring 136. A substrate 146 is provided on the intermediate layer 138 with an adhesive 142 interposed therebetween. A conductive foil 144 is formed on the substrate 146 at a position above the recess 138a and on a surface facing the recess 138a. Further, a through hole 146a is formed in the substrate 146 above the recess 138a so that the conductive foil 144 is exposed from the opposite surface. An external electrode 148 is formed through the through hole 146a.
[0101]
Further, the conductive paste 140 is filled in the recess 138a. In the conductive paste 140, a conductive filler such as silver (Ag), copper (Cu), silver-plated copper, or gold (Au) is added to a soft resin similar to the resin 32 filled in the recess 16a shown in FIG. Is. With this conductive paste 140, the wiring 136 and the conductive foil 144 are electrically connected.
[0102]
Also in the present embodiment, the recess 138 a is formed in the intermediate layer 138, so that the stress relaxation function can be achieved.
[0103]
(Ninth embodiment)
FIG. 13A to FIG. 14B are views showing a method for manufacturing a semiconductor device according to the ninth embodiment. In the present embodiment, a semiconductor chip 152 in which a passivation film (not shown) is formed on the active surface 152a is used as in the semiconductor chip 102 shown in FIG. This passivation film is formed from a material that is etched under the etching conditions of the intermediate layer 158.
[0104]
As shown in FIG. 13A, a coating layer 156 is formed on the passivation film on the active surface 152a. The covering layer 156 is formed of a material that is not etched under the etching conditions of the intermediate layer 158 (for example, chromium (Cr), titanium (Ti), titanium tungsten (Ti—W), or copper (Cu)). The covering layer 156 is formed by sputtering, for example.
[0105]
Next, as illustrated in FIG. 13B, an intermediate layer 158 is formed including the coating layer 156 and avoiding the electrode 154. The material of the intermediate layer 158 is the same as that in the first embodiment.
[0106]
Then, as illustrated in FIG. 13C, a wiring 160 is formed from the electrode 154 to the intermediate layer 158, and a conductive foil 162 is formed so as to be electrically connected to the wiring 160. Specifically, chromium (Cr), titanium (Ti), titanium tungsten (Ti-W), copper (Cu), or a metal film in which a plurality of these are laminated is formed by sputtering, and this is etched. Then, the wiring 160 and the conductive foil 162 are integrally formed. In addition, a hole 162 a is formed in the conductive foil 162.
[0107]
Subsequently, as illustrated in FIG. 13D, the external electrode 164 is formed over the conductive foil 162. Specifically, bumps in which copper (Cu), nickel (Ni), gold (Au), or a plurality of these are laminated are formed on the conductive foil 162 by electrolytic plating or electroless plating, An electrode 164 is formed.
[0108]
Then, as illustrated in FIG. 14A, a solder resist layer 166 is formed over the wiring 160, and a coating layer 168 is formed over the solder resist layer 166. The covering layer 168 is also formed of a material that is not etched under the etching conditions of the intermediate layer 158 (for example, chromium (Cr), titanium (Ti), titanium tungsten (Ti-W), or copper (Cu)).
[0109]
Then, as shown in FIG. 14B, a recess 158a is formed in the intermediate layer 158. The process is similar to the process shown in FIG. Further, the covering layer 168 is removed by etching. In this example, there is an opening at the center of the external electrode 164, but an opening design as in the seventh embodiment may be used.
[0110]
Through the above steps, the semiconductor device 150 can be obtained. The semiconductor device 150 also has a stress relaxation function by forming the recess 158 a in the intermediate layer 158.
[0111]
Instead of the bump-like external electrode 164 of the semiconductor device 150 shown in FIG. 14B, as shown in FIG. 15, the external electrode made of a solder ball is formed on the end of the conductive foil 162 where the hole 162a is formed. 170 may be formed.
[0112]
Note that the present invention is not limited to the CSP type semiconductor device. For example, if a deformed portion is directly laminated on an electrode of a semiconductor chip, a semiconductor device having a stress relaxation function while having the same size as a flip chip can be obtained.
[0113]
FIG. 16 shows a circuit board 1000 on which the semiconductor device 1100 manufactured by the method according to the above-described embodiment is mounted. As the circuit board 1000, an organic substrate such as a glass epoxy substrate is generally used. On the circuit board 1000, for example, a wiring pattern made of copper is formed so as to form a desired circuit, and solder balls are provided on the circuit board 1000. Then, the solder balls of the wiring pattern and the external electrodes of the semiconductor device 1100 are mechanically connected to achieve electrical conduction therebetween.
[0114]
In this case, since the semiconductor device 1100 is provided with a structure that absorbs distortion caused by a difference in thermal expansion with the outside, even when the semiconductor device 1100 is mounted on the circuit board 1000, reliability at the time of connection and thereafter is improved. Can be improved.
[0115]
Note that the mounting area can be reduced to the area mounted by the bare chip. For this reason, if this circuit board 1000 is used for an electronic device, the electronic device itself can be reduced in size. Further, it is possible to secure a mounting space within the same area, and it is possible to achieve high functionality.
[0116]
As an electronic device including the circuit board 1000, a notebook personal computer 1200 is shown in FIG.
[0117]
Note that the present invention can also be applied to various electronic components for surface mounting regardless of whether they are active components or passive components. Examples of the electronic component include a resistor, a capacitor, a coil, an oscillator, a filter, a temperature sensor, a thermistor, a varistor, a volume, or a fuse.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment.
FIG. 2 is a plan view showing the semiconductor device according to the first embodiment.
FIG. 3A to FIG. 3E are views showing a method for manufacturing a semiconductor device according to the first embodiment.
FIG. 4 is a diagram illustrating a semiconductor device according to a second embodiment.
FIG. 5 is a diagram illustrating a semiconductor device according to a third embodiment.
FIG. 6 is a diagram illustrating a semiconductor device according to a fourth embodiment.
FIGS. 7A to 7D are views for explaining a method for manufacturing a semiconductor device according to a fourth embodiment;
FIGS. 8A to 8C are views for explaining a method for manufacturing a semiconductor device according to the fourth embodiment;
FIG. 9A to FIG. 9C are views showing a method for manufacturing a semiconductor device according to a fifth embodiment.
FIG. 10A to FIG. 10C are views showing a method for manufacturing a semiconductor device according to a sixth embodiment.
FIGS. 11A and 11B are views showing a semiconductor device according to a seventh embodiment.
FIG. 12 is a diagram illustrating a semiconductor device according to an eighth embodiment.
FIG. 13A to FIG. 13D are views showing a method for manufacturing a semiconductor device according to a ninth embodiment.
FIG. 14A and FIG. 14B are views showing a method for manufacturing a semiconductor device according to a ninth embodiment.
FIG. 15 is a diagram showing a modification of the ninth embodiment.
FIG. 16 is a view showing a circuit board on which the semiconductor device according to the embodiment is mounted;
FIG. 17 is a diagram illustrating an electronic apparatus including a circuit board on which the semiconductor device according to the embodiment is mounted.
[Explanation of symbols]
10 Semiconductor devices
11 Passivation film
12 Semiconductor chip
12a Active surface
14 electrodes
16 Middle layer
16a recess
18 Wiring
20 substrates
20a Through hole
22 Conductive foil
26 External electrode

Claims (21)

電極を有する半導体素子と、
それぞれの電極の少なくとも一部を避けて前記半導体素子の表面上に設けられるパッシベーション膜と、
前記パッシベーション膜が形成された面の上方において、厚み方向に所定の間隔をあけて設けられる導電箔と、
前記電極の上方を避けて前記導電箔上に形成される外部電極と、
前記電極を避けて前記パッシベーション膜と前記導電箔との間に形成されるとともに前記導電箔を支持する中間層と、
前記電極と前記導電箔とを電気的に接続する配線と、を有し、
前記中間層には、前記導電箔における前記外部電極との接合部を含む領域の下方に、前記電極を避けて、前記パッシベーション膜と前記導電箔との間に開口領域となる凹部が形成され、
前記導電箔は、前記凹部上の部分が前記電極上を避けるように設けられている半導体装置。A semiconductor element having an electrode;
A passivation film provided on the surface of the semiconductor element avoiding at least a part of each electrode;
Above the surface on which the passivation film is formed, a conductive foil provided at a predetermined interval in the thickness direction;
An external electrode formed on the conductive foil avoiding the top of the electrode;
An intermediate layer that is formed between the passivation film and the conductive foil while avoiding the electrode and supports the conductive foil;
A wiring for electrically connecting the electrode and the conductive foil;
In the intermediate layer, below the region including the joint portion with the external electrode in the conductive foil, a recess serving as an open region is formed between the passivation film and the conductive foil, avoiding the electrode,
The said conductive foil is a semiconductor device provided so that the part on the said recessed part may avoid on the said electrode. 請求項１記載の半導体装置において、
前記凹部内には、前記中間層よりもヤング率が低い樹脂が充填されている半導体装置。The semiconductor device according to claim 1,
A semiconductor device in which the recess is filled with a resin having a Young's modulus lower than that of the intermediate layer. 請求項２記載の半導体装置において、
前記配線は、前記パッシベーション膜が形成された面上に形成されるとともに前記中間層の凹部の底面に位置し、
前記樹脂は、導電フィラーが添加されたものであって、前記配線と前記導電箔とを電気的に接続する半導体装置。The semiconductor device according to claim 2,
The wiring is formed on the surface on which the passivation film is formed and located on the bottom surface of the concave portion of the intermediate layer,
The resin is a semiconductor device to which a conductive filler is added, and electrically connects the wiring and the conductive foil. 請求項１又は請求項２記載の半導体装置において、
前記中間層は、前記電極と前記導電箔との間に傾斜面を有し、
前記配線は、前記傾斜面を通って前記電極と前記導電箔とを電気的に接続する半導体装置。The semiconductor device according to claim 1 or 2,
The intermediate layer has an inclined surface between the electrode and the conductive foil,
The wiring is a semiconductor device that electrically connects the electrode and the conductive foil through the inclined surface. 請求項１から請求項４のいずれかに記載の半導体装置において、
前記中間層は、柔軟性を有する材料から形成される半導体装置。The semiconductor device according to any one of claims 1 to 4,
The intermediate layer is a semiconductor device formed of a flexible material. 請求項１から請求項５のいずれかに記載の半導体装置において、
前記導電箔は、前記凹部の開口領域の内側の位置であって前記外部電極との接続部を避ける位置に、穴を有する半導体装置。The semiconductor device according to any one of claims 1 to 5,
The semiconductor device, wherein the conductive foil has a hole at a position inside the opening region of the recess and avoiding a connection portion with the external electrode. 請求項１から請求項６のいずれかに記載の半導体装置において、
前記導電箔が形成された基板が、前記導電箔が形成された面を前記中間層に向けて設けられており、
前記基板は、前記凹部の上方に貫通穴を有し、
前記貫通穴を介して前記導電箔に前記外部電極が形成される半導体装置。The semiconductor device according to any one of claims 1 to 6,
The substrate on which the conductive foil is formed is provided with the surface on which the conductive foil is formed facing the intermediate layer,
The substrate has a through hole above the recess,
A semiconductor device in which the external electrode is formed on the conductive foil through the through hole. 請求項１から請求項６のいずれかに記載の半導体装置において、
前記中間層と前記導電箔との間に、柔軟性を有する材料から形成される基板が設けられ、
前記基板は、前記凹部の上方を除く領域に貫通穴を有し、
前記貫通穴を介して前記配線と前記導電箔とが電気的に接続される半導体装置。The semiconductor device according to any one of claims 1 to 6,
A substrate formed from a flexible material is provided between the intermediate layer and the conductive foil,
The substrate has a through hole in a region excluding the upper portion of the recess,
A semiconductor device in which the wiring and the conductive foil are electrically connected through the through hole. 請求項１から請求項８のいずれかに記載の半導体装置において、
前記導電箔と前記配線とは、一体的に形成されている半導体装置。The semiconductor device according to any one of claims 1 to 8,
The conductive foil and the wiring are semiconductor devices formed integrally. 請求項１から請求項８のいずれかに記載の半導体装置において、
前記導電箔と前記配線とは、別体である半導体装置。The semiconductor device according to any one of claims 1 to 8,
The conductive foil and the wiring are separate semiconductor devices. 電極を有し、それぞれの電極の少なくとも一部を避けて表面上にパッシベーション膜が設けられた半導体素子を用意する工程と、
前記パッシベーション膜が形成された面の上方に、厚み方向に所定の間隔をあけて導電箔を設け、前記パッシベーション膜と前記導電箔との間に前記導電箔を支持する中間層を形成し、前記中間層に、前記導電箔の下方であって前記電極を避ける位置でくぼむ凹部を形成する工程と、
前記電極と前記導電箔とを電気的に接続する配線を形成する工程と、
前記導電箔における前記凹部の上方位置に外部電極を形成する工程と、
を含み、
前記導電箔を、前記凹部上の部分が前記電極上を避けるように設ける半導体装置の製造方法。Preparing a semiconductor element having electrodes, and avoiding at least a part of each electrode, and having a passivation film on the surface;
Above the surface on which the passivation film is formed, a conductive foil is provided at a predetermined interval in the thickness direction, and an intermediate layer that supports the conductive foil is formed between the passivation film and the conductive foil, Forming a recess recessed in the intermediate layer at a position below the conductive foil and avoiding the electrode;
Forming a wiring for electrically connecting the electrode and the conductive foil;
Forming an external electrode at a position above the recess in the conductive foil;
Including
A method of manufacturing a semiconductor device, wherein the conductive foil is provided so that a portion on the concave portion avoids the electrode. 請求項１１記載の半導体装置の製造方法において、
貫通穴を有し、かつ、前記貫通穴上を含めて前記導電箔が貼り付けられた基板を用意し、
前記パッシベーション膜が形成された面上に前記中間層を形成し、前記中間層に前記凹部を形成し、
その後、前記貫通穴を前記凹部の上方に位置させて、かつ、前記導電箔を前記凹部に対向させて、前記基板を前記中間層に載せ、
前記貫通穴を介して前記導電箔に前記外部電極を形成する半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 11.
A substrate having a through hole and having the conductive foil pasted on the through hole is prepared,
Forming the intermediate layer on the surface on which the passivation film is formed, forming the recess in the intermediate layer;
Then, the through hole is positioned above the recess, and the conductive foil is opposed to the recess, and the substrate is placed on the intermediate layer,
A method of manufacturing a semiconductor device, wherein the external electrode is formed on the conductive foil through the through hole. 請求項１１記載の半導体装置の製造方法において、
柔軟性を有する材料から形成されて貫通穴を有する基板を用意し、
前記パッシベーション膜が形成された面上に前記中間層を形成し、前記中間層に前記凹部を形成し、かつ、前記中間層に前記配線を形成し、
前記配線上に前記貫通穴を位置させて前記基板を前記中間層に載せ、前記基板に前記導電箔を形成し、前記貫通穴を介して前記配線と前記導電箔とを電気的に接続する半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 11.
Prepare a substrate having a through hole formed from a flexible material,
Forming the intermediate layer on the surface on which the passivation film is formed, forming the recess in the intermediate layer, and forming the wiring in the intermediate layer;
A semiconductor that positions the through hole on the wiring, places the substrate on the intermediate layer, forms the conductive foil on the substrate, and electrically connects the wiring and the conductive foil through the through hole Device manufacturing method. 請求項１１記載の半導体装置の製造方法において、
前記パッシベーション膜が形成された面上に前記中間層を形成し、前記中間層に前記導電箔を形成し、前記導電箔に穴を形成し、前記穴を介して前記中間層をエッチングして前記凹部を形成する半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 11.
Forming the intermediate layer on the surface on which the passivation film is formed, forming the conductive foil in the intermediate layer, forming a hole in the conductive foil, and etching the intermediate layer through the hole; A method of manufacturing a semiconductor device for forming a recess. 請求項１４記載の半導体装置の製造方法において、
前記中間層は、前記半導体素子のエッチングが不可能な条件下で、エッチング可能な材料で形成される半導体装置の製造方法。15. The method of manufacturing a semiconductor device according to claim 14,
The method for manufacturing a semiconductor device, wherein the intermediate layer is formed of an etchable material under conditions where the semiconductor element cannot be etched. 請求項１１記載の半導体装置の製造方法において、
前記パッシベーション膜は、前記中間層のエッチング条件下でエッチングされるものであり、
前記パッシベーション膜上に、前記中間層のエッチング条件下でエッチングされにくい材料からなる被覆層を形成し、前記被覆層に前記中間層を形成し、前記中間層に前記導電箔を形成し、前記導電箔に穴を形成し、前記穴を介して前記中間層をエッチングして前記凹部を形成する半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 11.
The passivation film is etched under the etching conditions of the intermediate layer,
On the passivation film, a covering layer made of a material that is difficult to be etched under the etching conditions of the intermediate layer is formed, the intermediate layer is formed on the covering layer, the conductive foil is formed on the intermediate layer, and the conductive layer is formed. A method of manufacturing a semiconductor device, wherein a hole is formed in a foil, and the intermediate layer is etched through the hole to form the recess. 請求項１１記載の半導体装置の製造方法において、
前記パッシベーション膜は、前記中間層のエッチング条件下でエッチングされるものであり、
前記パッシベーション膜上に、前記中間層のエッチング条件下でエッチングされにくい材料からなる第１の被覆層を形成し、
前記第１の被覆層上に前記中間層を形成し、
前記中間層上に前記導電箔及び配線を形成するとともに前記導電箔に穴を形成し、
前記配線上にソルダレジスト層を形成し、
前記ソルダレジスト層上に、前記中間層のエッチング条件下でエッチングされにくい材料からなる第２の被覆層を形成し、
前記導電箔の穴を介して前記導電箔の下に至るまで前記中間層をエッチングする半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 11.
The passivation film is etched under the etching conditions of the intermediate layer,
Forming a first covering layer made of a material that is difficult to be etched under the etching condition of the intermediate layer on the passivation film;
Forming the intermediate layer on the first coating layer;
Forming the conductive foil and wiring on the intermediate layer and forming a hole in the conductive foil;
Forming a solder resist layer on the wiring;
On the solder resist layer, a second coating layer made of a material that is difficult to be etched under the etching conditions of the intermediate layer is formed,
A method for manufacturing a semiconductor device, wherein the intermediate layer is etched through a hole in the conductive foil to reach under the conductive foil. 請求項１４から請求項１７のいずれかに記載の半導体装置の製造方法において、
前記中間層をエッチングする工程の前に、前記導電箔に前記外部電極を形成し、前記外部電極に、前記中間層のエッチング条件下でエッチングされにくい材料からなる電極被覆層を形成する工程を含む半導体装置の製造方法。In the manufacturing method of the semiconductor device in any one of Claims 14-17,
Before the step of etching the intermediate layer, the method includes forming the external electrode on the conductive foil, and forming an electrode covering layer made of a material that is difficult to be etched under the etching condition of the intermediate layer on the external electrode. A method for manufacturing a semiconductor device. 請求項１１から請求項１８のいずれかに記載の半導体装置の製造方法において、
前記凹部に、前記中間層よりもヤング率が低い樹脂を充填する工程を含む半導体装置の製造方法。In the manufacturing method of the semiconductor device in any one of Claims 11-18,
A method for manufacturing a semiconductor device, comprising filling the recess with a resin having a Young's modulus lower than that of the intermediate layer. 請求項１から請求項１０のいずれかに記載の半導体装置が実装された回路基板。  A circuit board on which the semiconductor device according to claim 1 is mounted. 請求項２０記載の回路基板を有する電子機器。  An electronic device having the circuit board according to claim 20.
JP07528299A 1998-03-23 1999-03-19 Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus Expired - Fee Related JP3753218B2 (en)

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