JP3695920B2 - Carrier wave reproducing circuit and carrier wave reproducing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a carrier recovery circuit used for synchronous demodulation of a digital modulated wave, and more particularly to a carrier recovery circuit having a frequency control loop and a phase locked loop.
[0002]
[Prior art]
In digital communication and digital broadcasting, if synchronous demodulation is performed when demodulating a digital modulated wave such as a QPSK (4-phase phase shift keying) modulated wave on the receiving side, the error rate of the demodulated data is smaller than in the case of asynchronous demodulation. It is known that it can be done. In synchronous demodulation, it is necessary to regenerate a carrier wave from an input modulated wave.
[0003]
Japanese Patent Application Laid-Open No. 6-78009 shows the basic configuration of a carrier recovery circuit used for synchronous demodulation of such a digital modulated wave as shown in FIG. In this carrier wave recovery circuit, a frequency control loop (AFC loop) and a phase locked loop (PLL loop) are used in combination, and the frequency error is first removed by AFC operation so that the frequency of the recovered carrier wave falls within the phase pull-in range of the PLL loop. After that, the phase error of the reproduced carrier wave is removed by the PLL loop, and the reproduced carrier wave is phase-synchronized with the input modulated wave. This series of operations is carrier wave recovery. Here, in a situation where the reception state is poor due to co-channel interference or the like, or in a situation where the C / N (carrier noise ratio) is low, the frequency error cannot be sufficiently removed by the AFC operation, so that the carrier wave can be correctly reproduced. become unable.
[0004]
Therefore, in order to enable carrier recovery even in such a poor reception state, a technique for performing carrier recovery by alternately operating the AFC loop and the PLL loop is described in Japanese Patent Laid-Open No. 7-30602. . In this case, since the frequency sweep operation of the regenerated carrier wave by AFC needs to be performed at a low speed so that the PLL loop can follow, there is a problem that the pull-in time until the frequency of the regenerated carrier wave reaches a predetermined frequency becomes long.
[0005]
[Means for Solving the Invention]
As described above, in the conventional carrier recovery circuit in which the frequency error is removed to the extent that the frequency of the recovered carrier falls within the pull-in range of the PLL loop by the AFC operation, and then the phase error of the recovered carrier is removed by the PLL loop. When the reception condition is bad, there is a problem that the frequency error cannot be sufficiently removed by the AFC operation, and it is difficult to perform the carrier wave reproduction, and the AFC loop and the PLL loop are alternately operated repeatedly. In the carrier wave recovery circuit, it is necessary to perform the sweep operation by AFC at a low speed so that the PLL loop can follow, so there is a problem that the pull-in time becomes long.
[0006]
An object of the present invention is to provide a carrier recovery circuit that solves such problems and can perform good carrier recovery even under a bad reception condition of a modulated wave, and can increase the pull-in time. .
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides first frequency conversion means for generating a first frequency conversion signal by multiplying an input modulated wave by a first local oscillation signal, and first frequency conversion A frequency control means for detecting the frequency error of the signal and controlling the frequency of the first local oscillation signal so as to reduce the frequency error; and multiplying the first frequency conversion signal by the second local oscillation signal. Second frequency conversion means for generating a second frequency conversion signal, and detecting a phase error of the second frequency conversion signal, and controlling the phase of the second local oscillation signal so as to reduce the phase error. Phase synchronization means for synchronizing the phase with the modulated wave, offset applying means for applying an offset to the frequency of the first local oscillation signal or the second local oscillation signal, and the phase control means after operating the frequency control means Operate the phase The offset supply means when the period has not been established An offset is given in one of the positive direction and the negative direction with respect to the frequency of the first local oscillation signal. Control to operate the phase synchronization means again after operating. If phase synchronization is not established by the control, the offset applying means is operated so as to apply an offset in the other of the plus direction and the minus direction with respect to the frequency of the first local oscillation signal. Control to operate the phase synchronization means again from And a control means.
[0008]
In the carrier recovery circuit of the present invention configured as described above, even in a situation where the reception state of the modulated wave is poor due to transmission interference such as co-channel interference and the phase cannot be pulled in by the PLL operation, the first or second By applying an offset to the frequency of the local oscillation signal, the phase can be pulled in by another PLL operation.
[0009]
Further, in the conventional method of driving into the PLL pull-in range only by the sweep operation by AFC, it is necessary to perform the sweep operation slowly. However, when the offset is applied to drive into the pull-in range as in the present invention, the AFC is performed. The operation can be performed at high speed, and the pull-in time, that is, the time required to establish synchronization is shortened.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing the configuration of a digital demodulator including a carrier recovery circuit according to the first embodiment of the present invention.
[0011]
In FIG. 1, a QPSK modulated wave is input to the input terminal 1 as a digital modulated wave. This QPSK modulated wave is input to the in-phase detector 2 and the quadrature detector 3, and the output of the local oscillator 5 having a fixed frequency is passed through the distributor 4 including a 90 ° phase shifter to obtain 0 ° phase and 90 ° phase. Respectively multiplied by the local oscillation signal. The outputs of the in-phase detector 2 and the quadrature detector 3 are digitized by A / D converters 6 and 7, respectively. Outputs of the A / D converters 6 and 7 are input to a first complex multiplier 8 and multiplied by a first local oscillation signal having a sine and cosine characteristic generated by an AFC loop described later, whereby an I signal And the first frequency conversion signal consisting of the Q signal.
[0012]
The first frequency conversion signal output from the first complex multiplier 8 is input to the digital low-pass filters 9 and 10. The digital low-pass filters 9 and 10 have a transfer characteristic for preventing intersymbol interference in digital data transmission, and are generally designed so as to obtain a so-called roll-off characteristic when combined with a filter characteristic on the transmission side. Yes. As a result, the first frequency conversion signal from the first complex multiplier 8 is spectrally shaped by the digital low-pass filters 9 and 10 so that the eye opening ratio becomes sufficiently large.
[0013]
The outputs of the digital low-pass filters 9 and 10 are input to a second complex multiplier 11 and multiplied by a second local oscillation signal having a sine and cosine characteristic generated by a PLL loop, which will be described later. And a second frequency conversion signal composed of the Q signal. The second complex multiplier 11 realizes the same operation as the frequency converter in the intermediate frequency band in the baseband. That is, since the real number type multiplier cannot realize a negative frequency component and cannot be a frequency converter, a complex multiplier is used in this embodiment.
[0014]
The second frequency conversion signal output from the second complex multiplier 11 is input to the clock recovery circuit 12, the data recovery circuit 13, the phase detector 16, and the amplitude distribution detection circuit 25. The clock recovery circuit 12 recovers the clock signal by extracting the symbol timing component in the second frequency conversion signal. The regenerated clock signal is fed back to the A / D converters 9 and 10 as a conversion clock. The data reproduction circuit 13 discriminates and reproduces the second frequency conversion signal, binarizes it into an I signal and a Q signal, and outputs it to the output terminals 14 and 15 as I and Q demodulated data.
[0015]
The phase detector 16 detects the phase error of the second frequency conversion signal and detects the phase error, in other words, the phase error of the second local oscillation signal from the PLL loop described later. The phase error signal output from the phase detector 16 is further input to the frequency detector 17, where the frequency error of the first frequency conversion signal output from the first complex multiplier 8, in other words, will be described later. A frequency error of the first local oscillation signal from the AFC loop is detected.
[0016]
The frequency error signal output from the frequency detector 17 is smoothed by an AFC loop filter 18 formed of a digital filter, and further supplied to a frequency control terminal of a numerically controlled oscillator 20 via an offset addition circuit 19 described later. The numerically controlled oscillator 20 is a circuit whose output frequency is changed by a digital signal supplied to a frequency control terminal. That is, the numerically controlled oscillator 20 is configured by a cumulative addition circuit that does not prohibit overflow, and enters an oscillation state by performing an addition operation up to its dynamic range in accordance with the value of the control signal input to the frequency control terminal. Changes depending on the value of the control signal, and thus operates in the same manner as a VCO (voltage controlled oscillator) in an analog circuit. Since the output of the numerically controlled oscillator 20 is a sawtooth signal, it is converted into a signal having a sine and cosine characteristic by the data converter 21 and becomes a first local oscillation signal. The data converter 21 is realized by a ROM, for example.
[0017]
Here, the first complex multiplier 8 to the digital low-pass filter 9 and 10 to the second complex multiplier 11 to the phase detector 16 to the frequency detector 17 to the AFC loop filter 18 to the offset adding circuit 19 to the numerically controlled oscillator. The loop from 20 to the data converter 21 to the first complex multiplier 8 constitutes an AFC loop.
[0018]
On the other hand, the phase error signal output from the phase detector 16 is smoothed by the PLL loop filter 22 formed of a digital filter and then supplied to the frequency control terminal of the numerically controlled oscillator 23. Similar to the numerical controller 20 of the AFC loop, the numerically controlled oscillator 23 is a circuit whose output frequency is changed by a digital signal supplied to the frequency control terminal. Since the output of the numerically controlled oscillator 23 is also a sawtooth signal, it is converted into a signal of sine and cosine characteristics by a data converter 24 realized by a ROM, for example, and becomes a second local oscillation signal.
[0019]
Here, the loop of the second complex multiplier 11 to the phase detector 16 to the PLL loop filter 22 to the numerical control oscillator 23 to the data converter 24 to the second complex multiplier 11 constitutes a PLL loop. .
[0020]
The amplitude distribution detection circuit 25 is a circuit that detects the amplitude distribution of the eye pattern of the second frequency conversion signal output from the second complex multiplier 11, and this detection signal is input to the synchronization determination circuit 26. The synchronization determination circuit 26 determines from the detection signal output from the amplitude distribution detection circuit 25 whether or not the carrier wave recovery circuit is in a synchronization established state. If not, an asynchronous state determination signal is supplied to the loop control circuit 27, respectively.
[0021]
The loop control circuit 27 is a circuit that controls the offset addition circuit 19 in accordance with the determination signal supplied from the synchronization determination circuit 26. When the synchronization determination signal is supplied, the offset addition circuit 19 is not operated and the asynchronous determination signal is supplied. Then, the offset adding circuit 19 is set in an operating state. As a result, the offset adding circuit 19 superimposes the offset signal on the frequency error signal output from the AFC loop filter 18, and the signal after the offset signal is superimposed is supplied to the frequency control terminal of the numerically controlled oscillator 20. An offset is added to the frequency of the first local oscillation signal.
[0022]
FIG. 2 shows a configuration example of the offset adding circuit 19. An output signal of the AFC loop filter 18 is input to the input terminal 101, and a control signal from the loop control circuit 27 is input to the input terminal 102. The output signal of the AFC loop filter 18 input to the input terminal 101 is supplied to the adder 103 and added with the output signal from the switch 104. The switch 104 outputs “0” when the carrier recovery circuit is in a synchronization established state according to the control signal from the loop control circuit 102 input to the input terminal 102, and “+ a” or “+ a” when the carrier recovery circuit is not in the synchronization established state “−a” is output as an offset signal. That is, the adder 103 adds an offset signal to the output signal of the AFC loop filter 18 input from the input terminal 102 when the carrier recovery circuit is not in a synchronization established state. The output signal of the adder 103 is supplied to the frequency control terminal of the numerically controlled oscillator 20 via the output terminal 105.
[0023]
Next, the operation of this embodiment will be described with reference to FIG.
FIG. 3 is a diagram showing a carrier wave reproduction operation in the present embodiment, where the horizontal axis represents time, and the vertical axis represents the frequency error (second local oscillation) of the second frequency conversion signal output from the second complex multiplier 11. (Frequency error of signal), Ta represents an AFC operation period, and Tp represents a PLL operation period.
[0024]
FIG. 3A shows the carrier wave reproduction operation when the frequency error can be sufficiently removed by the AFC operation. The frequency error is reduced to a level within the phase pull-in range of the PLL by the AFC operation. The phase synchronization is established by the PLL operation.
[0025]
FIG. 3B shows a carrier recovery operation when the frequency error cannot be sufficiently removed by the AFC operation. If there is co-channel interference, the AFC loop may converge to a specific frequency. In this case, since the frequency error is not sufficiently reduced by the AFC operation to fall within the PLL phase pull-in range, even if the AFC operation is shifted to the PLL operation in this state, phase synchronization cannot be achieved.
[0026]
In such a case, in the present embodiment, the loop control circuit 27 controls the AFC loop filter 18 and the offset adding circuit 19, and after the PLL operation over the period of Tp is completed, the offset adding circuit 19 is put into an operating state. The switch 104 in FIG. 2 is connected to the “−a” side for a period of time, a negative offset signal is added to the output of the AFC loop filter 18, and the PLL is reactivated in this state. When a negative offset signal is added to the output of the AFC loop filter 18 in this way, the frequency of the first local oscillation signal is offset to the plus side, the frequency error is also offset to the plus side, and away from the phase pull-in range of the PLL. Therefore, phase synchronization cannot be established.
[0027]
Therefore, next, the loop control circuit 27 connects the switch 104 in FIG. 2 in the offset adding circuit 19 to the “+ a” side over the period of Tp +, and adds a positive offset signal to the output of the AFC loop filter 18. In this state, the PLL is restarted. When a plus offset signal is added to the output of the AFC loop filter 18, the frequency of the first local oscillation signal is offset to the minus side, and the frequency error is also offset to the minus side so that it is within the phase pull-in range of the PLL. Therefore, phase synchronization can be established.
[0028]
Although FIG. 3 shows the case where the frequency error of the second frequency conversion signal is on the plus side, the frequency error can actually be on both the plus side and the minus side. It is uncertain whether the frequency error occurs in the positive or negative direction. For this reason, in the present embodiment, when phase synchronization is not established in the AFC operation, first, the frequency of the first local oscillation signal is first offset in a predetermined direction, for example, the minus side for a certain period as described above, and thereafter the constant frequency is constant. The period is offset to the plus side.
[0029]
As described above, according to the present embodiment, when the carrier recovery circuit is not in the synchronization established state, the AFC and the PLL are sequentially operated, and then an offset is given to the frequency of the first local oscillation signal to obtain the second frequency. By driving the frequency error of the converted signal within the PLL phase pull-in range and then restarting the PLL, carrier wave recovery is possible even under poor reception conditions of modulated waves due to co-channel interference, etc. Since it is not necessary to perform at low speed, the pull-in time can be shortened.
[0030]
(Second Embodiment)
FIG. 4 is a block diagram showing the configuration of a digital demodulator including a carrier recovery circuit according to the second embodiment of the present invention. The same reference numerals are given to the same parts as those in FIG. 1 to describe differences from the first embodiment. In this embodiment, a reception state detection circuit 28 is added.
[0031]
The reception state detection circuit 28 is a circuit that detects the reception state (for example, C / N) of the QPSK modulated wave from the second frequency conversion signal output from the second complex multiplier 11, and the detection result is a loop. It is sent to the control circuit 27. In response to this detection result, the loop control circuit 27 switches the carrier wave reproduction operation.
[0032]
FIG. 5 shows a carrier wave reproduction operation when the frequency error cannot be sufficiently removed by AFC in this embodiment. The horizontal axis is time, and the vertical axis is from the second complex multiplier 11 as in FIG. The frequency error of the output second frequency conversion signal (frequency error of the second local oscillation signal), Ta represents the AFC operation period, and Tp represents the PLL operation period.
[0033]
In the first embodiment, the case where the frequency error is within the pull-in range of the PLL by one AFC operation has been described. However, when the frequency error is low at low C / N, the pull-in operation by the AFC is slow and 1 In the AFC operation over a predetermined period (Ta) times, the frequency error may not be reduced to the extent that the offset adding circuit 19 drives the phase error into the PLL phase pull-in range. In this case, if Ta is set long, the frequency error can be made sufficiently small in one AFC operation. However, since this increases the AFC operation period even at high C / N, the time required to establish phase synchronization. Will become longer.
[0034]
Therefore, in the second embodiment, when the reception state detection circuit 28 is in a poor reception state of the QPSK modulated wave, for example, when C / N falls below a predetermined value, the loop control circuit 27 causes the period Ta as shown in FIG. AFC operation over a period of time and a PLL operation over a period of time Tp are alternately repeated a predetermined number of times N (N = 3 in the example shown in the figure), and then the offset addition circuit 19 is operated in the same manner as in FIG. An offset signal is added to the output of the filter 18, and the frequency of the first local oscillation signal is offset to bring the frequency error into the PLL pull-in range, thereby establishing phase synchronization. However, Ta is set so that the pull-in time becomes optimum when the modulated wave has a high C / N.
[0035]
Here, as described above, if the offset addition circuit 19 is operated when phase synchronization is not established after the PLL operation, the operation period of the PLL becomes (Tp) + (Tp −) + (Tp +). . When the AFC operation and the PLL operation are repeated, the operation period of the PLL becomes longer by (Tp −) + (Tp +) each time the number of repetitions is increased. Therefore, the time required for establishing synchronization becomes longer as the C / N becomes lower. End up.
[0036]
On the other hand, in the present embodiment, as shown in FIG. 5, when the AFC and PLL are repeatedly operated, the offset adding circuit 19 is inactivated until the predetermined number of repetitions (N), and the AFC operation and the PLL operation are performed N times. After the repetition, the offset adding circuit 19 is operated to give an offset to the frequency of the first local oscillation signal, thereby enabling carrier wave reproduction without increasing the pull-in time at low C / N. it can.
[0037]
In this embodiment, detection by the reception state detection circuit 28 may be performed in multiple stages, and the number of repetitions N of the AFC operation and the PLL operation may be changed according to the magnitude of C / N, for example.
[0038]
(Third embodiment)
FIG. 6 shows the configuration of a digital demodulator including a carrier recovery circuit according to the third embodiment of the present invention. The same reference numerals are given to the same parts as in FIG. 1 to explain the differences from the first embodiment. In this embodiment, an offset adding circuit 29 is provided between the PLL loop filter 22 and the numerically controlled oscillator 23 in the PLL loop. And an offset is given to the frequency of the second local oscillation signal output from the numerically controlled oscillator 23. The offset addition circuit 29 is configured in the same manner as the offset addition circuit 19 in the first embodiment.
[0039]
FIG. 7 shows the carrier wave reproduction operation when the frequency error cannot be sufficiently removed by AFC in this embodiment, the horizontal axis is time, and the vertical axis is the second output from the second complex multiplier 11. The frequency error of the frequency conversion signal (frequency error of the second local oscillation signal), TA represents the AFC operation period, and TP represents the PLL operation period. As shown by the solid line in FIG. 7, the AFC operation is first performed over the period TA. Here, since the frequency error has converged to a specific frequency due to co-channel interference or the like, phase synchronization cannot be established by the PLL operation over the next TP period.
[0040]
Therefore, in such a case, the loop control circuit 27 controls the PLL loop filter 22 and the offset adding circuit 29 based on the asynchronous determination signal from the synchronous determination circuit 26, and the AFC operation over the period TA and the PLL over the period TP. After the operation, the offset adding circuit 29 is set in an operating state. First, a negative offset signal is added to the output of the loop filter 28 over a period of TP−, and the PLL is operated again in this state. Thus, when a negative offset signal is added to the output of the loop filter 28, the frequency of the second local oscillation signal is offset to the negative side, and the PLL pull-in range is offset to the negative side as shown in FIG. As a result, the PLL pull-in range is widened for negative frequency errors, but the PLL pull-in range is narrowed for positive frequency errors, so phase synchronization cannot be established.
[0041]
Then, the loop control circuit 27 controls the offset adding circuit 29 so as to add a positive offset signal to the output of the loop filter 28, and re-activates the PLL over the period of TP−. When a positive offset signal is added to the output of the loop filter 28, the frequency of the second local oscillation signal is offset to the positive side, and the PLL pull-in range is also offset to the positive side as shown in FIG. The frequency error falls within the pull-in range of the PLL, and phase synchronization can be established.
[0042]
Although FIG. 7 shows the case where the frequency error of the second frequency conversion signal is on the plus side, as described above, since the frequency error can be on both the plus side and the minus side, in this embodiment, an AFC operation is performed. If phase synchronization is not established, first, the frequency of the second local oscillation signal is first offset in a predetermined direction, for example, as described above, to the minus side for a certain period, and then to the plus side for a certain period of time. Yes.
[0043]
As described above, according to the present embodiment, when the carrier recovery circuit is not in the synchronization established state, the AFC and the PLL are sequentially operated, and then the second local oscillation signal is offset to give the second frequency. By driving the frequency error of the converted signal within the pull-in range of the PLL and then restarting the PLL, the carrier wave can be recovered even in a situation where the modulated wave reception state is poor due to co-channel interference, etc., as in the first embodiment. In addition, since it is not necessary to perform the AFC operation at a low speed, the synchronization pull-in time can be shortened.
[0044]
As a modification of the present embodiment, the reception state is detected as in the second embodiment, the AFC and the PLL are operated repeatedly according to the reception state, and then the offset adding circuit 29 is operated to operate the second local unit. By adding an offset to the frequency of the oscillation signal, carrier wave reproduction can be performed without increasing the pull-in time at low C / N. Also in this case, the number of repetitions N of the AFC operation and the PLL operation may be changed according to the magnitude of C / N, for example, by detecting the reception state detection circuit 28 in multiple stages.
[0045]
(Fourth embodiment)
FIG. 8 shows the configuration of a digital demodulator including a carrier recovery circuit according to the fourth embodiment of the present invention. In this embodiment, the AFC loop filter 31 is provided with an offset addition function. Since the carrier wave reproduction operation of this embodiment is the same as that of the first embodiment, description thereof is omitted.
[0046]
FIG. 9 is a diagram illustrating a configuration example of the AFC loop filter 31 having an offset addition function according to the present embodiment. The output signal of the frequency detector 17 is input to the input terminal 201 and input to the input terminal 202. The switch 203 that is switched in accordance with a control signal from the loop control circuit 27 is selected during the AFC operation and guided to the multiplier 204. Multiplier 204 multiplies the input signal by a coefficient α.
[0047]
The output signal of the multiplier 204 is smoothed by a digital integrator composed of an adder 205 and a latch 206 and supplied to a hold circuit 208. In accordance with the control signal from the loop control circuit 27 input to the input terminal 207, the hold circuit 208 supplies the smoothed signal from the integrator as it is to the numerically controlled oscillator 20 through the output terminal 209 during the AFC operation, and during the PLL operation. The smoothed signal is held and supplied to the numerically controlled oscillator 20 via the output terminal 209.
[0048]
In the operation of applying an offset to the frequency of the first local oscillation signal, the switch 203 selects a positive offset signal + b or a negative offset signal −b after the AFC operation is completed and supplies it to the integrator, and an offset is applied to the smoothing signal. This is done by adding. During the PLL operation period, the smoothed signal to which the offset is added is held by the hold circuit 208 and supplied to the numerically controlled oscillator 20 via the output terminal 209. At this time, when the offset signal + b is selected by the switch 203, a positive offset is applied to the frequency of the second local oscillation signal, and when the offset signal -b is selected, a negative offset is applied to the frequency of the second local oscillation signal.
[0049]
(Fifth embodiment)
FIG. 10 shows the configuration of a digital demodulator including a carrier recovery circuit according to the fifth embodiment of the present invention. In the present embodiment, the PLL loop filter 32 has an offset addition function. Since the carrier wave reproduction operation of this embodiment is the same as that of the third embodiment, the description thereof is omitted.
[0050]
FIG. 11 is a diagram illustrating a configuration example of the PLL loop filter 32 having an offset addition function in the present embodiment. The output signal of the phase detector 16 is input to the input terminal 301 and input to the input terminal 302. The switch 303 that is switched in accordance with a control signal from the loop control circuit 27 is selected during the PLL operation and guided to the multipliers 304 and 307. Multiplier 304 multiplies the input signal by a coefficient β, and multiplier 307 multiplies the input signal by a coefficient γ. The output signal of the multiplier 304 is smoothed by a digital integrator composed of an adder 305 and a latch 306, and this smoothed signal is supplied to the adder 308.
[0051]
The output signal of the multiplier 307 is directly supplied to the adder 308 and added with the smoothed signal. An output signal of the adder 308 is input to the latch circuit 309. The latch circuit 309 supplies the smoothed signal from the integrator as it is to the numerically controlled oscillator 23 via the output terminal 311 during the PLL operation in accordance with the control signal input from the loop control circuit 27 via the input terminal 310 to perform the AFC operation. Sometimes cleared.
[0052]
In the operation of giving an offset to the frequency of the second local oscillation signal, the positive offset signal + c or the negative offset signal −c is selected by the switch 303 and supplied to the integrator before the PLL operation starts, and the smoothing signal is supplied. Is performed by adding an offset to. The smoothed signal to which the offset is added in this way is supplied to the numerically controlled oscillator 23 via the output terminal 311. During the operation period of the PLL, the switch 303 selects the output signal of the phase detector 16 input via the input terminal 301, and operates as a normal loop filter.
[0053]
【The invention's effect】
As described above, according to the present invention, the first local oscillation in the AFC loop is performed when the phase pull-in operation is performed by the PLL after the frequency error is removed by the AFC operation. After applying an appropriate offset to the frequency of the signal or the frequency of the second local oscillation signal in the PLL loop, the PLL is operated again to perform the phase pull-in operation, so that a modulated wave due to transmission interference such as co-channel interference Even in a situation where the reception state is poor and phase pull-in cannot be performed by PLL operation, phase pull-in can be performed reliably and at high speed, and synchronization can be established in a short time.
[0054]
In addition, by applying the offset after performing the repeated operation of AFC and PLL a plurality of times, phase synchronization can be established without increasing the phase pull-in time particularly in a low C / N state. Further, in this case, it is more effective if the reception state is detected by the C / N of the modulated wave and the number of repetitions of AFC and PLL is set accordingly.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a digital demodulator including a carrier recovery circuit according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration example of an offset addition circuit in the embodiment.
FIG. 3 is a diagram for explaining a carrier wave reproduction operation in the embodiment;
FIG. 4 is a block diagram showing a configuration of a digital demodulator including a carrier recovery circuit according to a second embodiment of the present invention.
FIG. 5 is a diagram for explaining a carrier wave reproduction operation in the embodiment;
FIG. 6 is a block diagram showing a configuration of a digital demodulator including a carrier recovery circuit according to a third embodiment of the present invention.
FIG. 7 is a diagram for explaining a carrier wave reproduction operation in the embodiment;
FIG. 8 is a block diagram showing a configuration of a digital demodulator including a carrier recovery circuit according to a fourth embodiment of the present invention.
FIG. 9 is a block diagram showing a configuration example of an AFC loop filter having an offset addition capability according to the embodiment;
FIG. 10 is a block diagram showing a configuration of a digital demodulator including a carrier recovery circuit according to a fifth embodiment of the present invention.
FIG. 11 is a block diagram showing the configuration of a PLL loop filter having an offset addition capability in the embodiment;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Modulation wave input terminal, 2 ... In-phase detector, 3 ... Quadrature detector, 4 ... Distributor, 5 ... Local oscillator, 6, 7 ... A / D converter, 8 ... 1st complex multiplier, 9, DESCRIPTION OF SYMBOLS 10 ... Digital low-pass filter, 11 ... 2nd complex multiplier, 12 ... Clock reproduction circuit, 13 ... Data reproduction circuit, 14, 15 ... Demodulated data output terminal, 16 ... Phase detector, 17 ... Frequency detector, 18 ... AFC loop filter, 19 ... offset addition circuit, 20 ... numerical control oscillator, 21 ... data converter, 22 ... PLL loop filter, 23 ... numerical control oscillator, 24 ... data converter, 25 ... amplitude distribution detection circuit, 26 ... Synchronous judgment circuit, 27 ... Loop control circuit, 28 ... Reception state detection circuit, 29 ... Offset addition circuit, 31 ... AFC loop filter having offset addition capability, 32 ... Offset addition possible Loop filter for PLL having.

Claims (8)

First frequency conversion means for generating a first frequency conversion signal by multiplying the input modulated wave by a first local oscillation signal;
Frequency control means for detecting a frequency error of the first frequency conversion signal and controlling the frequency of the first local oscillation signal so as to reduce the frequency error;
Second frequency conversion means for generating a second frequency conversion signal by multiplying the first frequency conversion signal by a second local oscillation signal;
Phase synchronization means for detecting a phase error of the second frequency conversion signal and controlling the phase of the second local oscillation signal so as to reduce the phase error to synchronize the phase with the modulated wave;
An offset applying means for applying an offset to the frequency of the first local oscillation signal;
After the frequency control unit is operated, the phase synchronization unit is operated, and when the phase synchronization is not established, the offset applying unit is set in the plus direction or the minus direction with respect to the frequency of the first local oscillation signal. out have line control for operating the phase synchronization means again operated to impart an offset to the predetermined one direction, the said offset supply means when the phase synchronization was not established by the control Control means for performing control to operate the phase synchronization means again after operating to give an offset in the other of the plus direction and the minus direction with respect to the frequency of the first local oscillation signal A carrier recovery circuit. First frequency conversion means for generating a first frequency conversion signal by multiplying the input modulated wave by a first local oscillation signal;
Frequency control means for detecting a frequency error of the first frequency conversion signal and controlling the frequency of the first local oscillation signal so as to reduce the frequency error;
Second frequency conversion means for generating a second frequency conversion signal by multiplying the first frequency conversion signal by a second local oscillation signal;
Phase synchronization means for detecting a phase error of the second frequency conversion signal and controlling the phase of the second local oscillation signal so as to reduce the phase error to synchronize the phase with the modulated wave;
An offset applying means for applying an offset to the frequency of the first local oscillation signal;
After the frequency control unit and the phase synchronization unit are alternately operated by the number of times corresponding to the reception state of the modulated wave, the phase offset unit is operated when the phase synchronization is not established, and then the phase again A carrier recovery circuit comprising control means for performing control for operating the synchronization means. First frequency conversion means for generating a first frequency conversion signal by multiplying the input modulated wave by a first local oscillation signal;
Frequency control means for detecting a frequency error of the first frequency conversion signal and controlling the frequency of the first local oscillation signal so as to reduce the frequency error;
Second frequency conversion means for generating a second frequency conversion signal by multiplying the first frequency conversion signal by a second local oscillation signal;
Phase synchronization means for detecting a phase error of the second frequency conversion signal and controlling the phase of the second local oscillation signal so as to reduce the phase error to synchronize the phase with the modulated wave;
An offset applying means for applying an offset to the frequency of the second local oscillation signal;
After the frequency control unit is operated, the phase synchronization unit is operated, and when the phase synchronization is not established, the offset applying unit is set in the plus direction or the minus direction with respect to the frequency of the first local oscillation signal. out have line control for operating the phase synchronization means again operated to impart an offset to the predetermined one direction, the said offset supply means when the phase synchronization was not established by the control Control means for performing control to operate the phase synchronization means again after operating to give an offset in the other of the plus direction and the minus direction with respect to the frequency of the first local oscillation signal A carrier recovery circuit. First frequency conversion means for generating a first frequency conversion signal by multiplying the input modulated wave by a first local oscillation signal;
Frequency control means for detecting a frequency error of the first frequency conversion signal and controlling the frequency of the first local oscillation signal so as to reduce the frequency error;
Second frequency conversion means for generating a second frequency conversion signal by multiplying the first frequency conversion signal by a second local oscillation signal;
Phase synchronization means for detecting a phase error of the second frequency conversion signal and controlling the phase of the second local oscillation signal so as to reduce the phase error to synchronize the phase with the modulated wave;
An offset applying means for applying an offset to the frequency of the second local oscillation signal;
After the frequency control unit and the phase synchronization unit are alternately operated by the number of times corresponding to the reception state of the modulated wave, the phase offset unit is operated when the phase synchronization is not established, and then the phase again A carrier recovery circuit comprising control means for performing control for operating the synchronization means. An input modulated wave is multiplied by a first local oscillation signal to generate a first frequency conversion signal, and the first local oscillation signal is reduced so that the frequency error of the first frequency conversion signal is reduced. Controlling the frequency, multiplying the first frequency converted signal by a second local oscillation signal to generate a second frequency converted signal, and reducing the phase error of the second frequency converted signal In a method for reproducing a carrier wave by controlling the phase of a second local oscillation signal and synchronizing the phase with the modulated wave,
After the frequency control of the first local oscillation signal, performs the phase synchronization, previously among the plus direction or minus direction for the frequency of the first local oscillation signal when the phase synchronization is not completed There line again phase synchronization after applying an offset in the direction of one which defines, plus direction with respect to the frequency of the first local oscillation signal when the phase synchronization has not established even if the該再degree phase synchronization Alternatively , a carrier wave regeneration method characterized by performing phase synchronization again after providing an offset in the other of the minus directions . An input modulated wave is multiplied by a first local oscillation signal to generate a first frequency conversion signal, and the first local oscillation signal is reduced so that the frequency error of the first frequency conversion signal is reduced. Controlling the frequency, multiplying the first frequency converted signal by a second local oscillation signal to generate a second frequency converted signal, and reducing the phase error of the second frequency converted signal In a method for reproducing a carrier wave by controlling the phase of a second local oscillation signal and synchronizing the phase with the modulated wave,
After the frequency control of the first local oscillation signal, performs the phase synchronization, previously among the plus direction or minus direction for the frequency of the second local oscillation signal when the phase synchronization is not established There line again phase synchronization after applying an offset in the direction of one which defines, plus direction with respect to the frequency of the second local oscillation signal when the phase synchronization has not established even if the該再degree phase synchronization Alternatively , a carrier wave regeneration method characterized by performing phase synchronization again after providing an offset in the other of the minus directions .   An input modulated wave is multiplied by a first local oscillation signal to generate a first frequency conversion signal, and the first local oscillation signal is reduced so that the frequency error of the first frequency conversion signal is reduced. Controlling the frequency, multiplying the first frequency converted signal by a second local oscillation signal to generate a second frequency converted signal, and reducing the phase error of the second frequency converted signal Second In the carrier wave reproduction method for carrying out carrier wave reproduction by controlling the phase of the local oscillation signal and synchronizing the phase with the modulated wave,
  After the frequency control of the first local oscillation signal and the phase synchronization are alternately operated by the number of times corresponding to the reception state of the modulated wave, the first local oscillation is performed when the phase synchronization is not established. A carrier wave reproducing method, wherein an offset is given to a frequency of a signal and then the phase synchronization is performed again.   An input modulated wave is multiplied by a first local oscillation signal to generate a first frequency conversion signal, and the first local oscillation signal is reduced so that the frequency error of the first frequency conversion signal is reduced. Controlling the frequency, multiplying the first frequency converted signal by a second local oscillation signal to generate a second frequency converted signal, and reducing the phase error of the second frequency converted signal In the carrier wave reproduction method for carrying out carrier wave reproduction by controlling the phase of the second local oscillation signal and synchronizing the phase with the modulated wave,
  After the frequency control of the first local oscillation signal and the phase synchronization are alternately repeated by the number of times corresponding to the reception state of the modulated wave, the second local oscillation is performed when the phase synchronization is not established. A carrier wave reproducing method, wherein an offset is given to a frequency of a signal and then the phase synchronization is performed again.

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