JP3674631B2 - Liquid crystal device and projection display device - Google Patents

Description

  The present invention relates to a liquid crystal device and a projection display device. More specifically, the present invention relates to a light shielding structure in a liquid crystal device using a thin film transistor (hereinafter referred to as TFT) as a pixel switching element.

  Conventionally, as an active matrix liquid crystal device, pixel electrodes are formed in a matrix on a glass substrate, and a pixel switching TFT using an amorphous silicon film or a polysilicon film as a semiconductor layer corresponding to each pixel electrode is provided. A configuration in which a liquid crystal is driven by applying a voltage to each pixel electrode via a TFT has been put into practical use. In a liquid crystal device using a polysilicon TFT for pixel switching, a TFT for a driving circuit that constitutes a peripheral driving circuit such as a shift register circuit for driving and controlling a screen display unit is substantially the same process as a pixel switching TFT. Since it can be formed, it is attracting attention as being suitable for high integration.

  In an active matrix liquid crystal device, a light-shielding film formed of a chromium film or an aluminum film called a black matrix (or black stripe) is formed on a counter substrate for the purpose of achieving high definition display. Yes. Further, this light shielding film is formed so as to overlap with the pixel switching TFT, so that light incident from the counter substrate side reaches the channel region of the pixel switching TFT and the junction region thereof, and leakage current is generated in the pixel switching TFT. The structure does not flow.

  However, the leakage current due to light is not only incident light from the counter substrate side but also light reflected by a polarizing plate or the like disposed on the back side of the substrate for the liquid crystal device is applied to the channel region of the pixel switching TFT. May flow.

  As a method for preventing such a leakage current due to reflected light (return light), Patent Document 1 proposes an invention in which a light shielding film is provided on the lower layer side of the channel region of the pixel switching TFT.

Japanese Patent Publication No. 3-52611

  However, in the disclosed invention, since the potential of the light shielding film is not fixed, there is a problem that TFT characteristics fluctuate or deteriorate due to the parasitic capacitance between the semiconductor layer of the TFT and the light shielding film.

  On the other hand, with the increase in the number of pixels and the downsizing of electronic devices incorporating a liquid crystal device, peripheral driver circuits are desired to be increasingly highly integrated. In particular, in a liquid crystal device in which a peripheral drive circuit is built in the same substrate, a multilayer wiring technique in which a metal film such as aluminum is formed in a multilayer through an insulating film is used as a technique for achieving high integration of the circuit. However, there is a problem that the number of steps in the manufacturing process increases and the manufacturing cost increases as the multilayer wiring structure is formed.

  In addition, as the operating frequency of liquid crystal devices of the active matrix drive system increases, attempts to improve the quality of semiconductor films by adopting SOI technology or recrystallization technology by laser annealing to improve TFT characteristics. However, the improvement of the TFT characteristics by such a method has the problems that the characteristic variation is large and the manufacturing process becomes complicated.

  Accordingly, an object of the present invention is to suppress the leakage current of the pixel switching TFT due to the influence of the light reflected by the polarizing plate or the like in the liquid crystal device and the projection display device using the same, and to improve the characteristics of the pixel switching TFT. The object is to provide a technique capable of achieving stabilization.

In order to solve the above problems, the present invention provides a display area in which pixels are configured in a matrix by a plurality of data lines and a plurality of scanning lines, and at least one of the data lines and the scanning lines on the outer peripheral side of the display area. A liquid crystal device substrate comprising a peripheral driving circuit connected to the plurality of thin film transistors provided corresponding to the data lines and the scanning lines, and sandwiched between the liquid crystal device substrate and the counter substrate In a liquid crystal device having a liquid crystal and a sealing material for bonding the liquid crystal device substrate and the counter substrate, a peripheral parting formed on the counter substrate along an outer edge of the display region and defining the display region and a light shielding film for use in the liquid crystal device substrate, and shielding the channel portion of the thin film transistor, and the branch which extends to the area of a light-shielding film for the peripheral partition, the peripheral partition Characterized in that it comprises a capacitance of the light-shielding film is formed along the sides of the display area in the region under the light-shielding and a trunk connected the the branch line electrically interconnect.

  In the liquid crystal device according to the present invention, since the light-shielding capacitor wiring is formed so as to overlap with the thin film transistor connected to the data line and the scanning line, that is, the channel region of the pixel switching TFT, light is transmitted to the pixel switching TFT. It does not reach the channel area. Therefore, the pixel switching TFT does not generate a leak current due to the reflected light from the back side of the liquid crystal device substrate.

  In the liquid crystal device according to the aspect of the invention, it is preferable that the branch line extends along the scanning line and the data line.

  In the liquid crystal device according to the present invention, a storage capacitor may be formed by the capacitor wiring and the drain region of the thin film transistor.

  In the liquid crystal device according to the present invention, the peripheral parting light-shielding film may be formed in an inner region of the sealing material and along an outer edge of the display region.

  The liquid crystal device according to the present invention is preferably used as a light valve of a projection display device that is irradiated with intense light because leakage current due to light from the TFT is suppressed. In such a projection display device, light from a light source is modulated by the liquid crystal device according to the present invention, and the modulated light is enlarged and projected by projection optical means.

  Embodiments of the present invention will be described with reference to the accompanying drawings.

(Basic configuration of liquid crystal device)
1 and 2 are a plan view of a liquid crystal device to which the present invention is applied and a cross-sectional view taken along the line H-H ', respectively.

  As shown in these drawings, the liquid crystal device 100 includes a rectangular display region 61 (screen display region) in which pixels to be described later are formed in a matrix, and a data line driving circuit 103 formed in an outer region of the display region 61. (Peripheral drive circuit) and a liquid crystal device substrate 300 including a pair of scanning line drive circuits 104 (peripheral drive circuit) formed on both sides of the display area 61, and a counter substrate disposed opposite to the liquid crystal device substrate 300 31. A pixel electrode 14 made of an ITO film (Indium Tin Oxide) is formed on the liquid crystal device substrate 300 for each pixel 105 described later. On the counter substrate 31, a counter electrode 32 is formed on substantially the entire surface, and a black matrix 6 is formed corresponding to each pixel 105. In the counter substrate 31, a counter electrode 32 made of a transparent conductive film such as an ITO film is formed on a transparent substrate such as glass, neoceram, or quartz. Further, the counter substrate 31 includes a light shielding film 60 for closing the periphery along the outer edge of the display area 61 so that light does not leak when the liquid crystal device 100 is assembled as a module. Is formed.

  The counter substrate 31 and the liquid crystal device substrate 300 are bonded to each other with a predetermined cell gap by a gap material-containing sealing material 200 formed along the outer periphery of the light shielding film 60 for parting the periphery outside the display region 61. The liquid crystal 108 is sealed in the inner region of the sealing material 200. The sealing material 200 performs sealing on the data line described later between the display area 61 and the data line driving circuit 103, and on the scanning line described later between the display area 61 and the scanning line driving circuit 104. Sealing is performed. The sealing material 200 is partially interrupted, and the liquid crystal injection port 241 is configured by the interrupted portion. Therefore, in the liquid crystal device 100, after the counter substrate 31 and the liquid crystal device substrate 300 are bonded together, the inner region of the sealant 200 is brought into a reduced pressure state, and the liquid crystal 108 is injected under reduced pressure from the liquid crystal injection port 241. After the sealing, the liquid crystal injection port 241 is closed with the sealant 242.

  As the sealing material 200, an epoxy resin, various ultraviolet curable resins, or the like is used, and a gap material made of glass fiber or glass beads is blended therein. As the liquid crystal 108, a well-known TN (Twisted Nematic) type liquid crystal or the like is used. If a polymer dispersion type liquid crystal dispersed as fine particles in a polymer is used as the liquid crystal 108, neither an alignment film nor a polarizing plate is required, so that the light use efficiency is increased and the bright active matrix type liquid crystal device 100 is manufactured. Can be provided. Further, for the pixel electrode 14, the liquid crystal device 100 can be configured as a reflective liquid crystal device by using a non-transmissive and highly reflective metal film such as an aluminum film instead of the ITO film. In the case of the reflective liquid crystal device 100, an SH (Super Homeotropic) liquid crystal in which liquid crystal molecules are substantially vertically aligned in a state where no voltage is applied can be used. Furthermore, it goes without saying that other liquid crystals may be used.

  In this embodiment, since the counter substrate 31 is smaller than the liquid crystal device substrate 300, the liquid crystal device substrate 300 is bonded in a state where the peripheral driving circuit protrudes from the outer peripheral edge of the counter substrate 31. Accordingly, since the scanning line driving circuit 104 and the data line driving circuit 103 are located outside the counter substrate 31 and are not opposed to the counter substrate 31, an alignment film such as polyimide or liquid crystal deteriorates due to a DC component. Can be prevented. The sealing material 200 is formed along the outer periphery of the substrate when viewed from the counter substrate 31, but is formed inside when viewed from the substrate 300 for the liquid crystal device. A large number of mounting terminals 107 are formed on the liquid crystal device substrate 300 outside the counter substrate 31, and a flexible printed wiring board is connected by a method such as wire bonding or ACF (Anisotropic Conductive Film) pressure bonding.

(Basic configuration of liquid crystal device substrate and display area)
FIG. 3 is a block diagram of a liquid crystal device substrate 300 with a built-in drive circuit used in the liquid crystal device 100 of the present embodiment. In FIG. 3, the first light-shielding film on the liquid crystal device substrate 300 side, which will be described later, is omitted for easy understanding of the basic components of the liquid crystal device substrate 300.

  As can be seen from FIG. 3, in the display region 61 of the liquid crystal device substrate 300, a plurality of pixels 105 are formed in a matrix on the substrate 10 by a plurality of scanning lines 2 and a plurality of data lines 3. A detailed block diagram and configuration diagram of each pixel 105 are shown in FIGS. 4 (A) and 4 (B). As shown in FIGS. 4A and 4B, a pixel switching TFT 102 connected to the scanning line 2 and the data line 3 is formed in the pixel 105. A liquid crystal cell CE is formed with a liquid crystal 108 interposed between the pixel electrode connected to the TFT 102 and the counter electrode 32 of the counter substrate 31. For the liquid crystal cell CE, a storage capacitor CAP is configured by using the capacitor wiring 18 formed simultaneously with the scanning line 2. In other words, in the present embodiment, the drain region of the semiconductor layer 1 constituting the pixel switching TFT 102 is expanded, the expanded region is used as the first electrode of the storage capacitor CAP, and the capacitor wiring 18 formed simultaneously with the scanning line 2 is formed. The storage capacitor CAP is configured by using the second electrode and a gate insulating film formed between the first and second electrodes as a dielectric film.

Here, the region in which the capacitor wiring 18 is formed is a region that causes the liquid crystal disclination due to the influence of the electric field in the lateral direction and the like and causes deterioration of the screen display quality. The black matrix 6 (see FIG. 2) was overlaid and shielded from light. However, in this embodiment, the capacitor wiring 18 is arranged in such a region that should become a dead space, thereby preventing occurrence of flicker, crosstalk, etc. without wasting an area through which light can be transmitted in the pixel 105. doing.
Therefore, the liquid crystal device 100 of this embodiment can perform high-quality display.

  In this embodiment, the first light-shielding film 7 is formed of, for example, the same aluminum film as the data line 3 for supplying the constant voltage power supply VSSY on the low potential side of the scanning line driving circuit 104 for supplying a constant potential. The capacitance wiring 18 formed of the same polysilicon film or the like as the scanning line 2 may be electrically connected in the contact hole 5 using the constant potential wiring 8 formed. The contact hole 5 can be formed in the same process as the contact hole for connecting the data line 3 and the high concentration source region 1a. With such a configuration, since the constant potential wiring 8 for supplying a constant potential to the first light shielding film 7 and the capacitor wiring 18 can be shared, it is not necessary to provide a dedicated wiring for each, and the layout can be effectively performed with a small area. . Further, since the constant potential wiring for supplying the counter electrode potential to the power source of the peripheral drive circuit and the counter substrate is substituted, the dedicated mounting terminal 107 and the lead wiring 28 are not necessary. Therefore, since the number of mounting terminals can be reduced and the space can be effectively used, the smaller the liquid crystal device is, the more advantageous.

Although not shown, the storage capacitor CAP is configured by extending the drain region of the semiconductor film constituting the pixel switching TFT 102 and overlapping it with the scanning line 2 in the previous stage via the gate insulating film. It is also possible to do.
In the liquid crystal device substrate 300, constant power supplies VDDX, VSSX, VDDY, VSSY, modulated image signals VID 1 to VID 6, various signals (start signal DY of the scanning line shift register circuit 231) are provided on the side portion on the data line driving circuit 103 side. A number of mounting terminals 107 to which a clock signal CLY, an inverted clock signal CLYB thereof, a start signal DX of the data line shift register circuit 221, a clock signal CLX, and an inverted clock signal CLXB thereof, and the like are input. The mounting terminal 107 is composed of a metal film such as an aluminum film, a metal silicide film, or a conductive film such as an ITO film. From these mounting terminals 107, a plurality of signal wirings 28 for driving the scanning line driving circuit 104 and the data line driving circuit 103 are respectively routed from the sealing material 200 through the outer peripheral side of the substrate. These signal wirings 28 are made of a low-resistance metal film such as an aluminum film formed simultaneously with the data lines 3 or a metal silicide film. When resistance is added as a countermeasure against static electricity, the signal wiring 28 contacts the second interlayer insulating film 13. A hole may be opened and electrically connected by a contact hole to a polysilicon film formed of the same material in the same process as the scanning line. In order to supply the counter electrode potential LCCOM externally input from the mounting terminal 107 from the liquid crystal device substrate 300 to the counter substrate 31, a vertical conduction terminal 106 is formed on the liquid crystal device substrate 300. If the liquid crystal device substrate 300 and the counter substrate 31 are bonded to each other with the vertical conductive material having a predetermined diameter interposed between the vertical conductive terminals 106, the liquid crystal device substrate 300 side is connected to the counter electrode 32 of the counter substrate 31. The counter electrode potential LCCOM can be applied.

  In the liquid crystal device substrate 300, a signal output from the data line shift register circuit 221, the data line buffer circuit 222, and the data line shift register circuit 221 via the data line buffer circuit 222 is provided on the data line driving circuit 103 side. A data sampling circuit 101 having an analog switch composed of TFTs that operate based on it, and six image signal lines 225 corresponding to the modulated image signals VID1 to VID6 developed in six phases are configured.

  The data line shift register circuit 221 of the data line driving circuit 103 may be constituted by a plurality of series in which a common start signal DX is input for each series, for example. In this manner, if the data line shift register circuit 221 is configured in multiple series, the transfer frequency of the clock signal CLX and its inverted clock signal CLXB can be lowered, so that the circuit load can be reduced. A start signal DX is supplied to the data line shift register circuit 221 from the outside via the mounting terminal 107, and a clock signal CLX and its inverted clock signal CLXB are supplied to flip-flops (not shown) in each stage. Is supplied. Therefore, in the data line shift register circuit 221, after the start signal DX is input, the shift signal (the analog switch of the data sampling circuit 101 is driven in synchronization with the rising edge of the clock signal CLX and its inverted clock signal CLXB). Sampling signals X1, X2, X3...) Are generated and output. When a sampling signal having a phase shift is output from the data line shift register circuit 221 to the data sampling circuit 101 via the data line buffer circuit 222, the analog switches are sequentially operated based on the sampling signal. As a result, the modulated image signals VID1 to VID6 supplied via the image signal line 225 are taken into the predetermined data line 3 at a predetermined timing and selected by the scanning signal supplied via the scanning line 2. It is held in the pixel 105. In this example, the method of sequentially driving the data lines 3 one by one at a certain timing has been described. However, a large number of data lines 3, such as three, six or twelve, are simultaneously selected by one sampling signal. On the other hand, the same image display can be obtained by changing the timing of the modulated image signal input from the outside. Further, the number of phase expansions of the modulated image signal supplied to the data line 3 is not limited to six phases, but may be five or less if the analog switch constituting the data sampling circuit 101 has good writing characteristics. If the frequency is high, it may be increased to 7 or more phases. At this time, it is needless to say that at least the number of image signal lines 225 is required for the number of phase expansions of the modulated image signal. Further, by configuring the data line driving circuit 103 on the opposite side of the display region 61, the two data line driving circuits 103 may drive every other data line 3 in a comb-like shape. With such a configuration, the drive frequency of the shift register can be halved, and the circuit load can be reduced.

  Similarly, the scan line driver circuit 104 generates a shift signal (scan signal) based on the start signal DY, the clock signal CLY, and the inverted clock signal CLYB, and outputs the shift signal, and the scan line. A buffer circuit 232 is configured. In this embodiment, since the scanning line driving circuit 104 is configured on both sides of the display area 61 and the scanning line 2 is driven from both sides, the driving load on the scanning line 2 can be reduced. If the time constant of the scanning line 2 can be ignored, the scanning line driving circuit 104 may be configured only on one side of the display area 61.

  In the substrate 300 for the liquid crystal device, a peripheral parting light shielding film 60 (a region with a diagonal line rising to the right in FIG. 3) on the opposite side of the display region 61 from the side where the data line driving circuit 103 is formed. An auxiliary circuit 109 for the data line 3 is also formed in the overlapping region. The auxiliary circuit 109 includes a switching circuit 171 that uses TFTs, two signal wirings 172 that are electrically connected to the data line 3 via the switching circuit 171, and a signal wiring that controls the switching circuit 171. 173. In the auxiliary circuit 109, the connection state between the data line 3 and the signal wiring 172 can be controlled by operating the switching circuit 171 based on the control signal NRG supplied to the signal wiring 173. Accordingly, the auxiliary circuit 109 is driven by the control signal NRG during one horizontal blanking period of the image signal, and an actual modulated image is obtained by a precharge function that preliminarily applies a certain level of potential to the data line 3 as the signals NRS1 and NRS2. The load for writing the signals VID1 to VID6 to the data line 3 via the data sampling circuit 101 can be reduced. As the auxiliary circuit 109, an inspection circuit for detecting a point defect or a line defect can be configured, or the above-described precharge function and the inspection circuit can be combined.

  FIG. 5 is a cross-sectional view taken along line A-A ′ of FIG.

  As can be seen from FIGS. 4B and 5, the pixel switching TFT 102 includes a scanning line 2 (gate electrode), a channel region 1 c where a channel is formed by an electric field from the scanning line 2, and the scanning line 2 and the channel. A gate insulating film 12 formed between the region 1c, a high concentration source region 1a electrically connected to the data line 3 (source electrode) through a contact hole 5 of the second interlayer insulating film 13, and a pixel electrode 14 is provided with a high-concentration drain region 1b electrically connected via a contact hole 4 formed in the second interlayer insulating film 13 and the third interlayer insulating film 15. Further, the pixel switching TFT 102 includes a junction between the channel region 1c and the source region 1a implanted with high-concentration impurity ions, and a junction between the channel region 1c and the drain region 1b implanted with high-concentration impurity ions. It has an LDD (Lightly Doped Drain) structure in which low-concentration source / drain regions 1d and 1e into which low-concentration impurity ions are implanted are formed.

  In this embodiment, the TFT 102 is configured using the lower side of the data line 3, and at least the gate electrode of the scanning line 2, that is, the channel region 1 c and the low concentration source / drain regions 1 d and 1 e of the pixel switching TFT 102 are the data line 3. It is in a state covered with. Thereby, incident light from the counter substrate 31 side is not irradiated to the channel region 1c and the low-concentration source / drain regions 1d and 1e of the pixel switching TFT 102, so that the leakage current of the TFT due to light can be reduced. The basic configuration of the embodiment and improvement examples described below is the same as the above-described configuration.

[Embodiment 1]
FIG. 6 is an enlarged plan view showing the periphery of two pixels formed at the end of the display area in the liquid crystal device substrate used in the liquid crystal device of this embodiment. FIG. 7 is an explanatory diagram showing a wiring portion (wiring) of the first light-shielding film formed on the liquid crystal device substrate of this embodiment and a connection structure between the wiring and the constant potential wiring. FIGS. 8A and 8B are cross-sectional views taken along the line BB ′ in FIG. 6 and a connection portion between the first light shielding film wiring and the constant potential wiring, and the light shielding film wiring, respectively. It is an enlarged plan view of a connection portion with a constant potential wiring.

  As shown in FIG. 5, in the liquid crystal device substrate 300 of the liquid crystal device 100 of this embodiment, a first interlayer insulating film 11 is formed on the lower layer side of the pixel switching TFT 102, and the interlayer insulating film 11 and the substrate 10 are separated from each other. The light shielding structure described below is configured using the layers.

  In this embodiment, the channel region 1c, the low concentration source / drain regions 1d, 1e, and the low concentration source / drain regions 1d, 1e of the pixel switching TFT 102 are high between the first interlayer insulating film 11 and the substrate 10. Opaque and conductive made of a metal film such as tungsten, titanium, chromium, tantalum or molybdenum or a metal alloy film such as metal silicide containing these metals so as to at least overlap with the junction with the concentration source / drain regions 1a and 1b. A light-shielding film 7 having a property is formed. In this embodiment, since there is a portion where the first light shielding film 7 is not formed on the lower layer side of the high concentration drain region 1b of the pixel switching TFT 102, the region where the TFT 102 is formed depends on the presence or absence of the first light shielding film 7. There is a step in Such a step may make the characteristics of the TFT 102 unstable. Therefore, in this embodiment, the step has an effect on the characteristics of the TFT 102 by shifting the position of the step from the junction between the high-concentration drain region 1b and the low-concentration drain region 1e by 1 micron or more toward the high-concentration drain region 1b. Is kept to a minimum.

As can be seen from FIG. 6, the first light-shielding film 7 includes a channel light-shielding portion that overlaps the channel region 1c and the like on its lower layer side, and a lower side of the scanning line 2 in order to apply a constant voltage to this channel light-shielding portion. A wiring portion ((wiring)) extending from the channel light-shielding portion along the scanning line 2 is provided.In this embodiment, the mask line and the scanning line 2 are shifted by the mask alignment deviation during the mask alignment in the photolithography process of the manufacturing process. Even if the formation position is deviated from the wiring of the first light shielding film 7, incident light (light transmitted through the liquid crystal 108) is blocked by the wiring of the first light shielding film 7 or directly on the surface of the light shielding film 7. The width of the wiring of the first light shielding film 7 is set to be slightly narrower than the width of the scanning line 2 so as not to be irradiated with light, which is shown in FIG. And each picture The positional relationship with the element 105 is shown, and display is performed in the inner region of the black matrix 6 indicated by a dotted line.
As shown in FIGS. 6 and 7, the wiring of the first light shielding film 7 is led out to the outside of the display region 61 along each scanning line 2 and extends to the lower layer side of the light shielding film 60 for parting the periphery. It is installed. A constant potential wiring 8 for supplying a constant voltage power supply VSSY on the low potential side to the scanning line drive circuit 104 is disposed along the side of the display region 61 on the lower layer side of the light shielding film 60 for parting the periphery. One end of the first light shielding film 7 is connected to the constant potential wiring 8. Therefore, since the first light shielding film 7 is connected to the constant potential wiring 8 that supplies the constant voltage power supply VSSY on the low potential side of the scanning line driving circuit 104, the first light shielding film is the constant potential wiring 8. It is in a fixed state and not in a floating state.

  In connecting the wiring portion of the first light shielding film 7 and the constant potential wiring 8, in this embodiment, as shown in FIG. 8A, the wiring of the first light shielding film 7 is the first interlayer insulating film 11. And between the substrate 10 and the substrate 10. Since the constant potential wiring 8 is a conductive film formed simultaneously with the data line 3, it is disposed between the second interlayer insulating film 13 and the third interlayer insulating film 15. Therefore, in this embodiment, as shown in FIGS. 6, 7, 8 </ b> A, and 8 </ b> B, the end portion of the wiring of the first light shielding film 7 includes the first interlayer insulating film 11 and the second interlayer insulating film. It is connected to the constant potential wiring 8 through a contact hole 9 formed in the film 13.

  In such a connection structure, the contact hole 9 for connecting the wiring of the first light shielding film 7 and the constant potential wiring 8 is formed, and the source electrode (data line 3) is connected to the source region of the pixel switching TFT 102. This corresponds to the case where the contact hole 5 (see FIG. 5) is simultaneously formed, and the contact hole 9 is opened by a single etching process. However, in order to simultaneously perform the opening of the contact hole 5 and the opening of the contact hole 9, the second interlayer is formed so that the polysilicon film in the contact hole 5 portion of the high concentration source region 1a of the pixel switching TFT 102 is not etched. It is preferable that the first interlayer insulating film 11 is sufficiently thin with respect to the insulating film 13.

  Thus, in the liquid crystal device 100 of this embodiment, at least the channel region 1c, the low concentration source / drain regions 1d, 1e, the low concentration source / drain regions 1d, 1e and the high concentration source / drain region 1a of the pixel switching TFT 102. Since the first light-shielding film 7 (channel light-shielding portion) is formed on the lower layer side of the junction with 1b via the first interlayer insulating film 11, the back side of the liquid crystal device substrate 300 is formed. Even if there is reflected light from the pixel, this light does not reach the channel region 1c of the pixel switching TFT 102 or the like. Therefore, in the liquid crystal device 100 of this embodiment, the TFT 102 does not generate a leakage current due to the reflected light from the back side of the liquid crystal device substrate 300. In addition, since the first light shielding film 7 is fixed to the potential of the constant voltage power supply VSSY on the low potential side of the scanning line driving circuit 104, there is a parasitic between the semiconductor layer 1 of the TFT 102 and the first light shielding film 7. TFT characteristics do not fluctuate or deteriorate under the influence of the capacitance to be applied.

  The surface of the first light-shielding film 7 is subjected to antireflection treatment, and incident light (light transmitted through the liquid crystal 108) is reflected by the surface of the first light-shielding film 7 toward the pixel switching TFT 102. It is preferable to prevent the irradiation.

  In this embodiment, as described with reference to FIG. 4B, the pixel switching TFT 102 is configured using the lower portion of the data line 3, and includes a channel region 1c, a low concentration source / drain region 1d, 1e and the low concentration source / drain regions 1d, 1e and the high concentration source / drain regions 1a, 1b are at least covered with the data line 3. Therefore, the data line 3 functions as a second light shielding film for the pixel switching TFT 102, and the channel region 1 c, the low concentration source / drain regions 1 d, 1 e, and the low concentration source / drain regions 1 d, 1 e and the high concentration source • The junction between the drain regions 1a and 1b has a structure sandwiched from above and below by at least the first light shielding film 7 and the data line 3 (second light shielding film). Further, the black matrix 6 described with reference to FIG. 2 is formed so as to overlap the data line 3 (second light shielding film), and the channel region 1c, the low concentration source / drain regions 1d and 1e, and the low concentration source. It is in a state of covering the junction between the drain regions 1d and 1e and the high concentration source / drain regions 1a and 1b and the first light-shielding film 7 disposed below them. Accordingly, the black matrix 6 functions as a third light shielding film for the pixel switching TFT 102 and exhibits a redundant function for the data line 3 as the second light shielding film. Therefore, in the liquid crystal device substrate 300 of this embodiment, the TFT 102 does not generate a leak current due to incident light from the counter substrate 31 side.

  In this embodiment, the case where the pixel switching TFT 102 has an LDD structure has been described as an example. However, the present invention is applied to an offset structure in which impurity ions are not introduced into regions corresponding to the low concentration source / drain regions 1d and 1e. May be. Such a TFT having an LDD structure or an offset structure has an advantage that a breakdown voltage is improved and a leakage current at the time of OFF can be reduced. Of course, the present invention may be applied to a self-aligned TFT in which source / drain regions are formed by implanting high-concentration impurity ions using a gate electrode (a part of the scanning line 2) as a mask.

  Modifications of the connection portion between the first light shielding film and the constant potential wiring described below have the same configuration as that of the first embodiment. In these modifications, the first light shielding film and the constant potential wiring Will be described, and other configurations will be omitted.

(Modification 1 of the connection portion between the first light-shielding film and the constant potential wiring)
As shown in FIGS. 9A and 9B, the wiring of the first light-shielding film 7 between the first interlayer insulating film 11 and the substrate 10, the second interlayer insulating film 13, and the third interlayer insulating film Contact holes 17 and 9 formed in the first interlayer insulating film 11 and the second interlayer insulating film 13, respectively, may be used for connection to the constant potential wiring 8 located between the layers 15 and 15. When such a connection structure is adopted, the step of forming the contact hole 17 in the first interlayer insulating film 11 and the step of forming the contact hole 9 in the second interlayer insulating film 13 are performed separately. . Therefore, even when the first interlayer insulating film 11 is thicker than the gate insulating film 12 by several thousand angstroms, the contact hole 5 (see FIG. 5) is formed in the high concentration source region 1a of the pixel switching TFT 102. At this time, since the contact hole 9 or the contact hole 17 having substantially the same depth is formed at the same time, the high concentration source region 1a of the TFT 102 is not etched at the time of opening.

(Modification 2 of the connection portion between the first light-shielding film and the constant potential wiring)
As shown in FIGS. 10A and 10B, the wiring portion of the first light-shielding film 7 between the first interlayer insulating film 11 and the substrate 10, the second interlayer insulating film 13 and the third interlayer insulation are provided. The connection to the constant potential wiring 8 between the film 15 and the film 15 includes a contact hole 17 formed in the first interlayer insulating film 11 and a relay electrode 16 connected to the wiring of the first light shielding film 7 through the contact hole 17. The contact hole 9 of the second interlayer insulating film 13 formed at a position corresponding to the relay electrode 16 may be used. In this case, the relay electrode 16 is formed simultaneously with the scanning line 2 and the capacitor wiring 18.

(Modification 3 of the connection portion between the first light-shielding film and the constant potential wiring)
As shown in FIGS. 11A and 11B, the wiring of the first light-shielding film 7 between the first interlayer insulating film 11 and the substrate 10, the second interlayer insulating film 13, and the third interlayer insulating film 15 is connected to the constant potential wiring 8 in the interlayer between the contact hole 17 formed in the first interlayer insulating film 11 and a wider relay connected to the wiring portion of the first light shielding film 7 through the contact hole 17. The contact hole 9 formed in the second interlayer insulating film 13 at a position shifted from the contact hole 17 in the electrode 16 and the region corresponding to the relay electrode 16 may be used. Also in this case, the relay electrode 16 is formed simultaneously with the scanning line 2 and the capacitor wiring 18.

[Modification 1 of Embodiment 1]
In the embodiment shown in FIG. 7, the one end of the wiring of the first light shielding film 7 is connected to the constant potential wiring 8, but as shown in FIG. 12, the first light shielding film Both ends of the wiring 7 may be drawn out to the outside of the display area 61 along each scanning line 2, and each of the ends on both sides may be connected to the constant potential wiring 8. Also in this case, since the first light shielding film 7 and the constant potential wiring 8 are formed between different layers, the connection structure using the contact hole 9 shown in FIG. 8, FIG. 9, FIG. 10, or FIG. Thus, the wiring of the first light shielding film 7 and the constant potential wiring 8 are connected. Other configurations are the same as described with reference to FIG.

  Also in this embodiment, the lower layer side such as the channel region 1c of the pixel switching TFT 102 is covered with the channel light shielding portion of the first light shielding film 7, so that even if there is reflected light from the back surface side of the liquid crystal device substrate 300, This light does not reach the channel region 1c of the pixel switching TFT 102 or the like. Therefore, in the liquid crystal device 100 of this embodiment, the TFT 102 does not generate a leakage current due to the reflected light from the back side of the liquid crystal device substrate 300. In addition, since the first light shielding film 7 is connected to the constant potential wiring 8 that supplies the constant voltage power supply VSSY on the low potential side of the scanning line driving circuit 104, the first light shielding film 7 is connected to the constant potential wiring 8. The potential is fixed. Therefore, TFT characteristics do not fluctuate or deteriorate under the influence of the parasitic capacitance between the semiconductor layer 1 of the TFT 102 and the first light shielding film 7.

  Furthermore, in this embodiment, since the wiring of the first light shielding film 7 is connected to the constant potential wiring 8 at both ends, the first light shielding film 7 is provided even if there is a break in the middle of the wiring. Is supplied with a constant potential. Therefore, since the first light shielding film 7 is configured with redundant wiring for wiring, the reliability is high.

[Improvement 2 of Embodiment 1]
In the form shown in FIG. 12, the constant potential is applied only from one end of each of the two constant potential wirings 8. However, as shown in FIG. In any of the cases 8, it is more preferable that a constant potential is applied from both ends thereof. With this configuration, the redundant wiring is configured also for the constant potential wiring 8 that applies a constant potential to the first light shielding film 7. Since other configurations are the same as those of the first embodiment and the improvement example 1, the description thereof is omitted.

[Modification 3 of Embodiment 1]
In this example, the basic configuration is the same as that of the first embodiment and its improved examples 1 and 2, and therefore description of common parts is omitted. In this example, as shown in FIG. 14, the wiring portion of the first light shielding film 7 is formed in a lattice shape along both the scanning line 2 and the data line 3. Therefore, the first light-shielding film 7 is further reduced in resistance and increased in redundancy. The first light-shielding film 7 overlaps the black matrix 6 (see FIG. 2) of the counter substrate 31. For this reason, the first light-shielding film 7 exhibits a redundant function with respect to the black matrix 6 of the counter substrate 31 and enables the black matrix 6 to be omitted from the counter substrate 31.

  Even in such a configuration, both ends of the wiring portion of the first light-shielding film 7 that extends along the scanning line 2 are extended to the outside of the display region 61, and the peripheral parting is performed. The wiring portion of the first light-shielding film 7 and the constant potential wiring 8 are connected to each other in a region overlapping with the light-shielding film 60 by a connection structure using the contact hole 9 shown in FIG. 8, FIG. 9, FIG. Just connect.

  Further, in the first embodiment shown in FIGS. 7, 12, 13, and 14, the constant potential is obtained by the connection structure using the contact hole 9 or the like (shown in FIG. 8, FIG. 9, FIG. 10, or FIG. 11). The wiring portion of the first light shielding film 7 connected to the wiring 8 is formed independently below each scanning line 2. The wiring portions of these first light shielding films 7 are extended, and the wiring portions extending from all the first light shielding films 7 under the region overlapping with the light shielding film 60 for parting the periphery are used as the first light shielding films. When the wiring is disconnected by electrically connecting with a conductive film made of a metal film formed in the same process as the film 7 or a metal alloy film such as a metal silicide containing these metals, This is advantageous because it provides a redundant function and the resistance of the first light-shielding film 7 can be reduced.

[Embodiment 2]
FIG. 15 is an enlarged plan view showing the periphery of two pixels formed at the end of the display area in the liquid crystal device substrate used in the liquid crystal device of this embodiment. FIG. 16 is an explanatory diagram showing a wiring portion of the first light-shielding film formed on the liquid crystal device substrate of this embodiment and a connection structure between the wiring portion and the constant potential wiring. The basic configuration of the liquid crystal device substrate 300 according to the present embodiment is as described with reference to FIGS. 1 to 5. Here, the light shielding structure formed on the liquid crystal device substrate 300 and the light shielding that constitutes the light shielding structure. The description will focus on the connection structure between the film and the constant potential wiring. Further, since the basic structure of the liquid crystal device substrate of the liquid crystal device of the present embodiment is the same as that of the liquid crystal device substrate of the liquid crystal device according to Embodiment 1, parts having common functions are denoted by the same reference numerals. Detailed description thereof will be omitted.

  Also in this embodiment, as described with reference to FIG. 5, the basic configuration is that between the first interlayer insulating film 11 and the substrate 10, the channel region 1 c of the pixel switching TFT 102, the low concentration source / drain Metal films of tungsten, titanium, chromium, tantalum, molybdenum, or the like so as to overlap at least the junctions between the regions 1d and 1e and the low-concentration source / drain regions 1d and 1e and the high-concentration source / drain regions 1a and 1b An opaque conductive light shielding film 7 made of a metal alloy film such as a metal silicide containing the above metal is formed.

  As shown in FIGS. 15 and 16, the first light-shielding film 7 includes a channel light-shielding portion that overlaps the channel region 1c on the lower layer side, and a scanning line 2 for applying a constant voltage to the channel light-shielding portion. And a wiring portion extending along the scanning line 2 from the channel light shielding portion on the lower layer side.

  In the present embodiment, the wiring portion of the first light shielding film 7 includes branch lines extending further outward from the light shielding film 60 for parting off from the display area 61 along each scanning line 2, and end portions on one side of these branch lines. It consists of a single trunk line that connects each other. The trunk line is located at a position overlapping the peripheral parting light shielding film 60 located between the display region 61 and the scanning line driving circuit 104. Here, one end of the trunk line (wiring portion) of the first light shielding film 7 overlaps with the constant potential wiring 8 that supplies the scanning line driving circuit 104 with the constant voltage power supply VSSY on the low potential side. In the portion, the wiring portion (trunk line) of the first light shielding film 7 and the constant potential wiring 8 are connected. Accordingly, since the first light shielding film 7 is connected to the constant potential wiring 8 that supplies the constant voltage power supply VSSY on the low potential side of the scanning line driving circuit 104, the first light shielding film 7 is connected to the constant potential wiring 8. It is in a fixed state and not in a floating state.

  As can be seen from FIG. 5, the wiring (trunk line) of the first light shielding film 7 is also located between the first interlayer insulating film 11 and the substrate 10, and the constant potential wiring 8 is connected to the second interlayer insulating film 13 and the second interlayer insulating film 13. Since it is between the three-layer insulating film 15, the wiring (trunk line) of the first light shielding film 7 and the constant-potential wiring 8 include the contact hole 9 shown in FIG. 8, FIG. 9, FIG. 10, or FIG. Connect according to the connection structure used. Since other configurations are substantially the same as those of the first embodiment, description thereof is omitted.

  In the liquid crystal device 100 configured as described above, the first light-shielding film 7 is formed so as to overlap the channel region 1c of the pixel switching TFT 102 and the like, as in the first embodiment. Even if there is reflected light from the side, this light does not reach at least the channel region 1 c of the pixel switching TFT 102. Therefore, the pixel switching TFT 102 does not generate a leak current due to the reflected light from the back side of the liquid crystal device substrate 300. In addition, since the first light shielding film 7 is connected to the constant potential wiring 8 that supplies the constant voltage power supply VSSY on the low potential side of the scanning line driving circuit 104, the first light shielding film 7 is connected to the constant potential wiring 8. The potential is fixed. Therefore, the same effects as those of the first embodiment are obtained, such as TFT characteristics are not fluctuated or deteriorated due to the parasitic capacitance between the semiconductor layer 1 of the TFT 102 and the first light shielding film 7. .

  Further, in the present embodiment, the wiring of the first light shielding film 7 has branch lines extending along the scanning lines 2 and trunk lines connected at the ends of these branch lines. This wiring is connected to the constant potential wiring 8 through this trunk line. Therefore, it is not necessary to connect the first light-shielding film 7 and the constant potential wiring 8 for each branch line, and it may be performed between the main line and the constant potential wiring 8. For this reason, the main line can be routed to an arbitrary position where the wiring does not pass, and the first light shielding film 7 and the constant potential wiring 8 can be connected there. In addition, if wet etching is performed when the contact hole 9 for connecting the first light shielding film 7 and the constant potential wiring 8 is formed, cracks are likely to occur in the interlayer insulating film due to the penetration of the etching solution. However, in this embodiment, there is an advantage that the trunk line is routed to an arbitrary position, and the place where the crack may occur can be limited to a safe position. Furthermore, since the first light shielding film 7 and the constant potential wiring 8 are connected between the main line and the constant potential wiring 8, the place where the crack may occur is stopped at one place. There is also an advantage of high reliability.

  This embodiment may be applied to a configuration in which dry etching is performed when the contact hole 9 for connecting the first light shielding film 7 and the constant potential wiring 8 is formed.

[Improved Example 1 of Embodiment 2]
In the form shown in FIG. 16, the wiring of the first light-shielding film 7 has a configuration in which one end of the branch line is connected to the main line, but as shown in FIG. While pulling out to the outside of the display area 61 along each scanning line 2, the ends on both sides may be connected to the main line. Also in this case, since the first light shielding film 7 and the constant potential wiring 8 are formed in different layers, the connection structure using the contact hole 9 shown in FIG. 8, FIG. 9, FIG. 10, or FIG. Thus, the main line of the wiring of the first light shielding film 7 and the constant potential wiring 8 are connected at two places. Other configurations are the same as described with reference to FIG.

  Even in such a configuration, since at least the lower layer side of the channel region 1c of the pixel switching TFT 102 is covered with the first light shielding film 7, there is reflected light from the back side of the liquid crystal device substrate 300. However, this light does not reach at least the channel region 1c of the pixel switching TFT 102 or the like. Therefore, in the liquid crystal device 100 of this embodiment, the TFT 102 does not generate a leakage current due to the reflected light from the back side of the liquid crystal device substrate 300. In addition, since the first light shielding film 7 is connected to the constant potential wiring 8 that supplies the constant voltage power supply VSSY on the low potential side of the scanning line driving circuit 104, the first light shielding film 7 is connected to the constant potential wiring 8. The potential is fixed. Therefore, TFT characteristics do not fluctuate or deteriorate under the influence of the parasitic capacitance between the semiconductor layer 1 of the TFT 102 and the first light shielding film 7.

  Further, in this embodiment, only two trunk lines are connected to the constant potential wiring 8, and it is not necessary to connect the first light shielding film 7 and the constant potential wiring 8 for each branch line. For this reason, the trunk line is routed to an arbitrary position where the wiring does not pass, such as a position adjacent to the scanning line driving circuit 104, and the first light shielding film 7 and the constant potential wiring 8 are connected at two positions there. The same effects as those of the second embodiment are obtained.

  Further, in the wiring of the first light-shielding film 7, each branch line is connected to two trunk lines at both ends, so that each branch line is fixed from the trunk line even if there is a break in the middle. A potential is supplied. Therefore, the wiring portion of the first light-shielding film 7 has a redundant wiring for each branch line, so that the reliability is high.

[Example 2 of improvement of Embodiment 2]
In the form shown in FIG. 17, the constant potential wiring 8 is connected to only one end of each of the two trunk lines. However, as shown in FIG. 18, in any of the two trunk lines, However, it is more preferable that the constant potential wiring 8 is connected to the both ends. With this configuration, redundant wiring is configured for the trunk line that applies a constant potential to each branch line in the first light shielding film 7. Since other configurations are the same as those of the second embodiment and its improved example 2, the description thereof is omitted.

[Modification 3 of Embodiment 2]
In this example, the basic configuration is the same as that of the second embodiment and its improved examples 1 and 2, and therefore description of common parts is omitted. In this example, as shown in FIG. 19, in the wiring portion of the first light shielding film 7, the branch lines are formed in a lattice shape along both the scanning lines 2 and the data lines 3. Therefore, the first light-shielding film 7 is further reduced in resistance and increased in redundancy. Further, the first light shielding film 7 overlaps the black matrix 6 (see FIGS. 2 and 15) of the counter substrate 31. For this reason, the first light-shielding film 7 exhibits a redundant function with respect to the black matrix 6 of the counter substrate 31 and enables the black matrix 6 to be omitted from the counter substrate 31.

  Even in such a configuration, out of the branch lines of the wiring portion of the first light shielding film 7, the end portions on both sides of the portion extending along the scanning line 2 are extended to the outside of the display region 61, and the peripheral parting is performed. What is necessary is just to connect the edge part of the both sides of a branch line with each trunk line in the area | region which overlaps with the light shielding film 60 for use. In the second embodiment, the constant potential wiring may be connected to the light shielding film 60 for parting around the periphery, and connected to the first light shielding film 7 in the corner region of the light shielding film 60 for parting around the periphery. Needless to say. Furthermore, in the first and second embodiments, the number of mounting terminals electrically connected to an external IC for supplying a constant potential signal (for example, VSSY) to the constant potential line 8 may be one, or two or more. The wiring resistance may be lowered or a redundant structure may be formed by short-circuiting each other in the liquid crystal device substrate.

[Embodiment 3]
FIG. 20 is an enlarged plan view showing the periphery of two pixels formed at the end of the display area in the liquid crystal device substrate used in the liquid crystal device of this embodiment. 21 is a cross-sectional view taken along line JJ ′ of FIG. The basic configuration of the liquid crystal device substrate 300 of this embodiment is as described with reference to FIGS. 1 to 5. Here, the light shielding film and the capacitor wiring 18 that constitute the light shielding structure of the liquid crystal device substrate 300 are provided. The connection structure will be mainly described. Further, since the basic structure of the liquid crystal device substrate of the liquid crystal device of the present embodiment is the same as that of the liquid crystal device substrate of the liquid crystal device according to the first and second embodiments, the same reference numerals are given to portions having common functions. A detailed description thereof will be omitted.

  Also in this embodiment, as shown in FIG. 20, the first light shielding film 7 includes a channel light shielding portion that overlaps the channel region 1c and the like, and the channel light shielding portion to the scanning line 2 in order to apply a constant voltage to the channel light shielding portion. It is comprised from the wiring extended along.

  The wiring portions of the first light shielding film 7 are connected to branch lines extending from the display region 61 to the position overlapping the light shielding film 60 for parting along the respective scanning lines 2, and ends of these branch lines are connected to each other. It consists of a trunk line. The main line of the first light shielding film 7 overlaps with the constant potential wiring 8 that supplies the constant voltage power supply VSSY on the low potential side of the scanning line driving circuit 104. The wiring portion (main line) and the constant potential wiring 8 are connected via the contact hole 9 shown in FIG. 8, FIG. 9, FIG. 10, or FIG.

  In each pixel 105, the capacitor wiring 18 is formed in parallel with the scanning line 2, and the first light shielding film 7 is formed so as to overlap the scanning line 2 and the capacitor wiring 18. Therefore, in this embodiment, the capacitor wiring 18 is not extended to the scanning line driving circuit 104, and the capacitor wiring 18 is connected to the first light shielding film via the contact hole 12f of the first interlayer insulating film 11, as shown in FIG. It is connected to 7 trunk lines.

  Even in such a configuration, since the constant voltage power supply VSSY on the low potential side of the scanning line driving circuit 104 is supplied to the first light shielding film 7 through the constant potential wiring 8, the capacitor wiring 18 is also supplied. The constant voltage power supply VSSY is supplied through the trunk line of the first light shielding film 7. Therefore, there is no need to supply a constant potential for each capacitor wiring 18 in the scanning line driving circuit 104, and accordingly, the wiring density and the number of contact holes in the scanning line driving circuit 104 are reduced. Therefore, the scanning line driver circuit 104 has an advantage that a large-scale circuit can be introduced. There is also an advantage that it is not necessary to provide a mounting terminal and a dedicated wiring for supplying a constant potential to the capacitor wiring from the outside.

  In FIG. 21, in connecting the main line of the first light-shielding film 7 and the constant potential wiring 8, as described with reference to FIG. 8A, the first interlayer insulating film 11 and the second interlayer are connected. A form using the contact hole 9 formed in the insulating film 13 is shown. However, the connection structure described with reference to FIGS. 9, 10, and 11 may be used for connection between the main line of the first light shielding film 7 and the constant potential wiring 8.

[Embodiment 4]
FIG. 22 is an enlarged plan view showing the periphery of two pixels formed at the end of the display area in the liquid crystal device substrate used in the liquid crystal device of this embodiment. 23 is a cross-sectional view taken along the line KK ′ of FIG. The basic configuration of the liquid crystal device substrate 300 of this embodiment is as described with reference to FIGS. 1 to 5. Here, the light shielding film constituting the light shielding structure of the liquid crystal device substrate 300 is used as a capacitor wiring. An explanation will be made focusing on the configuration for this purpose. Further, since the basic structure of the liquid crystal device substrate of the liquid crystal device of the present embodiment is the same as that of the liquid crystal device substrate of the liquid crystal device according to the improved example 3 of the second embodiment, the same parts are used in common parts. Reference numerals are assigned and detailed descriptions thereof are omitted.

  Also in this embodiment, as shown in FIG. 22, the first light-shielding film 7 includes a channel light-shielding portion that overlaps the channel region 1c and the like, and the scanning line 2 and the channel light-shielding portion to apply a constant voltage to the channel light-shielding portion. And wiring portions formed in a grid pattern along the data lines 3. The wiring portion of the first light shielding film 7 includes a branch line extending from the display region 61 to the region overlapping with the peripheral light shielding film 60 along each scanning line 2, and a trunk line to which ends of these branch lines are connected. It is configured. The trunk line of the first light shielding film 7 overlaps with a constant potential wiring 8 that supplies a constant potential such as the counter electrode potential LCCOM. In these overlapping portions, the wiring part (trunk line) of the first light shielding film 7 is overlapped. The constant potential wiring 8 is connected through the contact hole 9 shown in FIG. 8, FIG. 9, FIG. 10, or FIG.

  Here, since the first light-shielding film 7 is configured to substantially overlap the capacitor wiring 18 described with reference to FIGS. 4A and 4B, in this embodiment, FIG. The capacitor wiring 18 described with reference to (B) is not formed. Instead, as shown in FIG. 23, the first light-shielding film 7 is a high-concentration drain of the TFT 102 via the first interlayer insulating film 11. The storage capacitor CAP is configured using the overlap with the region 1b. That is, since the constant voltage power supply VSSY on the low potential side of the scanning line driving circuit 104 is supplied to the first light shielding film 7 through the constant potential wiring 8, the first light shielding film 7 is the drain of the TFT 102. A storage capacitor CAP using the first interlayer insulating film 11 as a dielectric film is formed between the region (the high concentration region 1b).

[Example 1 of Manufacturing Method of Substrate 300 for Liquid Crystal Device]
Of the manufacturing method of the liquid crystal device 100, the manufacturing process of the liquid crystal device substrate 300 will be described with reference to FIGS. These drawings are process cross-sectional views showing a method for manufacturing a substrate for a liquid crystal device according to this embodiment, and in any of the drawings, the left-hand part is a cross-section corresponding to the line AA ′ in FIG. A cross section at the position corresponding to the line BB ′ in FIG. 6 (cross section of the connection portion between the first light-shielding film 7 and the constant potential wiring 8) is shown on the right side of the pixel TFT section. Here, an example in which the connection portion between the first light shielding film 7 and the constant potential wiring 8 is configured as shown in FIG. 9 will be described.

  First, as shown in FIG. 24A, a metal film of tungsten, titanium, chromium, tantalum, molybdenum, or the like is formed on the entire surface of a glass substrate, for example, a transparent insulating substrate 10 made of non-crisp glass, quartz, or the like by sputtering or the like. Alternatively, after forming an opaque conductive light shielding film 70 made of a metal alloy film such as a metal silicide containing these metals to a thickness of about 500 angstroms to about 3000 angstroms, preferably about 1000 angstroms to about 2000 angstroms. Then, using the photolithography technique, patterning is performed as shown in FIG. 24B to form the first light shielding film 7. The first light shielding film 7 includes at least a channel region 1c, low-concentration source / drain regions 1d and 1e, and low-concentration source / drain regions 1d and 1e and a high-concentration source / drain of a pixel switching TFT 102 to be formed later. It forms so that the junction part with area | region 1a, 1b may be covered seeing from the back surface of the insulated substrate 10 (refer FIG. 5). Of the first light shielding film 7 formed in this way, a portion formed corresponding to the channel region of the pixel switching TFT 102 is a channel light shielding portion, and a portion formed so as to be connected to the constant potential wiring 8 Wiring part.

  Next, as shown in FIG. 24C, a first interlayer insulating film 11 having a thickness of about 500 angstroms to about 15000 angstroms, preferably about 8000 angstroms, is formed on the surface of the first light shielding film 7. The first interlayer insulating film 11 insulates the first light-shielding film 7 from the semiconductor layer 1 to be formed later. For example, a silicon oxide film using an atmospheric pressure CVD method, a reduced pressure CVD method, a TEOS gas, or the like. Or an insulating film such as a silicon nitride film. In addition, by forming the first interlayer insulating film 11 on the entire surface of the insulating substrate 10, an effect as a base film can be obtained. That is, it is possible to prevent deterioration of the characteristics of the pixel switching TFT 102 due to roughness during polishing of the surface of the insulating substrate 10, dirt due to insufficient cleaning, and the like.

  Next, as shown in FIG. 24D, a polysilicon film 1a having a thickness of about 500 angstroms to about 2000 angstroms, preferably about 1000 angstroms, is formed on the entire surface of the first interlayer insulating film 11. As a method, a monosilane gas or a disilane gas is supplied at a flow rate of about 400 cc / min to about 600 cc / min while heating the substrate 10 to about 450 ° C. to about 550 ° C., preferably about 500 ° C., and a pressure of about 20 Pa to about 40 Pa. Then, an amorphous silicon film is formed. Thereafter, annealing treatment is performed in a nitrogen atmosphere at about 600 ° C. to about 700 ° C. for about 1 hour to about 10 hours, preferably about 4 hours to about 6 hours, and solid phase growth is performed. Form. The polysilicon film 1a may be directly formed by a low pressure CVD method or the like, or silicon ions are implanted into a polysilicon film deposited by a low pressure CVD method or the like to make it amorphous and then recrystallized by annealing or the like. Then, a polysilicon film may be formed.

  Next, patterning is performed using a photolithography technique as shown in FIG. 24E to form the island-shaped semiconductor layer 1 (active layer) in the pixel switching TFT portion 102. On the other hand, the polysilicon layer 1a is completely removed at the connection portion with the constant potential wiring 8.

  Next, as shown in FIG. 24F, the semiconductor layer 1 is thermally oxidized at a temperature of about 900 ° C. to about 1300 ° C., so that the thickness of the surface of the semiconductor layer 1 is about 500 Å to about 1500 Å. A gate insulating film 12 made of a silicon oxide film is formed. By this step, the thickness of the semiconductor layer 1 is finally about 300 angstroms to about 1500 angstroms, preferably about 350 angstroms to about 450 angstroms, and the gate insulating film 12 is about 200 angstroms to about 1500 angstroms. It becomes thickness. When a large substrate of about 8 inches is used, in order to prevent warping of the substrate due to heat, the thermal oxidation time is shortened to make the thermal oxide film thin, and a high temperature silicon oxide film (on the thermal oxide film ( An HTO film) or a silicon nitride film may be deposited by a CVD method or the like to form a multilayer gate insulating film structure having two or more layers.

  Next, as shown in FIG. 25A, after a polysilicon film 201 for forming the scanning line 2 (gate electrode) is formed on the entire surface of the substrate 10, phosphorus is thermally diffused to make the polysilicon film 201 conductive. Turn into. Alternatively, a doped silicon film in which phosphorus is introduced simultaneously with the formation of the polysilicon film 201 may be used.

  Next, the polysilicon film 201 is patterned using a photolithography technique as shown in FIG. 25B, and a gate electrode (a part of the scanning line 2) is formed on the pixel switching TFT 102 side. On the other hand, the polysilicon film 201 is completely removed at the connection portion with the constant potential wiring 8. Note that the material of the scanning line 2 (gate electrode) may be a metal film, a metal silicide film, or the like, or a metal film, a metal silicide film, and a polysilicon film may be combined to form a gate electrode in multiple layers.

  In particular, since the metal film and the metal silicide film have light shielding properties, it is possible to substitute the black matrix 6 on the counter substrate 31 by wiring the scanning line 2 as a light shielding film, and the black matrix 6 on the counter substrate 31 can be omitted. it can. Thereby, it is possible to prevent the pixel aperture ratio from being lowered due to the bonding deviation between the counter substrate 31 and the liquid crystal device substrate 300.

Next, as shown in FIG. 25C, on the pixel switching TFT 102 portion and the N channel TFT portion side of the peripheral driving circuit, about 0.1 × 10 ¹³ / cm ² to about 0.1 × 10 ¹³ / cm ² to about Low-concentration impurity ions (phosphorus etc.) 19 are implanted at a dose of 10 × 10 ¹³ / cm ² , and the low-concentration source / drain is self-aligned with the gate electrode on the pixel switching TFT 102 side. Regions 1d and 1e are formed. Here, since it is located below the gate electrode, the portion where the impurity ions 100 are not introduced becomes the channel region 1 c that remains in the semiconductor layer 1. When ion implantation is performed in this manner, impurity ions are also introduced into the polysilicon layer that has been formed as the gate electrode, which further makes it conductive.

Next, as shown in FIG. 25D, a resist mask 21 having a width wider than that of the gate electrode is formed on the pixel switching TFT 102 portion and the N channel TFT portion side of the peripheral driver circuit to form high concentration impurity ions. (Phosphorus etc.) 20 is implanted at a dose of about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ² to form a high concentration source region 1a and drain region 1b.

  In place of these impurity introduction steps, high concentration impurity ions (phosphorus, etc.) are implanted in a state where a resist mask wider than the gate electrode is formed without implanting low concentration impurity ions, and a source region having an offset structure In addition, a drain region may be formed. Needless to say, the source region and the drain region having a self-aligned structure may be formed by implanting high-concentration impurity ions (such as phosphorus) using the gate electrode as a mask.

Although not shown, in order to form the P-channel TFT portion of the peripheral drive circuit, the pixel switching TFT portion 102 and the N-channel TFT portion are covered and protected with a resist, and the gate electrode is used as a mask to provide about 0.1 by implanting impurity ions such as boron at a dose of × 10 ¹⁵ / cm ² ~ about 10 × 10 ¹⁵ / cm ^2, a self-aligning manner to form source and drain regions of the P-channel. Similar to the formation of the pixel TFT portion and the N-channel TFT portion of the peripheral driver circuit, the gate electrode is used as a mask and the dose amount is about 0.1 × 10 ¹³ / cm ² to about 10 × 10 ¹³ / cm ^2. After introducing low-concentration impurity ions (boron, etc.) to form low-concentration source / drain regions in the polysilicon film, a mask wider than the gate electrode is formed to form high-concentration impurity ions (boron, etc.) May be implanted at a dose of about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ² to form the source and drain regions of the LDD structure. Further, without implanting low-concentration impurity ions, high-concentration impurity ions (boron or the like) are implanted in a state where a mask wider than the gate electrode is formed, thereby forming an offset structure source region and drain region. Also good. By these ion implantation processes, CMOS can be realized, and the peripheral drive circuit can be built in the same substrate.

  Next, as shown in FIG. 25E, a thickness of about 5000 angstroms to about 15000 is formed on the surface side of the gate electrode by a normal pressure CVD method, a low pressure CVD method or the like under a temperature condition of about 800.degree. A second interlayer insulating film 13 made of an angstrom NSG film (silicate glass film not containing boron or phosphorus), a silicon nitride film, or the like is formed. Then, for example, annealing at about 1000 ° C. is performed to activate the impurity ions introduced into the source / drain regions.

  Next, a contact hole 9 is formed in a region corresponding to the wiring portion of the first light-shielding film 7 at the connection portion with the constant potential wiring 8. In this case, the anisotropic contact hole 9 formed by dry etching such as reactive ion etching or reactive ion beam etching is advantageous for high definition because the opening diameter can be formed almost as the size of the mask. is there. Further, if dry etching and wet etching are performed in combination to form the contact hole 9 in a tapered shape, it is effective in preventing disconnection when wiring is connected.

  Next, as shown in FIG. 26A, contact holes 5 are formed in the portion corresponding to the source region 1a in the second interlayer insulating film 13 on the side of the pixel switching TFT 102 using photolithography. To do. Further, a contact hole 17 connected to the contact hole 9 is formed in the second interlayer insulating film 13 at the connection portion with the constant potential wiring 8.

  Next, as shown in FIG. 26B, an aluminum film 301 for forming the data line 3 (source electrode) is formed on the surface side of the interlayer insulating film 13 by sputtering or the like. In addition to a metal film such as aluminum, a metal silicide film or a metal alloy film may be used.

  Next, as shown in FIG. 26C, the aluminum film 301 is patterned using a photolithography technique, and a source electrode is formed as a part of the data line 3 in the pixel switching TFT 102. On the other hand, the constant potential wiring 8 is formed at the connection portion with the constant potential wiring 8.

  Next, as shown in FIG. 26D, on the surface side of the source electrode and the constant potential wiring 8 by a normal pressure CVD method, a normal pressure ozone-TEOS method, or the like under a temperature condition of about 400 ° C., for example. A third interlayer insulating film 15 including at least two layers of a BPSG film (silicate glass film containing boron or phosphorus) having a thickness of about 500 angstroms to about 15000 angstroms and an NSG film having a thickness of about 100 angstroms to about 3000 angstroms is formed. . Further, a planarizing film having no step shape may be formed by applying an organic film or the like by spin coating.

  Next, as shown in FIG. 26E, on the pixel switching TFT 102 side, a high concentration of the second and third interlayer insulating films 13 and 15 is used by using a photolithography technique and a dry etching method. A contact hole 4 is formed in a portion corresponding to the drain region 1b. Also in this case, it is advantageous for high definition to form anisotropic contact holes by dry etching such as reactive ion etching and reactive ion beam etching. Further, if dry etching and wet etching are performed in combination to form the contact hole 4 in a tapered shape, there is an effect in preventing disconnection during wiring connection.

  Next, as shown in FIG. 27A, an ITO film 140 having a thickness of about 400 angstroms to about 2000 angstroms for forming the drain electrode is formed on the surface side of the third interlayer insulating film 15 by sputtering or the like. After the formation, as shown in FIG. 27B, the ITO film 140 is patterned by using a photolithography technique, and the pixel electrode 14 is formed in the pixel switching TFT 102. Further, the ITO film 140 is completely removed at the connection portion with the constant potential wiring 8. An alignment film such as polyimide is formed on the surface of the pixel electrode 14 and is subjected to a rubbing process. The pixel electrode 14 is not limited to the ITO film, and a transparent electrode material made of a high melting point metal oxide such as a SnOx film or a ZnOx film can be used. Step coverage in Japan is also practical. In the case of configuring a reflective liquid crystal device, a film having a high reflectance such as aluminum is formed as the pixel electrode 14.

  In the step shown in FIGS. 25E and 26A, when forming the contact hole 5 without forming the contact holes 9 and 17 separately at the connection portion with the constant potential wiring 8, the contact hole is formed. If 9 is formed simultaneously, the connecting portion between the constant potential wiring 8 and the first light shielding film 7 can be configured as shown in FIG.

[Example 2 of manufacturing method of substrate 300 for liquid crystal device]
In the manufacturing method of the liquid crystal device 100, another manufacturing process of the liquid crystal device substrate 300 will be described with reference to FIGS. These figures are also process cross-sectional views showing a method for manufacturing a substrate for a liquid crystal device, and in any of the figures, a cross-section (pixel) at a position corresponding to the line AA ′ in FIG. The cross section of the TFT portion) and the right portion show a cross section (cross section of the connection portion between the first light-shielding film 7 and the constant potential wiring 8) at a position corresponding to the line BB 'in FIG. Here, an example in which the connection portion between the first light shielding film 7 and the constant potential wiring 8 is configured as shown in FIG. 10 or FIG. 11 will be described. Further, since this manufacturing method is common to the manufacturing method described above from the step shown in FIG. 24A to the step shown in FIG. 24F, the steps after the step shown in FIG. 24F will be described. .

  In this embodiment, as shown in FIG. 24F, after forming a gate insulating film 12 made of a silicon oxide film having a thickness of about 500 angstroms to about 1500 angstroms on the surface of the semiconductor layer 1 by a thermal oxidation method or the like, As shown in FIG. 28A, a contact hole 17 is formed in the first interlayer insulating film 11 at the connection portion with the constant potential wiring 8. Next, after a polysilicon film 201 for forming a gate electrode or the like is formed on the entire surface of the substrate 10, phosphorus is thermally diffused to make the polysilicon film 201 conductive. Alternatively, a doped silicon film in which phosphorus is introduced simultaneously with the formation of the polysilicon film 201 may be used.

  Next, the polysilicon film 201 is patterned using photolithography as shown in FIG. 28B, and a gate electrode (a part of the scanning line 2) is formed on the pixel TFT portion side. On the other hand, the relay electrode 16 is formed at the connection portion with the constant potential wiring 8.

  Next, as shown in FIG. 28C, low-concentration impurity ions (such as phosphorus) 19 are implanted into the pixel switching TFT 102 and the N channel TFT portion of the peripheral driver circuit using the gate electrode as a mask. Then, low concentration source / drain regions 1d and 1e are formed on the pixel switching TFT 102 side in a self-aligned manner with respect to the gate electrode. Here, since it is located immediately below the gate electrode, the portion where the impurity ions 100 are not introduced becomes the channel region 1 c that remains in the semiconductor layer 1. When ion implantation is performed in this manner, impurity ions are also introduced into the polysilicon formed as the gate electrode and the polysilicon film formed as the relay electrode 16, so that they are further made conductive. Will do.

  Next, as shown in FIG. 28D, a resist mask 21 having a width wider than that of the gate electrode is formed on the pixel switching TFT 102 portion and the N channel TFT portion side of the peripheral driver circuit to form high concentration impurity ions. (Phosphorus etc.) 20 is implanted to form a high concentration source region 1a and drain region 1b.

  Next, as shown in FIG. 28E, an NSG film having a thickness of about 5000 angstroms to about 15000 angstroms on the surface side of the gate electrode and the relay electrode 16 under a temperature condition of, for example, about 800 ° C. by CVD or the like. A second interlayer insulating film 13 made of (silicate glass film not containing boron or phosphorus) or the like is formed.

  Next, as shown in FIG. 29A, a contact hole 5 is formed in a portion corresponding to the source region 1a in the second interlayer insulating film 13 on the pixel TFT portion side by using a photolithography technique. Further, a contact hole 9 is formed at a position corresponding to the relay electrode 16 with respect to the second interlayer insulating film 13 at a connection portion with the constant potential wiring 8.

  Next, as shown in FIG. 29B, an aluminum film 301 for forming the data line 3 (source electrode) is formed on the surface side of the second interlayer insulating film 13 by sputtering or the like. In addition to a metal film such as aluminum, a metal silicide film or a metal alloy film may be used.

  Next, as shown in FIG. 29C, the aluminum film 301 is patterned using a photolithography technique, and a source electrode is formed as a part of the data line 3 in the pixel switching TFT 102 portion. On the other hand, the constant potential wiring 8 is formed at the connection portion with the constant potential wiring 8.

  Next, as shown in FIG. 29D, on the surface side of the source electrode and the constant potential wiring 8, a thickness of about 500 angstroms to about 15000 angstroms under a temperature condition of about 400 ° C. by a CVD method or the like. A third interlayer insulating film 15 including at least two layers of a BPSG film (a silicate glass film containing boron or phosphorus) and an NSG film of about 100 angstroms to about 3000 angstroms is formed.

  Next, as shown in FIG. 29E, the pixel TFT portion side corresponds to the drain region 1b of the second and third interlayer insulating films 13 and 15 by using a photolithography technique, a dry etching method, or the like. A contact hole 4 is formed in the portion to be formed.

  Next, as shown in FIG. 30A, an ITO film 140 having a thickness of about 400 angstroms to about 2000 angstroms for forming the drain electrode is formed on the surface side of the third interlayer insulating film 15 by sputtering or the like. After the formation, as shown in FIG. 30B, the ITO film 140 is patterned by using a photolithography technique, and the pixel electrode 14 is formed in the pixel TFT portion. Further, the ITO film 140 is completely removed at the connection portion with the constant potential wiring 8.

  In the steps shown in FIGS. 28B and 29A, if the position where the relay electrode 16 is formed by patterning and the position where the contact hole 17 is formed are changed, the constant potential wiring 8 and the first light shielding film 7 are changed. The connection structure can be configured in any form of FIG. 10 and FIG.

[Configuration of peripheral drive circuit]
In the present invention, since the first light-shielding film 7 is formed between the first interlayer insulating film 11 and the substrate 10, the peripheral driving circuit (scanning line driving circuit 104 and data line driving circuit 103) using multilayer wiring is used. Thus, the wiring layer is further increased by one layer. An example in which the conductive film formed simultaneously with the first light shielding film 7 is used as a wiring in the peripheral drive circuit will be described below.

(Configuration example 1 of peripheral drive circuit)
FIG. 31 is an equivalent diagram showing an example of an equivalent circuit of a shift register circuit constituting a peripheral driver circuit (scan line driver circuit 104 and data line driver circuit 103) of the active matrix liquid crystal device 100 suitable for application of the present invention. It is a circuit diagram. The circuit that latches the transfer signal may be composed of a transmission gate circuit or a clocked inverter circuit.

  FIG. 32 shows an example of a layout plan view when the S portion of the shift register circuit in FIG. 31 is integrated and formed on the liquid crystal device substrate 300. FIG. 32A shows a conventional pattern layout, and FIG. 32B shows a pattern layout to which the present invention is applied. 33A and 33B are a cross-sectional view of a C-C ′ portion in FIG. 32A and a cross-sectional view of a D-D ′ portion in FIG. 32B, respectively.

  In FIGS. 32A and 33A, reference numerals 50, 51, and 46 denote a P-type TFT for a P-type region, an N-type region, and a driver circuit, respectively. In the conventional examples shown in these drawings, the clock signal line CL for controlling the transmission gate circuit (same as the scanning line) is used to pass the wiring through the connection portion N4 between the shift register circuit at the main stage and the shift register circuit at the next stage. On the second interlayer insulating film 13 formed on the surface of the process and the same layer), the wiring 40 made of a metal film such as aluminum between the same layers formed in the same process as the data line 3 was used. As a result, in the conventional example, the source / drain electrodes 41 and 42 of the transmission gate circuit are formed in the same layer as the wiring 40. Therefore, the distance L1 between the transmission gate circuits is determined by the dimensional accuracy during the photolithography process and the etching process between the wiring 40 and the source / drain electrodes 41 and 42 of the transmission gate circuit. As the wiring 40 passes, it cannot be further miniaturized and hinders high integration.

  However, in the present embodiment, as described in the above embodiments, the first light shielding film 7 is formed between the substrate 10 and the first interlayer insulating film 11, and therefore, the first light shielding film. 7 is also formed in the peripheral drive circuit portion, and as shown in FIGS. 32B and 33B, the first light shielding film 7 is used as the wiring material of the peripheral drive circuit, thereby realizing miniaturization. . That is, as shown in FIGS. 32B and 33B, the first interlayer insulating film 11 and the substrate 10 are used as the wiring material of the connection portion N4 between the main shift register circuit and the next shift register circuit. By using the first light-shielding film 7 formed between the two, there is no wiring between the same layers as the source and drain electrodes 41 and 42 of the transmission gate circuit. Accordingly, the distance L2 between the transmission gate circuits need only consider the distance between the source / drain electrodes 41 and 42 of the adjacent transmission gate circuits. Therefore, in this embodiment, the distance L2 between the transmission gate circuits can be always smaller than the distance L1 between the conventional transmission gate circuits.

(Configuration example 2 of peripheral drive circuit)
In this example, it will be described that the characteristics of TFTs for peripheral drive circuits (scanning line drive circuit and data line drive circuit) can be improved by the same number of steps as in the prior art. FIG. 34 is an example of an equivalent circuit used in the peripheral drive circuit, and (A), (B), and (C) respectively show a clocked inverter circuit, a transmission gate circuit, and an inverter circuit.

  In FIG. 34, each of the equivalent circuits is composed of a CMOS type TFT composed of a P-channel type TFT and an N-channel type TFT, and can be formed in combination with a process for forming a pixel switching TFT. CL is a clock signal, CLB is an inverted signal of the clock signal, VDD is a constant voltage power supply on the high potential side of the peripheral drive circuit, and VSS is a constant voltage power supply on the low potential side of the peripheral drive circuit. Reference numerals 46 and 47 denote a P-channel TFT for a driving circuit and an N-channel TFT for a driving circuit, respectively. A signal input from the IN side is output to the OUT side. Needless to say, the CL signal and the CLB signal are switched in the circuit configuration as shown in FIG. 35A is a plan view showing the layout of the inverter circuit of FIG. 34C on the substrate for a liquid crystal device, and FIG. 35B is a cross section taken along line EE ′ of FIG. The figure is shown.

In this embodiment, as described in the above embodiments, the first light-shielding film 7 is formed between the substrate 10 and the first interlayer insulating film 11. The peripheral drive circuit portion is also configured. That is, as shown in FIGS. 35A and 35B, the contact hole of the first interlayer insulating film 11 with respect to the source electrode 44 of each of the P-channel TFT 46 and the N-channel TFT 47 constituting the inverter circuit. The first light shielding film 7 is connected via 5. The first light shielding film 7 is formed so as to completely cover the channel regions 52 and 53 below the gate electrode 43 of the P-channel TFT 46 and the N-channel TFT 47 with the first interlayer insulating film 11 interposed therebetween. Therefore, the voltage is applied from the source electrode 48 of the P-channel TFT 46 (constant voltage power supply VDD on the high potential side of the peripheral drive circuit) and the source electrode 49 of the N-channel TFT 47 (constant voltage power supply VSS on the low potential side of the peripheral drive circuit). The first light-shielding film 7 serves as a pseudo second gate electrode at a voltage of For this reason, in the N-channel TFT 47, the potential of the portion of the channel region 53 in contact with the gate insulating film 12 of the depletion layer is increased more than before, and the potential energy for electrons is decreased.
As a result, electrons gather at the portion of the depletion layer in contact with the gate insulating film 12 to easily form an inversion layer, so that the resistance of the semiconductor layer is lowered and the TFT characteristics are improved. In the channel region 52 of the P-channel TFT 46, a phenomenon occurs in which the electrons are replaced with holes.

  In FIG. 35B, the P-channel TFT 46 and the N-channel TFT 47 of the peripheral driver circuit are represented by a gate self-alignment structure. However, as described in the manufacturing process, the breakdown voltage of the TFT is improved and the reliability is improved. In order to improve performance, the P-channel TFT 46 and the N-channel TFT 47 of the peripheral driver circuit may be formed with an LDD structure or an offset gate structure.

(Configuration example 3 of peripheral drive circuit)
FIG. 36A is a plan view of the layout of the inverter circuit of FIG. 34C on the liquid crystal device substrate 300, and FIG. 36B is a cross-sectional view taken along the line FF ′ of FIG. The figure is shown. FIG. 36C is a cross-sectional view taken along the line GG ′ in FIG.

  In this embodiment, as described in the above embodiments, the first light-shielding film 7 is formed between the substrate 10 and the first interlayer insulating film 11. The peripheral drive circuit portion is also configured. That is, as shown in FIGS. 36A, 36B, and 36C, the first light shielding formed so as to overlap the gate electrodes 43 of the P-channel TFT 46 and the N-channel TFT 47 constituting the inverter circuit. The film 7 is connected to the gate electrode 43. Further, the first light-shielding film 7 is the same as or narrower than the gate electrode 43, and the gate regions 43 and the first electrode are formed above and below the channel regions 52 and 53 via the gate insulating film 12 and the first interlayer insulating film 11. A TFT having a double gate structure is formed so as to be sandwiched between the light shielding films 7. Further, the wiring 44 on the input side of the inverter circuit is formed in the same layer as the data line 3 and is connected to the gate electrode 43 through the contact hole 5 of the first interlayer insulating film 11 and is connected to the first interlayer insulating film. 11 is connected to the first light shielding film 7 via the contact hole 5. The contact hole 5 is opened by the same process. Therefore, in the TFT having the double gate structure, since the first light shielding film 7 functions as the second gate electrode, the TFT characteristics can be further improved by the back channel effect.

(TFT characteristics)
FIG. 37 shows characteristics of the N-channel TFT having the structure described in the configuration examples 2 and 3 of the peripheral driver circuit. In FIG. 37, a triangular mark and a solid line (a) connecting it are conventional N-channel TFTs having no other layers below the channel region, and a round mark and a solid line (b) connecting it are examples of the configuration of the peripheral drive circuit. The N-channel TFT having the structure described in 2, the square mark, and the solid line (c) connecting the square marks respectively indicate the TFT characteristics of the N-channel TFT having the structure described in the configuration example 3 of the peripheral drive circuit. The TFT size is the same for all three levels (channel length: 5 μm, channel width: 20 μm) and measured by applying a voltage of 15 V between the source and drain. The film thickness conditions were set to 1000 angstroms for the first light-shielding film 7, 1000 angstroms for the first interlayer insulating film 11, 500 angstroms for the semiconductor layer 1, and 900 angstroms for the gate insulating film 12. As a measurement result, when 15 V is applied to the gate electrode of the TFT, the N-channel TFT (characteristic indicated by a round mark and a solid line (b) connecting it) having the structure described in the configuration example 2 of the peripheral drive circuit is a conventional one. It was confirmed that about 1.5 times the on-current was obtained from the TFT of (the characteristic indicated by the triangular mark and the solid line (a) connecting it). Further, when 15V is applied to the gate electrode of the TFT, the N-channel TFT (characteristic indicated by the square mark and the solid line (b) connecting it) having the structure described in the configuration example 3 of the peripheral drive circuit is a conventional TFT. It was confirmed that an on-current of 3.0 times or more (a characteristic indicated by a triangular mark and a solid line (a) connecting the triangular mark) was obtained. Therefore, by using the N-channel TFT having the structure described in the configuration examples 2 and 3 of the peripheral drive circuit, it is possible to increase the speed and miniaturization of the peripheral drive circuit as the number of display pixels increases, and to the data line 3. Since the writing of the image signal is improved, a liquid crystal device capable of realizing a high-quality image display can be provided.

[Examples of application to projection liquid crystal devices]
FIG. 38 shows an optical system used in a prism color composition projector using three active matrix liquid crystal devices as an example of a projection display device in which the liquid crystal device 100 according to each of the embodiments is applied as a light valve. It is explanatory drawing.

  In FIG. 38, 370 is a light source such as a halogen lamp, 371 is a parabolic mirror, 372 is a heat ray cut filter, 373, 375 and 376 are blue, green and red reflecting dichroic mirrors, 374 and 377 are reflecting mirrors, respectively. Reference numerals 378, 379, and 380 denote blue, green, and red modulation light valves made of the active matrix liquid crystal device, and reference numeral 383 denotes a dichroic prism.

  In this projector, the white light emitted from the light source 370 is collected by the parabolic mirror 371, passes through the heat ray cut filter 372, blocks the heat rays in the infrared region, and only visible light enters the dichroic mirror system. Is done. First, blue light (wavelength of approximately 500 nm or less) is reflected by the blue reflecting dichroic mirror 373 and other light (yellow light) is transmitted. The reflected blue light changes its direction by the reflecting mirror 374 and enters the blue modulation light valve 378. On the other hand, the light transmitted through the blue reflecting dichroic mirror 373 is incident on the green reflecting dichroic mirror 375, the green light (having a wavelength of approximately 500 to 600 nm) is reflected, and the other light, red light (having a wavelength of approximately 600 nm or more). To Penetrate. The green light reflected by the green modulation light valve 375 enters the green modulation light valve 379. Further, the red light transmitted through the dichroic mirror 375 is changed in direction by the reflection mirrors 376 and 377 and is incident on the red modulation light valve 380.

  The light valves 378, 379, and 380 of the respective colors are driven by blue, green, and red primary color signals supplied from the image signal processing circuit, and light incident on the light valves is modulated and synthesized by the dichroic prism 383. . The dichroic prism 383 is configured such that the red reflecting surface 381 and the blue reflecting surface 382 are orthogonal to each other. The color image synthesized by the dichroic prism 383 is enlarged and projected on the screen by the projection lens 384. Furthermore, since the reflected light (return light) from the back surface of the substrate for the liquid crystal device is almost negligible, there is no need to attach a polarizing plate or film that has been subjected to antireflection treatment to the exit side of the liquid crystal device as in the past, Cost reduction can be realized.

  The liquid crystal device 100 to which the present invention is applied can suppress a leakage current in the pixel switching TFT 102 that controls the pixel electrode 14 even when strong light is irradiated, and thus can obtain a high-definition image display such as high contrast. it can. Further, R (red), G (green), and B (blue) color filter layers are provided on a counter substrate of the liquid crystal device 100 to which the present invention is applied or a projector that uses a mirror in place of the dichroic prism 383. It is also effective to use a projector in which a color screen is enlarged and projected using a single liquid crystal device 100.

  Incidentally, as shown in FIG. 38, when the dichroic prism 383 is used for color synthesis, the present invention has a particular advantage. For example, light reflected by the dichroic mirror 374 passes through the light valve 378 and is combined by the dichroic prism 383. In this case, the light incident on the light valve 378 is modulated by 90 degrees and incident on the projection lens 384. However, the light incident on the light valve 378 may leak slightly and enter the light valve 380 on the opposite side. Therefore, taking the light valve 380 as an example, the light reflected by the dichroic mirror 377 is not only incident from the incident direction side as indicated by the arrow A, but also a part of the light transmitted through the light valve 378 There is a possibility that the light passes through the dichroic prism 382 and enters the light valve 380. Further, when the light reflected by the dichroic mirror 377 passes through the light valve 380 and is incident on the dichroic prism 383, it can be slightly reflected (regular reflection) by the dichroic prism 383 and re-entered on the light valve 380. There is also sex. As described above, the light valve 380 has a large incidence of light from the incident side direction and an incident from the opposite side direction. Even in such a case, the present invention, as described in the above embodiments, For the pixel switching TFT 102, the data line 2 (second light shielding film) and the black matrix 6 (third light shielding film) of the counter substrate 31 are arranged so that light does not enter from the incident side or the opposite side of the incident side. ) And the first light-shielding film 7, the light from the incident side is transmitted by the data line 2 (second light-shielding film) and the black matrix 6 (third light-shielding film) of the counter substrate 31. The light from the opposite side is blocked by the first light blocking film 7. Accordingly, no leak current occurs in the pixel switching TFT 102.

[Modified example of liquid crystal device]
In the liquid crystal device 100 according to any of the above-described forms, as shown in FIG. 39, after the microlenses 33 are bonded to the counter substrate 31 side, for example, in a matrix shape with an adhesive 34 without any gap between pixels, By covering it with the thin glass 35, incident light can be condensed on the pixel electrode 14 of the liquid crystal device substrate 300.

  For this reason, contrast and brightness can be greatly improved. In addition, since the incident light is condensed, it is possible to prevent light from entering the channel region 1c of the pixel switching TFT 102 from an oblique direction. When the micro lens 33 is used, the black matrix 6 on the counter substrate 31 side can be omitted. According to the liquid crystal device of the present invention, since at least the first light shielding film 7 is provided below the channel region 1c of the pixel switching TFT 102, the reflected light (return light) from the back surface of the substrate 300 for the liquid crystal device is used. Since the channel region 1c is not irradiated, leakage current caused by light can be suppressed. Therefore, there is no problem even if light is collected using the microlens 33.

  In any of the forms described above, the first light-shielding film 7 is connected to the constant voltage power supply VSSY on the low potential side of the scanning line driving circuit 104, but may be connected to the constant voltage power supply VDDY on the high potential side. Needless to say, the first light-shielding film 7 may be connected to the constant voltage power supply VSSX on the low potential side of the data line driving circuit 103 or to the constant voltage power supply VDDX on the high potential side. Further, the first power supply line that supplies the counter electrode potential LCCOM from the liquid crystal device substrate 300 to the counter electrode 32 of the counter substrate 31 via the vertical conduction member 31 and the power supply line that supplies the ground potential to each of the drive circuits 103 and 104. The light shielding film 7 may be connected.

  Further, in the first and second embodiments, the wiring portion of the first light shielding film 7 extends along the scanning line 2, but it may extend along the data line 3 to the outside of the display area 61. .

It is a top view of the liquid crystal device to which this invention is applied. It is sectional drawing in the HH 'line | wire of FIG. It is a block diagram of the board | substrate for liquid crystal devices of the liquid crystal device to which this invention is applied. (A) and (B) are an equivalent circuit diagram and a plan view, respectively, showing pixels arranged in a matrix in a liquid crystal device substrate. It is sectional drawing in the AA 'line of FIG. 4 (B). FIG. 4 is an enlarged plan view showing the periphery of two pixels formed at the outermost part of the display region in the liquid crystal device substrate used in the liquid crystal device according to Embodiment 1 of the present invention. FIG. 7 is an explanatory diagram showing a wiring portion of a first light shielding film formed on the liquid crystal device substrate shown in FIG. 6 and a connection structure between the wiring portion and a constant potential wiring. FIGS. 6A and 6B are a cross-sectional view taken along the line BB ′ in FIG. 6 where the wiring portion of the first light shielding film and the constant potential wiring are cut, and the wiring portion of the light shielding film, respectively. It is an enlarged plan view of a connection portion with a constant potential wiring. FIGS. 6A and 6B are cross-sectional views corresponding to a case where Modification 1 of the connection portion between the wiring portion of the first light-shielding film and the constant potential wiring is cut along the line BB ′ in FIG. 6. FIG. 4 is an enlarged plan view of a connection portion between a wiring portion of a light shielding film and a constant potential wiring. FIGS. 6A and 6B are cross-sectional views corresponding to a case where the second modification of the connection portion between the wiring portion of the first light-shielding film and the constant potential wiring is cut along the line BB ′ in FIG. 6. FIG. 4 is an enlarged plan view of a connection portion between a wiring portion of a light shielding film and a constant potential wiring. FIGS. 6A and 6B are cross-sectional views corresponding to a case where modification 3 of the connection portion between the wiring portion of the first light-shielding film and the constant potential wiring is cut along the line BB ′ in FIG. 6. FIG. 4 is an enlarged plan view of a connection portion between a wiring portion of a light shielding film and a constant potential wiring. Description showing a wiring portion of a first light-shielding film formed on a substrate for a liquid crystal device used in a liquid crystal device according to Modification 1 of Embodiment 1 of the present invention, and a connection structure between the wiring portion and a constant potential wiring FIG. Description showing a wiring portion of a first light-shielding film formed on a substrate for a liquid crystal device used in a liquid crystal device according to Modification 2 of Embodiment 1 of the present invention, and a connection structure between the wiring portion and a constant potential wiring FIG. Description showing the wiring portion of the first light-shielding film formed on the liquid crystal device substrate used in the liquid crystal device according to Modification 3 of Embodiment 1 of the present invention, and the connection structure between the wiring portion and the constant potential wiring FIG. FIG. 6 is an enlarged plan view showing the periphery of two pixels formed at the outermost portion of a display region in a liquid crystal device substrate used in a liquid crystal device according to Embodiment 2 of the present invention. FIG. 16 is an explanatory diagram showing a wiring portion of a first light shielding film formed on the liquid crystal device substrate shown in FIG. 15 and a connection structure between the wiring portion and a constant potential wiring. Description showing the wiring portion of the first light-shielding film formed on the liquid crystal device substrate used in the liquid crystal device according to Modification 1 of Embodiment 2 of the present invention, and the connection structure between the wiring portion and the constant potential wiring FIG. Description showing the wiring portion of the first light-shielding film formed on the liquid crystal device substrate used in the liquid crystal device according to Modification 2 of Embodiment 2 of the present invention, and the connection structure between the wiring portion and the constant potential wiring FIG. Description showing the wiring portion of the first light-shielding film formed on the substrate for the liquid crystal device used in the liquid crystal device according to Modification 3 of Embodiment 2 of the present invention, and the connection structure between the wiring portion and the constant potential wiring FIG. FIG. 6 is an enlarged plan view showing the periphery of two pixels formed at the endmost part of a display area in a liquid crystal device substrate used in a liquid crystal device according to Embodiment 3 of the present invention. It is sectional drawing in the JJ 'line | wire of FIG. FIG. 6 is an enlarged plan view showing the periphery of two pixels formed at the endmost part of a display area in a liquid crystal device substrate used in a liquid crystal device according to Embodiment 4 of the present invention. It is sectional drawing in the KK 'line | wire of FIG. It is process sectional drawing which shows the manufacturing method of the board | substrate for liquid crystal devices of the liquid crystal device to which this invention is applied. FIG. 25 is a process cross-sectional view of each step performed after the step shown in FIG. 24 in the method for manufacturing a liquid crystal device substrate of a liquid crystal device to which the present invention is applied. FIG. 26 is a process cross-sectional view of each step performed after the step shown in FIG. 25 in the method for manufacturing a substrate for liquid crystal device of the liquid crystal device to which the present invention is applied. FIG. 27 is a process cross-sectional view of each step performed after the step shown in FIG. 26 in the method for manufacturing a substrate for liquid crystal device of the liquid crystal device to which the present invention is applied. FIG. 25 is a process cross-sectional view of each step performed after the step shown in FIG. 24 in another method for manufacturing a substrate for liquid crystal device of the liquid crystal device to which the present invention is applied. FIG. 29 is a process cross-sectional view of each step performed after the step shown in FIG. 28 in the method for manufacturing a substrate for liquid crystal device of the liquid crystal device to which the present invention is applied. FIG. 30 is a process cross-sectional view of each step performed after the step shown in FIG. 29 in the method for manufacturing a substrate for liquid crystal device of the liquid crystal device to which the present invention is applied. FIG. 5 is an equivalent circuit diagram showing an example of a shift register circuit that constitutes a peripheral drive circuit of a preferred liquid crystal device to which the present invention is applied. (A) is a plan view showing an example of a layout of a shift register circuit constituting a peripheral drive circuit of a liquid crystal device suitable for application of the present invention, and (B) shows a peripheral drive circuit of a conventional liquid crystal device. It is the top view which showed the layout of the shift register circuit to perform. FIG. 5A is a cross-sectional view showing an example of a layout of a shift register circuit constituting a peripheral drive circuit of a liquid crystal device suitable for application of the present invention, and FIG. 5B shows a peripheral drive circuit of a conventional liquid crystal device. It is sectional drawing which showed the layout of the shift register circuit to perform. FIG. 3 is an equivalent circuit diagram showing (A) a clocked inverter, (B) an inverter, and (C) a transmission gate that constitute a peripheral drive circuit of a preferred liquid crystal device to which the present invention is applied. FIG. 7A is a layout example of an inverter circuit constituting a peripheral drive circuit of a liquid crystal device suitable for application of the present invention, and is a cross-sectional view along (a) a plan view and (b) E-E ′. FIG. 5 is a layout example of an inverter circuit constituting a peripheral drive circuit of a liquid crystal device suitable for application of the present invention, (a) a plan view, (b) a sectional view along FF ′, and (c) GG ′. FIG. It is a current-voltage characteristic diagram of a conventional N-channel TFT and an N-channel TFT to which the present invention is applied. 1 is a schematic configuration diagram of a projector as an example of a projection display device in which a liquid crystal device using a substrate for a liquid crystal device according to the present invention is applied as a light valve. It is sectional drawing which shows the structural example which used the microlens for the opposing board | substrate side with the liquid crystal device using the board | substrate for liquid crystal devices which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor layer 1a High concentration source region 1b High concentration drain region 1c Channel region 1d Low concentration source region 1e Low concentration drain region 2 Scan line 3 Data line (second light shielding film)
4 Data line and semiconductor layer contact hole 5 Pixel electrode (drain electrode) and semiconductor layer contact hole 6 Black matrix 7 First light shielding film 8 Constant potential wiring 9 Contact hole 10 between constant potential wiring and first light shielding film Substrate 11 First interlayer insulating film 12 Gate insulating film 13 Second interlayer insulating film 14 Pixel electrode 15 Third interlayer insulating film 16 Relay electrode (conductive film)
17 Contact hole 18 between conductive film and first light shielding film Capacitance wiring 19 Low concentration phosphorus ion 20 High concentration phosphorus ion 21 Resist 31 Counter substrate 32 Counter electrode 33 Micro lens 34 Adhesive 35 Thin glass 40 Wiring 41, 42 Source of TFT or Drain electrode 43 Gate electrode 44 Inverter circuit gate signal input wiring 45 Inverter circuit drain electrode (signal output wiring)
46 P-channel TFT
47 N-channel TFT
48 Positive charge wiring (VDD) of peripheral drive circuit
49 Peripheral drive circuit negative charge wiring (VSS)
50 P-type region 51 N-type region 52 P-type channel region 53 N-type channel region 60 Light shielding film 100 for parting off Liquid crystal device 101 Data sampling circuit 102 Pixel TFT
103 Data line driving circuit 104 Scanning line driving circuit 105 Pixel 106 Vertical conduction terminal 107 Mounting terminal 108 Liquid crystal 109 Auxiliary circuit 171 Switching circuit 172, 173 Signal wiring 200 Seal material 201 Polysilicon film 300 Liquid crystal device substrate 301 Aluminum film 370 Lamp 371 Parabolic mirror 372 Heat ray cut filter 373, 375, 376 Dichroic mirror 374, 377 Reflection mirror 378 Light valve (blue)
379 Light valve (green)
380 Light valve (red)
381 Red reflecting surface 382 Blue reflecting surface 383 Dichroic prism 384 Projection lens

Claims (5)

A display area in which pixels are configured in a matrix by a plurality of data lines and a plurality of scanning lines; a peripheral drive circuit connected to at least one of the data lines and the scanning lines on the outer peripheral side of the display area; and the data A liquid crystal device substrate comprising a plurality of thin film transistors provided corresponding to lines and scanning lines, a liquid crystal sandwiched between the liquid crystal device substrate and a counter substrate, and the liquid crystal device substrate and the counter In a liquid crystal device having a sealing material for bonding a substrate,
A light-shielding film for parting around the periphery of the counter substrate, which is formed along the outer edge of the display region and defines the display region;
The liquid crystal device substrate is shielded from the channel portion of the thin film transistor and extends to a lower part of the peripheral parting light shielding film, and a side of the display region under the peripheral parting light shielding film. A liquid crystal device comprising: a light-shielding capacitive wiring having a trunk line formed so as to extend along the branch line and electrically connected to the branch line.   The liquid crystal device according to claim 1, wherein the branch line extends along the scanning line and the data line.   3. The liquid crystal device according to claim 1, wherein the capacitor wiring and the drain region of the thin film transistor constitute a storage capacitor.   4. The liquid crystal according to claim 1, wherein the peripheral parting light-shielding film is formed in an inner region of the sealant and along an outer edge of the display region. 5. apparatus. 5. A projection display device comprising the liquid crystal device according to claim 1, wherein light from a light source is modulated by the liquid crystal device, and the modulated light is enlarged and projected by projection optical means. Projection display device.

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