JP3516332B2 - Display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device suitable for receiving a low voltage signal. 2. Description of the Related Art Conventionally, in a display device represented by a liquid crystal display device, a signal is received from a device such as a word processor or a personal computer as shown in Japanese Patent Application Laid-Open No. 8-254683. Was displayed by taking timing for display. In this case, like a video signal of a television, a synchronization signal corresponding to a vertical synchronization signal or a horizontal synchronization signal, a signal indicating an effective data area, or the like is received, and the received pixel information is selectively processed. However, in recent years, as the pixel density has increased and the display capacity has increased, it has become difficult to receive these signals. In addition, the low voltage differential method (LV
When the transmission with low voltage called signal transmission and reception in DS) increases, the waveform collapse due to noise or reflection is received as if it were a correct small signal, and based on this, signal processing of pixel information etc. This is inconvenient because the image is distorted or the image cannot be displayed at all. This is inconvenient because, especially when a transmission error occurs in the signal (DE) indicating the effective data area, the image is greatly disturbed. SUMMARY OF THE INVENTION The present invention has been made in consideration of the above points, and has been made in consideration of the above circumstances.
Receiving part, and receiving the clock, the output of the receiving part
Delay means for delaying the force by n clocks;
Compare the output of the delay means and output based on the result
A display device provided with a determination unit.
The signal is composed of a binary signal, and the data transfer for one scanning line
Is a signal that maintains the same level according to the length of the
The length delayed by n clocks by the delay means is one scanning line
Is set shorter than the data transfer length of
The stage has both the output of the receiving section and the output of the delay means.
If they match, the output of the receiver is output, and
In the case of a match, the output of the judgment circuit immediately before the
It is what you have. FIG. 1 is a block diagram of a main part of a display device according to an embodiment of the present invention, and 1 is a reception receiving a data signal (data enable: DE) indicating an effective range of image information. It may be a simple terminal, a differential amplifier circuit or a buffer. 2 is a clock (data clock: DAT
CLK), and delay means for delaying the output a of the receiver 1 by n clocks. The delay means comprises an n-ary shift register or a multi-stage flip-flop. Numeral 3 compares the output a of the receiving unit 1 with the output b of the delay means 2 and outputs the output a of the receiving unit 1 when the two match, and outputs the output a when the two do not match. A determination circuit that outputs using the value of (i) is configured by appropriately combining an exclusive logic gate, a comparator, a toggle flip-flop, or the like, or by programming an operation setting circuit. Reference numeral 4 denotes a synchronization counter for generating a synchronization signal using the output c of the determination circuit 3, and reference numeral 5 denotes a data processing circuit for reproducing image information from the image signal (DATA) using the output c of the determination circuit 3. The outputs of the synchronization counter 4 and the data processing circuit 5 are guided to, for example, a TFT liquid crystal panel (neither is shown) via a driver. The display device includes, for example, such a receiving circuit 1, a delay unit 2, a determination circuit 3, a synchronization counter 4, a data processing circuit 5, a driver, a TFT liquid crystal panel, and the like. In such a configuration, the data signal (DE) indicating the effective range of image information is maintained at the H level according to the length of data transfer for one scanning line, and is relatively long for each screen. A signal for maintaining the L level, for example, if the screen has 768 scanning lines, the H level of 768 constitutes one screen with the L level interposed (see DE in FIG. 2). In contrast, a display device that receives a clock and a low-voltage differential signal will be described with reference to FIG. 2 using seven clocks (n = 7) as an example. FIG. 2A shows an example in which noise occurs when the low-voltage differential signal DE is transferred by one scanning line. For example, when the display screen is 768 × 1024 dots, 1024 dots of the image signal are transferred during this one H period.
Since the delay means 2 delays this by seven clocks, the noises Z1 and Z2 are also directly delayed as shown in FIG. 2B. The determination circuit 3 compares the original data signal a with the data signal b which is delayed by 7 clocks, and uses the value if they match, and if the two do not match, it uses the value before the mismatch. Is used to generate a new data signal c. In this case, if the original data signal a is H and the delayed data signal b is H, the output data signal c is H. If the original data signal a is L and the delayed data signal b is L, the output data signal is H. If the signal c is L, the original data signal a is delayed by H and the data signal b is L or the original data signal a is delayed by L and the data signal b is H, the output data signal c is not changed. , The noise Z as shown in FIG.
Both 1 and Z2 are removed. If the noise is too small to be picked up by the clock, it may be removed simply by passing through the delay means 3. In addition, the 7-clock delay has been described in consideration of the size of noise that normally disappears and the prevention of discomfort from the start of signal transmission to the start of display. However, it is not limited to n = 7, but a prime number of 5 to 20 Is preferred. Although the above-described example has been described using a data signal indicating a reference period as an example, the present invention can also be applied to a timing signal such as a synchronization signal. As described above, according to the present invention, a signal can be reproduced by effectively removing a data signal consisting of an H level and an L level, even if noise is likely to be present. This is particularly effective for a data signal indicating a reference period.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a main block diagram of a display device according to an embodiment of the present invention. FIG. 2 is a waveform diagram illustrating the operation of the present invention. [Description of Signs] 1 Receiver 2 Delayer 3 Judgment Unit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yutaka Nojiri 3-201 Minamiyoshikata, Tottori City, Tottori Prefecture Within Tottori Sanyo Electric Co., Ltd. (72) Inventor Kazuki Asai 3-201 Minamiyoshikata, Tottori City, Tottori Prefecture Tottori (56) References JP-A-9-81081 (JP, A) JP-A-7-253565 (JP, A) JP-A-1-272386 (JP, A) JP-A-11-161236 ( JP, A) JP-A-8-160922 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/20 633 G09G 3/20 611 G09G 3/20 612 G02F 1/133 505 G09G 3/36

Claims (1)

(57) [Claim 1] A data signal indicating an effective range of an image signal is received.
Receiving the clock, and receiving the clock and changing the output of the receiving unit to n
Delay means for delaying clock, output of receiver and delay
Judgment means to compare the output of the stage and output based on the result
A display device comprising:
Value signal and the length of data transfer for one scan line
Signal that maintains the same level in accordance with
The length delayed by n clocks by the stage is the data for one scan line.
Data transfer length is set shorter than the data transfer length,
Both the output of the receiving unit and the output of the delay unit match.
Output the output of the receiver if
In the case, the display device holds the output of the judgment circuit immediately before the mismatch .