JP2001142440A - Error diffusion circuit and video display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video display device capable of decreasing a diffused pattern characteristic to a video after error diffusion processing. SOLUTION: Input side buffers 3, 4 perform a time-base adjustment of forward scanning or backward scanning to a video signal, and it is selected by a switch circuit 2 according to a buffer selection signal from a timing generation circuit 1 to which of the input side buffers 3, 4 the video signal is to be inputted. It is selected by a switch circuit 5 according to a scanning direction selection signal whether the input side buffer not switched to input the video signal is read by the forward scanning or backward scanning, and the signal is inputted to an error diffusion processing part 6. Either of output side buffers 8, 9 is selected and written by a switch circuit 7 according to whether the signal from the error diffusion processing part 6 is forward scanning or backward scanning, and the error-diffused signal is outputted to a PDP 11 through a switch circuit 10 after adjusted in time base.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error diffusion circuit and an image display device using the same, and more particularly to an error diffusion process for reducing a gradation error between an input video signal and an output video signal in the video display device. About.

[0002]

2. Description of the Related Art Conventionally, in a video display device, when the gradation of an output video signal is smaller than that of an input video signal, an error diffusion process is performed to reduce the number of input bits to the number of output bits while reducing the number of input and output signals. The gradation error is reduced.

FIG. 2 shows a general error diffusion circuit for performing the above error diffusion processing. 2, the error diffusion circuit includes a vertical direction addition circuit 21 and a horizontal direction addition circuit 22.
, A bit width adjusting circuit 23, a one-line delay circuit 24
, A one-pixel delay circuit 25, and a diffusion amount detection circuit 26.

A video signal input as an input signal is input to a bit width adjusting circuit 23 through a vertical direction adding circuit 21 and a horizontal direction adding circuit 22, and the bit width adjusting circuit 23 reduces the number of input bits to the number of output bits. Is performed and output as an output signal.

The diffusion amount detection circuit 26 is a horizontal direction addition circuit 2
2, the amount of diffusion is detected from the error diffusion signal output from 2, and the detected signal is multiplied by a certain coefficient and weighted. The one-line delay circuit 24 delays the weighted signal to reproduce the reproduced signal generated in the pixel one line before. Vertical addition circuit 2 as an error
1, and the one-pixel delay circuit 25 delays the weighted signal and outputs the delayed signal to the horizontal direction addition circuit 21 as a reproduction error generated in a pixel one pixel before.

[0006] By the bit conversion in the above-mentioned error diffusion circuit, the gradation which does not exist is converted into the LSB (Least S
(ignitant Bit) bits are output with a certain period, and an intermediate gray level is reproduced in a pseudo manner as an average.

[0007]

In the above-described conventional error diffusion circuit, since the coefficients to be weighted in the error diffusion process are always the same, there is a problem that a characteristic diffusion pattern appears in the video after the error diffusion process. .

Accordingly, an object of the present invention is to provide an error diffusion circuit which can solve the above-mentioned problems and can reduce a diffusion pattern characteristic of an image after error diffusion processing, and an image display device using the same. It is in.

[0009]

An error diffusion circuit according to the present invention is an error diffusion circuit used as a means for generating a pseudo intermediate gradation in a video display device in which a video output gradation is smaller than a video input gradation. In addition, the generation of a regular diffusion pattern due to the weight of error diffusion is performed by inverting the diffusion direction for each field.

A video display device according to the present invention is a video display device including an error diffusion circuit for performing an error diffusion process for generating a pseudo intermediate gray level when the video output gray level is smaller than the video input gray level. Thus, the generation of a regular diffusion pattern by the weight of error diffusion in the error diffusion circuit is reversed in the diffusion direction for each field.

That is, the error diffusion circuit of the present invention comprises a PD
2. Description of the Related Art In an error diffusion circuit used as a means for generating a pseudo intermediate gray scale in a video display apparatus having a small video output gray scale with respect to a video input gray scale such as P (Plasma Display Panel), a regular error diffusion weight is used. By inverting the diffusion direction of the diffusion pattern for each field, the diffusion is made uniform, and the diffusion pattern generated by error diffusion is reduced.

More specifically, in the error diffusion circuit of the present invention, an input signal is stored in a line buffer,
An error diffusion process is performed by an error diffusion circuit that can perform reverse scanning. A timing generation circuit that toggles with a field signal is connected to these circuits, and the processing direction of the error diffusion processing is determined in accordance with “0” and “1” of the timing signal. Therefore, the diffusion direction of the error diffusion changes for each field, and it is possible to reduce the diffusion pattern characteristic of the video after the error diffusion processing.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a video display device according to one embodiment of the present invention. In FIG. 1, an image display device according to one embodiment of the present invention includes a timing generation circuit 1, switch circuits 2, 5, 7, and 10,
Input-side line buffers 3, 4, an error diffusion processing unit 6,
Output side line buffers 8 and 9 and PDP (Plasma
(Display Panel: Plasma Display) 11.

The input-side line buffers 3 and 4 store the video signal 1
The time axis of forward scanning and reverse scanning is adjusted for 00. The switch circuit 2 selects which of the two input-side line buffers 3 and 4 is to be input by a buffer selection signal 101 generated by the timing generation circuit 1 using a horizontal synchronization signal.

In the switch circuit 2, the input side line buffer which is not connected to the input of the video signal is switched by the scanning direction selection signal 102 generated by the timing generation circuit 1 using the vertical synchronizing signal to read in the forward scan or the reverse scan. The signal is selected by the circuit 5 and input to the error diffusion processing unit 6. The error diffusion processing unit 6 performs an error diffusion process for performing pseudo halftone generation on the input video signal.

The output side line buffers 8 and 9 are selected and written by the switch circuit 7 in accordance with the forward scanning and the reverse scanning, and the signals output from the error diffusion processing section 6 are written into the output side line buffers 3 and 4. After the time axis adjustment similar to that described above is performed, the signal after error diffusion is passed through the switch circuit 10 to the PDP 11.
Output to

The video signal 100 is stored in the input line buffer selected by the switch circuit 2 by the buffer selection signal 101 from the timing generation circuit 1. Here, it is assumed that the input side line buffer 3 is selected.

Since the buffer selection signal 101 is a signal that toggles between "0" and "1" in response to the horizontal synchronization signal,
This means that the input side line buffer 4 that is not turned to the input side stores the video signal one horizontal period earlier.

The input signal stored in the input side line buffer 4 is similarly selected by the switch circuit 5 to be read out by the scan direction signal 102 from the timing generation circuit 1 in the forward scan or the reverse scan. Turned. The scanning direction signal 102 is a toggle signal generated by a vertical synchronization signal.

The video signal subjected to the error diffusion processing by the error diffusion processing unit 6 is input to the output side line buffers 8 and 9 whose input destinations are switched by the switch circuit 7 by the buffer selection signal 102 in order to return the reverse scanning to the forward scanning. In the forward scan, the data is written as it is, and in the reverse scan, the data is written from the end address.

When the writing of the video signal to the output side line buffers 8 and 9 is completed, the video signal is switched by the switch circuit 10 by the buffer selection signal 101, and the video is displayed in the PDP in the forward direction.
11 is output. The reason why the input / output line buffers are used even when the error diffusion processing is performed in the forward scan is to keep the same amount of video delay in the reverse scan.

In the conventional error diffusion processing, a coefficient of error weighting may be constant, and a diffusion pattern peculiar to the intermediate gradation generated by the error diffusion processing appears.
In the present invention, since the diffusion direction is reversed for each field, the diffusion pattern is made uniform by the integration effect of the time axis, and as a result, the diffusion pattern is reduced.

In the above description, the case where the PDP 11 is used has been described. However, the present invention is not limited to the PDP 11, but is also effective in a digital display device such as a liquid crystal display which reproduces gradation in small bits by an error diffusion process or the like. is there.

[0024]

As described above, according to the present invention, an error diffusion circuit used as a means for generating a pseudo intermediate gray scale in a video display device having a smaller video output gray scale than a video input gray scale, By inverting the diffusion direction of each regular field for the generation of a regular diffusion pattern due to the weighting, the diffusion pattern characteristic of the video after the error diffusion processing can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a video display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional error diffusion circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Timing generation circuit 2, 5, 7, 10 Switch circuit 3, 4 Input side line buffer 6 Error diffusion processing part 8, 9 Output side line buffer 11 PDP 100 Video signal 101 Buffer selection signal 102 Scanning direction selection signal

Claims (8)

[Claims] 1. An error diffusion circuit used as a means for generating a pseudo intermediate gray scale in a video display device having a smaller video output gray scale than a video input gray scale, wherein the error diffusion circuit generates a regular diffusion pattern by weighting error diffusion. An error diffusion circuit characterized in that the generation direction is inverted for each field. 2. The error diffusion circuit according to claim 1, wherein the inversion of the diffusion direction is performed by forward scanning and reverse scanning of a line buffer for storing an input video signal. 3. The video signal subjected to the error diffusion processing, wherein a writing direction to a line buffer for storing the video signal is switched according to the forward scanning and the reverse scanning. Error diffusion circuit as described. 4. The error according to claim 1, wherein the inversion of the diffusion direction is performed in accordance with a toggle signal generated by a vertical synchronization signal of the video signal. Diffusion circuit. 5. An image display device comprising an error diffusion circuit for performing an error diffusion process for generating a pseudo intermediate gray level when a video output gray level is smaller than a video input gray level. A video display device characterized in that the generation of a regular diffusion pattern due to the weighting of error diffusion is inverted in the diffusion direction for each field. 6. The video display according to claim 5, further comprising a line buffer for accumulating an input video signal, wherein the inversion of the diffusion direction is performed by forward scan and reverse scan of the line buffer. apparatus. 7. A line buffer for storing a video signal subjected to the error diffusion processing by the error diffusion circuit, and a writing direction of the video signal to the line buffer is switched according to the forward scan and the reverse scan. 7. The image display device according to claim 6, wherein: 8. The video display according to claim 5, wherein the diffusion direction is inverted according to a toggle signal generated by a vertical synchronization signal of the video signal. apparatus.