JP3438171B2 - Cascade A / D converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cascade A / D converter that can operate without an error in one clock, and more particularly to a cascade A / D converter that can prevent an error from occurring due to noise.

[0002]

2. Description of the Related Art As an A / D converter, there is a cascade A / D converter having a small circuit scale, low power consumption and low input capacity.
When this cascade A / D converter is operated with one clock, it operates at a high speed, but an error occurs. Therefore, the present inventors have invented a cascade A / D converter that can be operated in one clock without error. This invention is disclosed in Japanese Unexamined Patent Publication No. 9-238077.
It is described in the publication.

Such a device will be described with reference to FIG. The device shown here is a 5-bit A / D converter, and exemplifies a cascade A / D converter that outputs an alternating binary code (hereinafter, referred to as a Gray code).

In the figure, 8a to 8d are comparators, and 9a to 8d.
9e is a latch circuit, 10a to 10c are D / A converters, 1
1a to 11c are subtractors. Reference numerals 13a to 13h are comparators, 14 to 17 are AND circuits (hereinafter, referred to as AND circuits), and 18 to 20 are exclusive OR circuits (hereinafter, EOR).
Call it a circuit. ) 21 to 23 are OR circuits (hereinafter, OR
Call it a circuit. ), 24 and 25 are AND circuits (hereinafter referred to as AN
Called D circuit. ), 100a is an analog input signal, 10
1a is a digital output signal.

Further, the comparators 13a and 13b and the AND circuit 14 constitute a window comparator 50a. Then, the comparators 13c and 13d and the AND circuit 15
Compose the window comparator 50b. The comparators 13e and 13f and the AND circuit 16 have window
It constitutes the comparator 50c. Comparators 13g, 13h
The AND circuit 17 includes a window comparator 50.
Configure d. OR circuits 21 to 23 and AND circuit 2
4, 25 constitute an error correction circuit 51.

The analog input signal 100a is supplied to the comparator 8
It is input to the non-inverting input terminals of a and 13a, the inverting input terminal of the comparator 13b, and the addition input terminal of the subtractor 11a.

The output of the comparator 8a is the latch circuits 9a and D.
The / A converter 10a is connected to one input terminal of the EOR circuit 18, and the output of the D / A converter 10a is connected to the subtraction input terminal of the subtractor 11a.

The outputs of the comparators 13a and 13b are connected to the input terminals of the AND circuit 14, respectively, and the output of the AND circuit 14 is connected to one input terminal of the OR circuit 21 and the AND terminal.
Connected to the negative logic input terminals of the circuits 15-17, 24, 25.

The output of the subtractor 11a is the comparators 8b and 13
It is connected to the non-inverting input terminal of c, the inverting input terminal of the comparator 13d, and the addition input terminal of the subtractor 11b.

The output of the comparator 8b is the D / A converter 10
b, the other input terminal of the EOR circuit 18, the EOR circuit 19
Is connected to one input terminal of the subtractor 11b, and the output of the D / A converter 10b is connected to the subtraction input terminal of the subtractor 11b.

The outputs of the comparators 13c and 13d are respectively connected to the other two positive logic input terminals of the AND circuit 15, and the output of the AND circuit 15 is one input terminal of the OR circuit 22 and the AND circuit 16. , 17, 25 negative logic input terminals.

Further, the output of the EOR circuit 18 is connected to the other input terminal of the OR circuit 21, and the output of the OR circuit 21 is connected to the latch circuit 9b.

The output of the subtractor 11b is the comparators 8c and 13c.
It is connected to the non-inverting input terminal of e, the inverting input terminal of the comparator 13f, and the addition input terminal of the subtractor 11c.

The output of the comparator 8c is the D / A converter 10
c, the other input terminal of the EOR circuit 19, the EOR circuit 20
One input terminal of the OR circuit 22 is connected to the other input terminal of the OR circuit 22. OR
The output of the circuit 22 is connected to the positive logic input terminal of the AND circuit 24, and the output of the AND circuit 24 is connected to the latch circuit 9c.

The outputs of the comparators 13e and 13f are respectively connected to the other two positive logic input terminals of the AND circuit 16, and the output of the AND circuit 16 is one input terminal of the OR circuit 23 and the AND circuit 17. Connected to the negative logic input terminal of.

The output of the subtractor 11c is the comparators 8d, 13
It is connected to the non-inverting input terminal of g and the inverting input terminal of the comparator 13h.

The output of the comparator 8d is connected to the other input terminal of the EOR circuit 20, and the output of the EOR circuit 20 is O.
It is connected to the other input terminal of the R circuit 23. OR circuit 2
The output of 3 is connected to the positive logic input terminal of the AND circuit 25, and the output of the AND circuit 25 is connected to the latch circuit 9d.

The outputs of the comparators 13g and 13h are connected to the other two positive logic input terminals of the AND circuit 17, respectively, and the output of the AND circuit 17 is connected to the latch circuit 9e.

Further, the outputs of the latch circuits 9a-9d are output as a digital output signal 101a.

The inverting input terminals of the comparators 8a to 8d are grounded, and the voltage of "+ ΔV" is applied to the non-inverting input terminals of the comparators 13b, 13d, 13f and 13h.
"-" is applied to the inverting input terminals of a, 13c, 13e and 13g.
A voltage of ΔV ”is applied respectively, provided that“ ΔV = F
S / 32 "(FS: full scale).

The operation of the apparatus shown in FIG. 7 will now be described with reference to FIGS.
Will be explained. 8 and 9 show “−FS / 2” to “+
It is a characteristic curve figure which shows each output or each input with respect to the analog input signal 100a of "FS / 2."

In the figure, (a) to (d) are outputs from the comparators 8a to 8d, (e) to (h) are outputs from the window comparators 50a to 50d, and (i) to (i).
(K) is the output of the EOR circuits 18 to 20, respectively (l)
~ (P) show the inputs of the latch circuits 9a to 9e, respectively.

The comparators 8a to 8d respectively include the analog input signal 100a, the output of the subtractor 11a and the subtractor 11b.
Of zero and the output of the subtractor 11c are determined to be zero cross.

Then, the window comparator 50a
.About.50d output "high level" when the input signal is in the vicinity of "0" and the output of the preceding window comparator is "low level".

Therefore, the window comparator 50a
Is an analog input signal 100a as shown in (e) of FIG.
Outputs "high level" near "0".

The window comparator 50b is shown in FIG.
As can be seen from the middle (b), the analog input signal 100a
May output "high level" near "0" and "± FS / 4", but the analog input signal 100a is "
In the vicinity of 0 ", the window comparator 5 in the previous stage
Since the output of 0a is "high level", (f) in FIG.
As shown in, only the vicinity of "± FS / 4" becomes "high level".

The window comparator 50c is shown in FIG.
As you can see from the middle (c), there is a possibility that it will become "high level" at 7 places, but the window comparator 5 in the previous stage
Since the high level portions of 0a and 50b are excluded, the state is as shown in (g) of FIG.

Similarly, the window comparator 50d
8 may become "high level" at 15 places as can be seen from (d) in FIG. 8, but since the "high level" part of the window comparators 50a to 50c in the previous stage is excluded, As shown in (h).

The output of the EOR circuits 18 to 20 outputs the gray code of the intermediate bit of the digital output signal 101a, but spike noise occurs as shown in (i) to (k) in FIG. You can see that This is because the output from the comparators 8a to 8d has a dull change from "high level" to "low level" or "low level" to "high level".

Here, the error correction circuit 51 corrects the portion where the spike-like noise is generated by the output of the window comparator, so that (m) through (m) in FIG.
As shown in (o), the spiked noise is removed.

That is, the spike noise of (i) in FIG. 9 is output from the window comparator 50a, and the spike noise of (j) in FIG.
With the outputs of the comparators 50a and 50b, the spiked noise of (k) in FIG. 9 can be removed by masking with the outputs of the window comparators 50a to 50c.

[0032]

The outputs of the window comparators 50a to 50c of such a device become "high level" in the range near the code transition (hereinafter referred to as the window width) and all the lower levels. Has the function of fixing the code. First stage window comparator 5
Focusing on 0a, 2 near the MSB transition point
Forcibly sets the 3rd bit to the "high level",
The 4th bit and LSB (5th bit) are forced to "low level".

The window widths for determining each bit do not necessarily have to be the same. As shown in (m) of FIG. 9, the range in which the second bit is set to “high level” can be up to half of the full scale, and as shown in (n) of FIG. 9, the third bit is full scale. 1/4 of that is acceptable. The allowable window width becomes narrower toward the lower side, and the LSB becomes 1/16 of full scale, that is, 2 LSB, as shown in (p) of FIG.

However, since the output of the window comparator 50a for detecting the MSB transition propagates to the lower side, the window width must be kept constant. For example, at the MSB transition, the second bit becomes "high". The window width when the level is set to "level" and the window width when the LSB is set to the "low level" are the same.

Therefore, when the resolution becomes high and the window width approaches the noise level, the window
If the comparator 50a malfunctions due to the influence of noise, in the worst case, an error will occur in the code of the second bit.

Therefore, an object of the present invention is to realize a cascade A / D converter which can prevent the occurrence of errors due to noise.

[0037]

According to the present invention, a comparator for converting an analog input signal into a digital signal, a latch circuit for holding the output of the comparator, and the output of the comparator are again converted into an analog signal. D / A converter and this D / A
Cascade A / C composed of a plurality of stages connected in series with a subtractor for subtracting the output of the converter from the analog signal
In the D converter, a synthesizing circuit for synthesizing the varying waveform of the code of the comparator and the varying waveform of this synthesizing circuit are input,
A plurality of code change point vicinity detection means for detecting the code change of the comparator within two or more stages of code change point vicinity detection width, and noise generated at the code change point based on the output of the code change point vicinity detection means. and a error correction circuit to remove the code change point near detector, the lower bits
It is characterized in that the width of the detection of the code change point neighborhood of the upper bits is increased .

In the present invention as described above, the synthesizing circuit synthesizes the changing waveform of the code of the comparator. The code change point vicinity detection means detects a code change within the width of the code change point vicinity detection means of two or more stages from the change waveform of this synthesis circuit. Then, the error correction circuit removes the noise generated at the code change point based on the output of the code change point vicinity detection means.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Here, the same components as those in FIG. 7 are designated by the same reference numerals and the description thereof will be omitted.

In the figure, 11d to 11f are subtractors, and 6
0a to 60c are amplifiers, 61a and 61b are analog multiplexers, 71a to 71h and 72a to 72h are comparators, 25a, 73a to 73h, 74d and 74e are AND circuits (hereinafter referred to as AND circuits), and 100b is. An analog input signal 101b is a digital output signal.

The amplifiers 60a-60c and the analog multiplexers 61a, 61b form a synthesizing circuit 60. Comparators 71a and 72a and AND circuit 73a
Compose the window comparator 70a. The comparators 71b and 72b and the AND circuit 73b form a window comparator 70b. Comparators 71c, 72
The c and AND circuit 73c form a window comparator 70c. Window comparator 70a-
70c constitutes one chord change point vicinity detection means.

Comparators 71d and 72d and AND circuit 73
d and 74d form a window comparator 70d. Comparators 71e and 72e and AND circuits 73e and 7
4e constitutes the window comparator 70e.
The window comparators 70d and 70e form a code change point vicinity detection means.

Comparators 71f and 72f and AND circuit 73
f constitutes the window comparator 70f. The comparators 71g and 72g and the AND circuit 73g form a window comparator 70g. The window comparators 70f and 70g constitute a code change point vicinity detection means.

Comparators 71h and 72h and AND circuit 73
h constitutes the window comparator 70h. The window comparator 70h constitutes a code change point vicinity detection means.

Regarding the connection relationship, the basic part is the same, and the different points are as follows. Subtractors 11d-11
f is provided in place of the subtractors 11a to 11c, and amplifies and outputs twice.

The analog input signal 100b is supplied to the comparator 8
a, 71a-71c non-inverting input terminals, comparator 72a-
72c inverting input terminal, subtractor 11d addition input terminal,
It is input to the amplifier 60a.

The outputs of the comparators 71a and 72a are connected to the input terminals of the AND circuit 73a, respectively.
The output of the circuit 73a is connected to one input terminal of the OR circuit 21. The outputs of the comparators 71b and 72b are connected to the input terminals of the AND circuit 73b, respectively.
The output of 3b is connected to the negative logic input terminals of the AND circuits 24, 74d and 74e and the select terminal of the analog multiplexer 61a. The outputs of the comparators 71c and 72c are
Each connected to the input terminal of the AND circuit 73c
The output of the D circuit 73c is the analog multiplexer 61.
It is connected to one select terminal of b.

The output of the amplifier 60a is input to one input terminal of the analog multiplexer 61a.

The output of the subtractor 11d is the non-inverting input terminal of the comparator 8b, the addition input terminal of the subtractor 11e, and the analog
It is connected to the other input terminal of the multiplexer 61a.
The output of the analog multiplexer 61a is the comparator 71
It is connected to the non-inverting input terminals of d and 71e, the inverting input terminals of comparators 72d and 72e, and the amplifiers 60b and 60c.

The outputs of the comparators 71d and 72d are connected to the AND circuit 73d, and the AND circuit 73d.
Of the AND circuit 74d is connected to the positive logic input terminal of the AND circuit 74d, and the output of the AND circuit 74d is connected to one input terminal of the OR circuit 22. The outputs of the comparators 71e and 72e are
The AND circuit 73e is connected to the AND circuit 73e.
The output of e is the positive logic input terminal of the AND circuit 74e, AN
Connected to the negative logic input terminals of the D circuits 25a and 73f,
The output of the ND circuit 74e is the analog multiplexer 6
It is connected to the other select terminal of 1b. And AN
The output of the OR circuit 23 is connected to the positive logic input terminal of the D circuit 25a, and the output of the AND circuit 25a is connected to the latch circuit 9d.

The amplifiers 60b and 60c are input to the input terminals of the analog multiplexer 61b, respectively.

The output of the subtractor 11e is the non-inverting input terminal of the comparator 8c, the addition input terminal of the subtractor 11f, and the analog
The output of the analog multiplexer 61b, which is connected to the input terminal of the multiplexer 61b, is output from the comparators 71f and 71f.
The non-inverting input terminal of g and the inverting input terminals of the comparators 72f and 72g are connected.

The outputs of the comparators 71f and 72f are connected to the positive logic input terminals of the AND circuit 73f, respectively.
The output of the AND circuit 73f is connected to one input terminal of the OR circuit 23. The outputs of the comparators 71g and 72g are connected to the input terminals of the AND circuit 73g, respectively.
The output of the circuit 73g is connected to the negative logic input terminal of the AND circuit 73h.

The output of the subtractor 11f is the comparators 8d and 71.
It is connected to the non-inverting input terminal of h and the inverting input terminal of the comparator 72h.

The outputs of the comparators 71h and 72h are connected to the positive logic input terminals of the AND circuit 73h, respectively.
The output of the AND circuit 73h is connected to the latch circuit 9e.

Further, the outputs of the latch circuits 9a-9e are output as a digital output signal 101b.

The non-inverting input terminals of the comparators 72a to 72h have "+ FS / 4" and "+ FS /" respectively.
8 "," + FS / 16 "," + FS / 4 "," + FS /
8 "," + FS / 4 "," + FS / 8 "," + FS /
The voltage of 4 "is supplied to the inverting input terminals of the comparators 71a to 71h by" -FS / 4 "," -FS / 8 ", and" -F, "respectively.
S / 16 "," -FS / 4 "," -FS / 8 "," -F
Voltages of S / 4 "," -FS / 8 ", and" -FS / 4 "are applied, respectively.

The operation of such a device will be described below.
2 to 5 are characteristic curve diagrams showing the operation of the device shown in FIG.

In FIG. 2, (a) is an analog input signal 100b from "-FS / 2" to "+ FS / 2", (b).
Is the output of the comparator 8a, (c) is the output of the subtractor 11d,
(D) is the output of the comparator 8b, (e) is the output of the subtractor 11e, and (f) is the output of the comparator 8c.

Further, in FIG. 3, (g) is a subtractor 11
output of f, (h) output of comparator 8d, (i) to (k)
Are AND circuits 73a to 73c.

In FIG. 4, (l) is the output of the analog multiplexer 61a, and (m) to (o) are ANs.
The outputs of the D circuits 74d, 73e, and 74e, (p) is the output of the analog multiplexer 61b, and (q) and (r) are A.
The ND circuits 73f and 73g.

Further, in FIG. 5, (s) is the output of the AND circuit 73h, (t) is the output of the OR circuit 21,
(U) and (v) show the outputs of the AND circuits 24 and 25a, respectively.

The comparator 8a has an analog input signal 100b.
Is determined and output to the latch circuit 9a, the D / A converter 10a, and the EOR circuit 18. D / A converter 10
a is an analog signal from the output of the comparator 8a, and the subtractor 1
Output to 1d. The subtractor 11d has an analog input signal 1
The output of the D / A converter 10a is subtracted from 00b, amplified twice, and output.

The window comparator 70a is shown in FIG.
As shown in the middle (i), the window width "FS /" in the vicinity of "0" when the analog input signal 100b shown in (a) of FIG.
2 "outputs" high level ". The output of the AND circuit 73a is used for removing spike-like noise of the second bit from the MSB.

The window comparator 70b is shown in FIG.
As shown in the middle (j), the window width "FS /" in the vicinity of "0" when the analog input signal 100b shown in (a) of FIG.
4 "outputs" high level ". The output of the AND circuit 73b is used to remove spike-shaped noise from the MSB to the third bit.

The window comparator 70c is shown in FIG.
As shown in the middle (k), the analog input signal 100b shown in FIG. 2 (a) has a window width "FS /" near "0".
At 8 "," high level "is output.

The comparator 8b judges the zero cross of the output of the subtractor 11d, and the D / A converter 10b and the EOR circuit 1
Output to 8 and 19. The D / A converter 10b is the comparator 8
The output of b is converted into an analog signal and output to the subtractor 11e. The subtractor 11e subtracts the output of the D / A converter 10b from the output of the subtractor 11d, amplifies it by two, and outputs it.

The analog multiplexer 61a synthesizes the signal obtained by amplifying the analog input signal 100b by -2 times with the amplifier 60a and the output of the subtractor 11d. That is, the window comparator 70b (AND circuit 73b)
Is the "high level" section, the output of the amplifier 60a is selected, and the "low level" section, the subtracter 1 shown in FIG.
The output of 1d is selected, the change waveform of the code shown in (l) of FIG. 4 is created, and the window comparators 70d and 70d
Enter in e.

Then, the window comparator 70d
At, the input signal outputs "high level" from the AND circuit 73d with the window width of FS / 4 near "0". That is, as can be seen from (l) in FIG.
From S / 8 to + 3FS / 8, "high level" is set. Then, as shown in (m) in FIG. 4, the window comparator 70b excludes the "high level" section, and the input signal is ANDed with the "high level" at the window width of FS / 4 near "0". Output from the circuit 74d. And AN
The output of the D circuit 74d is used to remove spike-shaped noise from the MSB to the third bit.

The window comparator 70e is shown in FIG.
As shown in middle (n), FS / when the input signal is near "0"
The AND circuit 7 sets the "high level" with the window width of 8
3e outputs, and as shown in (o) in FIG. 4, the window comparator 70b excludes the "high level" section, and the input signal is "high level" in the window width of FS / 8 near "0". Is output from the AND circuit 74e. The output of the AND circuit 73e is 4 from MSB.
It is used to remove spike noise from the bit.

The comparator 8c determines the zero cross of the output of the subtractor 11e, and the D / A converter 10c and the EOR circuit 1
Output to 9 and 20. The D / A converter 10c is the comparator 8
The output of c is converted into an analog signal and output to the subtractor 11f. The subtractor 11f subtracts the output of the D / A converter 10c from the output of the subtractor 11e, amplifies the output twice, and outputs the amplified signal.

The analog multiplexer 61b outputs the output of the analog multiplexer 61a to the amplifier 60b,
60c, the signals multiplied by -2 and +2 respectively, and the subtractor 11
and the output of e. That is, the output of the AND circuit 74e of the window comparator 70e is "high level".
Section, the output of the amplifier 60b is selected, the section of the output of the window comparator 70c is "high level", the output of the amplifier 60c is selected, and both are the "low level" section, the subtracter shown in (e) of FIG. Select the output of 11e,
The change waveform of the code shown in (p) of FIG. 4 is created and input to the window comparators 70f and 70g.

Then, the window comparator 70f
As shown in (q) in FIG. 4, the AND circuit 73e of the window comparator 70e excludes the "high level" section from the "high level" of the window width of the FS / 8 where the input signal is near "0". And outputs from the AND circuit 73f. Then, the output of the AND circuit 73f is 4 from the MSB.
It is used to remove spike noise from the bit.

The window comparator 70g is shown in FIG.
As shown in the middle (r), FS / when the input signal is near "0"
The AND circuit 73g outputs "high level" with a window width of 16. The output of the AND circuit 73g is used for LSB noise removal.

The comparator 8d determines the zero cross of the output of the subtractor 11f and outputs it to the EOR circuit 20.

Then, the window comparator 70h
As can be seen from (g) in FIG. 3, (AND circuit 73h) may become "high level" at 15 places,
Since the "high level" portion of the window comparator 70g is excluded, it becomes as shown in (s) in FIG.

As in the conventional case, the outputs of the EOR circuits 18 to 20 output the gray code having the spike-like noise of the intermediate bit of the digital output signal 101b.

Then, the error correction circuit 51 corrects the portion where the spike-like noise is generated by the output of the window comparator, and removes the spike-like noise of the gray code.

That is, the spike noise of (i) in FIG. 9 is output from the window comparator 70a, and the spike noise of (j) in FIG.
With the outputs of the comparators 70b and 70d, the spiked noise of (k) in FIG. 9 can be removed by masking with the outputs of the window comparators 70e and 70f.

As described above, since the synthesizing circuit 60 creates the code change waveform including the preceding-stage code change, the window widths of the window comparators 70a to 70h can be freely set, and the window width should be increased as the number of higher bits increases. You can That is, the influence of noise can be reduced and the accuracy can be improved.

Since the window comparators 70a to 70g having different window widths are provided in each stage, the window width for error removal can be maximized in all bits. That is, the influence of noise can be minimized and the accuracy can be improved.

Then, the subtracters 11d to 11f and the amplifier 6
By doubling the gain of 0a to 60c, the voltage accuracy of the latter stage can be eased and the circuit can be simplified. Further, the analog multiplexer may include the function of an amplifier.

The present invention may be applied not only to the cascade A / D converter that outputs the Gray code but also to the cascade A / D converter that outputs the binary code (binary code). Nor is it limited to the number of output bits.

Then, the subtractors 11d to 11f and the amplifier 6
The gain of 0a to 60c is not only doubled, but the same effect can be obtained if it is larger than 1.

Further, although the code change point vicinity detecting means has the configuration of the window comparators 70a to 70h, it may have the configuration shown in FIG. That is, the window comparators 70a to 70h are configured by the absolute value circuit 12 and the comparator 13.

[0086]

The present invention has the following effects. According to claims 1, 2 , 4, and 5 , since the code change waveform including the preceding-stage code change is created in the synthesizing circuit, the width of the code change point vicinity detection of the lower code change point vicinity detection means can be freely set. This can be set, and the width of detection of the vicinity of the code change point can be increased as the higher order bit. That is, the influence of noise can be reduced and the accuracy can be improved.

Further, since the code change point neighborhood detection means for detecting the code change point neighborhood detection width of two or more stages is provided in each stage, the code change point neighborhood detection width for error removal is set in all bits. , Can be maximized.
That is, the influence of noise can be minimized and the accuracy can be improved.

According to the third aspect , by making the gains of the subtractor and the amplifier larger than 1, the voltage accuracy of the latter stage can be eased and the circuit can be simplified.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a characteristic curve diagram showing the operation of the device shown in FIG.

FIG. 3 is a characteristic curve diagram showing an operation of the device shown in FIG.

FIG. 4 is a characteristic curve diagram showing an operation of the device shown in FIG.

5 is a characteristic curve diagram showing the operation of the device shown in FIG. 1. FIG.

FIG. 6 is a configuration diagram showing another embodiment of the code change point vicinity detection means.

FIG. 7 is a configuration diagram showing a conventional cascade A / D converter.

FIG. 8 is a characteristic curve diagram showing an operation of the device shown in FIG.

9 is a characteristic curve diagram showing the operation of the apparatus shown in FIG.

[Explanation of symbols]

8a-8d comparator 9a to 9e Latch circuit 10a-10c A / D converter 11d-11f Subtractor 12 Absolute value circuit 13 Comparator 70a-70h Window comparator 51 Error correction circuit 60 Synthesis circuit 60a-60c amplifier 61a, 61b analog multiplexer 100b analog input signal 101b Digital output signal

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-9-23077 (JP, A) JP-A-6-53832 (JP, A) JP-A-5-14199 (JP, A) JP-A-8- 195678 (JP, A) JP-A-9-69779 (JP, A) JP-A-9-69778 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03M 1/00-1 / 88

Claims (5)

(57) [Claims] 1. A comparator for converting an analog input signal into a digital signal, a latch circuit for holding the output of the comparator, and a D / A for converting the output of the comparator into an analog signal again.
A cascade A / D converter configured by cascading a plurality of stages of a converter and a subtracter that subtracts the output of the D / A converter from the analog signal, and synthesizes a change waveform of the code of the comparator. And a plurality of code change point vicinity detecting means for inputting the change waveform of the combiner circuit and detecting the code change of the comparator within two or more stages of code change point vicinity detection width, and the code change point. Yes an error correction circuit for removing noise caused by the change point of the code based on the output of the point near detector
However, the code change point vicinity detection means is
The cascade A / D converter is characterized in that the width of detection of the code change point neighborhood of the switch is increased . 2. The synthesizing circuit, which has the same gain as that of the subtractor, inputs the input of the code change point vicinity detecting means of the preceding stage and outputs an inverting output or a non-inverting output, the output of this amplifier, and the preceding stage. Select the output of the subtractor and
Analog output to the local code change point vicinity detection means
Cascade A / D converter of claim 1, characterized in that it comprises a multiplexer. 3. The cascade A / D according to claim 2, wherein the gains of the subtractor and the amplifier are set to be larger than 1.
converter. 4. A code change point near the detection means according to claim, characterized in that is constituted by window comparator 1
4. The cascade A / D converter according to any one of 3 to 3 . 5. The code change point vicinity detection means is provided with an absolute value circuit for inputting the change waveform of the synthesizing circuit and making it an absolute value, and a second comparator for comparing the output of this absolute value circuit. cascade a / D converter according to claim 1, characterized in.