JP3438170B2 - Cascade A / D converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cascade A / D converter that can operate without an error in one clock, and more particularly to a cascade A / D converter that can prevent an error from occurring due to noise.

[0002]

2. Description of the Related Art As an A / D converter, there is a cascade A / D converter having a small circuit scale, low power consumption and low input capacity.
When this cascade A / D converter is operated with one clock, it operates at a high speed, but an error occurs. Therefore, the present inventors have invented a cascade A / D converter that can be operated in one clock without error. This invention is disclosed in Japanese Unexamined Patent Publication No. 9-238077.
It is described in the publication.

Such a device will be described with reference to FIG. The device shown here is a 5-bit A / D converter, and exemplifies a cascade A / D converter that outputs an alternating binary code (hereinafter, referred to as a Gray code).

In the figure, 8a to 8d are comparators, and 9a to 8d.
9e is a latch circuit, 10a to 10c are D / A converters, 1
1a to 11c are subtractors. Reference numerals 13a to 13h are comparators, 14 to 17 are AND circuits (hereinafter, referred to as AND circuits), and 18 to 20 are exclusive OR circuits (hereinafter, EOR).
Call it a circuit. ) 21 to 23 are OR circuits (hereinafter, OR
Call it a circuit. ), 24 and 25 are AND circuits (hereinafter referred to as AN
Called D circuit. ), 100a is an analog input signal, 10
1a is a digital output signal.

Further, the comparators 13a and 13b and the AND circuit 14 constitute a window comparator 50a. Then, the comparators 13c and 13d and the AND circuit 15
Compose the window comparator 50b. The comparators 13e and 13f and the AND circuit 16 have window
It constitutes the comparator 50c. Comparators 13g, 13h
The AND circuit 17 includes a window comparator 50.
Configure d. OR circuits 21 to 23 and AND circuit 2
4, 25 constitute an error correction circuit 51.

The analog input signal 100a is supplied to the comparator 8
It is input to the non-inverting input terminals of a and 13a, the inverting input terminal of the comparator 13b, and the addition input terminal of the subtractor 11a.

The output of the comparator 8a is the latch circuits 9a and D.
The / A converter 10a is connected to one input terminal of the EOR circuit 18, and the output of the D / A converter 10a is connected to the subtraction input terminal of the subtractor 11a.

The outputs of the comparators 13a and 13b are connected to the input terminals of the AND circuit 14, respectively, and the output of the AND circuit 14 is connected to one input terminal of the OR circuit 21 and the AND terminal.
Connected to the negative logic input terminals of the circuits 15-17, 24, 25.

The output of the subtractor 11a is the comparators 8b and 13
It is connected to the non-inverting input terminal of c, the inverting input terminal of the comparator 13d, and the addition input terminal of the subtractor 11b.

The output of the comparator 8b is the D / A converter 10
b, the other input terminal of the EOR circuit 18, the EOR circuit 19
Is connected to one input terminal of the subtractor 11b, and the output of the D / A converter 10b is connected to the subtraction input terminal of the subtractor 11b.

The outputs of the comparators 13c and 13d are respectively connected to the other two positive logic input terminals of the AND circuit 15, and the output of the AND circuit 15 is one input terminal of the OR circuit 22 and the AND circuit 16. , 17, 25 negative logic input terminals.

Further, the output of the EOR circuit 18 is connected to the other input terminal of the OR circuit 21, and the output of the OR circuit 21 is connected to the latch circuit 9b.

The output of the subtractor 11b is the comparators 8c and 13c.
It is connected to the non-inverting input terminal of e, the inverting input terminal of the comparator 13f, and the addition input terminal of the subtractor 11c.

The output of the comparator 8c is the D / A converter 10
c, the other input terminal of the EOR circuit 19, the EOR circuit 20
One input terminal of the OR circuit 22 is connected to the other input terminal of the OR circuit 22. OR
The output of the circuit 22 is connected to the positive logic input terminal of the AND circuit 24, and the output of the AND circuit 24 is connected to the latch circuit 9c.

The outputs of the comparators 13e and 13f are respectively connected to the other two positive logic input terminals of the AND circuit 16, and the output of the AND circuit 16 is one input terminal of the OR circuit 23 and the AND circuit 17. Connected to the negative logic input terminal of.

The output of the subtractor 11c is the comparators 8d, 13
It is connected to the non-inverting input terminal of g and the inverting input terminal of the comparator 13h.

The output of the comparator 8d is connected to the other input terminal of the EOR circuit 20, and the output of the EOR circuit 20 is O.
It is connected to the other input terminal of the R circuit 23. OR circuit 2
The output of 3 is connected to the positive logic input terminal of the AND circuit 25, and the output of the AND circuit 25 is connected to the latch circuit 9d.

The outputs of the comparators 13g and 13h are connected to the other two positive logic input terminals of the AND circuit 17, respectively, and the output of the AND circuit 17 is connected to the latch circuit 9e.

Further, the outputs of the latch circuits 9a-9d are output as a digital output signal 101a.

The inverting input terminals of the comparators 8a to 8d are grounded, and the voltage of "+ ΔV" is applied to the non-inverting input terminals of the comparators 13b, 13d, 13f and 13h.
"-" is applied to the inverting input terminals of a, 13c, 13e and 13g.
A voltage of ΔV ”is applied respectively, provided that“ ΔV = F
S / 32 "(FS: full scale).

The operation of the apparatus shown in FIG. 4 will now be described with reference to FIGS.
Will be explained. 5 and 6 show “+ FS / 2” to “+
It is a characteristic curve figure which shows each output or each input with respect to the analog input signal 100a of "FS / 2."

In the figure, (a) to (d) are outputs from the comparators 8a to 8d, (e) to (h) are outputs from the window comparators 50a to 50d, and (i) to (i).
(K) is the output of the EOR circuits 18 to 20, respectively (l)
~ (P) show the inputs of the latch circuits 9a to 9e, respectively.

The comparators 8a to 8d respectively include the analog input signal 100a, the output of the subtractor 11a and the subtractor 11b.
Of zero and the output of the subtractor 11c are determined to be zero cross.

Then, the window comparator 50a
.About.50d output "high level" when the input signal is in the vicinity of "0" and the output of the preceding window comparator is "low level".

Therefore, the window comparator 50a
Is an analog input signal 100a as shown in FIG.
Outputs "high level" near "0".

The window comparator 50b is shown in FIG.
As can be seen from the middle (b), the analog input signal 100a
May output "high level" near "0" and "± FS / 4", but the analog input signal 100a is "
In the vicinity of 0 ", the window comparator 5 in the previous stage
Since the output of 0a is "high level", (f) in FIG.
As shown in, only the vicinity of "± FS / 4" becomes "high level".

The window comparator 50c is shown in FIG.
As you can see from the middle (c), there is a possibility that it will become "high level" at 7 places, but the window comparator 5 in the previous stage
Since the high level portions of 0a and 50b are excluded, the state is as shown in (g) of FIG.

Similarly, the window comparator 50d
As shown in (d) of FIG. 5, there is a possibility that it will be "high level" at 15 places, but since the "high level" part of the window comparators 50a-50c in the previous stage is excluded, As shown in (h).

The outputs of the EOR circuits 18 to 20 output the gray code of the intermediate bit of the digital output signal 101a, but spike noise occurs as shown in (i) to (k) in FIG. You can see that This is because the output from the comparators 8a to 8d has a dull change from "high level" to "low level" or "low level" to "high level".

Here, the error correction circuit 51 corrects the portion where the spike-like noise is generated by the output of the window comparator, so that (m) through (m) in FIG.
As shown in (o), the spiked noise is removed.

That is, the spike-like noise of (i) in FIG. 6 is output from the window comparator 50a, and the spike-like noise of (j) in FIG.
With the outputs of the comparators 50a and 50b, the spiked noise of (k) in FIG. 6 can be removed by masking with the outputs of the window comparators 50a to 50c.

[0032]

The outputs of the window comparators 50a to 50c of such a device become "high level" in the range near the code transition (hereinafter referred to as the window width) and all the lower levels. Has the function of fixing the code. First stage window comparator 5
Focusing on 0a, 2 near the MSB transition point
Forcibly sets the 3rd bit to the "high level",
The 4th bit and LSB (5th bit) are forced to "low level".

The window widths for determining each bit do not necessarily have to be the same. As shown in (m) in FIG. 6, the range in which the second bit is set to “high level” can be up to half of the full scale, and as shown in FIG. 6 (n), the third bit is full scale. Acceptable up to 1/4. The allowable window width becomes narrower toward the lower side, and the LSB becomes 1/16 of full scale, that is, 2 LSB, as shown in FIG. 6 (p).

However, since the output of the window comparator 50a for detecting the MSB transition propagates to the lower side, the window width must be kept constant. For example, at the MSB transition, the second bit becomes "high". The window width when the level is set to "level" and the window width when the LSB is set to the "low level" are the same.

Therefore, when the resolution becomes high and the window width approaches the noise level, the window
If the comparator 50a malfunctions due to the influence of noise, in the worst case, an error will occur in the code of the second bit.

Therefore, an object of the present invention is to realize a cascade A / D converter which can prevent the occurrence of errors due to noise.

[0037]

According to the present invention, a comparator for converting an analog input signal into a digital signal, a latch circuit for holding the output of the comparator, and the output of the comparator are again converted into an analog signal. D / A converter and this D / A
Cascade A / C composed of a plurality of stages connected in series with a subtractor for subtracting the output of the converter from the analog signal
In the D converter, a plurality of code change point vicinity detection means for detecting a change in the code of the plurality of stages of comparators, at least one of which is detected in the width of the code change point vicinity detection of two or more steps,
An error correction circuit for removing noise generated at the code change point based on the output of the code change point vicinity detection means is provided.
However , the code change point vicinity detection means is a code of two or more stages.
At least one of the widths of change point neighborhood detection is code change
The feature is that the width of the point neighborhood detection is increased .

In the present invention as described above, the code change point vicinity detection means detects the code change of the comparators of a plurality of stages within the width of the code change point vicinity detection of two or more stages. And
The error correction circuit removes noise generated at the code change point based on the output of the code change point vicinity detection means.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Here, the same symbols as in FIG.

In the figure, 521 to 524 are comparators, 5
25 and 526 are AND circuits, 100b is an analog input signal, and 101b is a digital output signal.

Further, the window comparator 52a
Is composed of comparators 521 and 522 and an AND circuit 525. The window comparators 50a and 52a form a code change point vicinity detection means. The window comparator 52b is composed of comparators 523 and 524 and an AND circuit 526. Window comparator 50
b and 52b constitute a chord change point vicinity detection means.

Regarding the connection relationship, the basic part is the same, and the different points are as follows. Analog input signal 1
00b is a non-inverting input terminal of the comparators 8a, 13a, 521, an inverting input terminal of the comparators 13b, 522, a subtractor 11
It is input to the addition input terminal of a.

The outputs of the comparators 521 and 522 are connected to the input terminals of the AND circuit 525, respectively.
The output of the circuit 525 is, instead of the AND circuit 14 of the conventional example, one input terminal of the OR circuit 21, the AND circuit 15,
Connect to the negative logic input terminal of 526. That is, the output of the AND circuit 14 is connected to the negative logic input terminals of the AND circuits 16 and 17.

The output of the subtractor 11a is the comparator 5
It is also connected to the non-inverting input terminal of 23 and the inverting input terminal of the comparator 524.

The outputs of the comparators 523 and 524 are connected to the input terminals of the AND circuit 526, respectively.
The output of 26 is O instead of the AND circuit 15 of the conventional example.
It is connected to one input terminal of the R circuit 22. That is, AN
The output of the D circuit 15 is connected to the negative logic input terminals of the AND circuits 16, 17, 25.

Further, the outputs of the latch circuits 9a-9d are
The digital output signal 101b is output.

A voltage of "+ 3FS / 32" is applied to the non-inverting input terminals of the comparators 522 and 524. The inverting input terminals of the comparators 521 and 523 are "-3FS /
A voltage of 32 "is applied.

The operation of such a device will be described below.
FIG. 2 is a characteristic curve diagram showing the operation of the device shown in FIG. The other characteristic curve diagrams are the same as FIGS. 5 and 6 except that FIG. 5A shows the analog input signal 100b.

In FIG. 2, (a) shows an AND circuit 525.
, And (b) shows the output of the AND circuit 526, respectively.

The comparators 8a to 8d respectively include the analog input signal 100b, the output of the subtractor 11a and the subtractor 11b.
Of zero and the output of the subtractor 11c are determined to be zero cross.

The window comparator 50a is shown in FIG.
As shown in the middle (e), the analog input signal 100b is "
"High level" is output with a window width of "FS / 16" near 0 ".

Window comparator 52a (AND
The circuit 525) outputs a "high level" with a window width of "3FS / 16" in the vicinity of "0" of the analog input signal 100b, as shown in FIG.

The window comparator 50b is shown in FIG.
As can be seen from the middle (b), the analog input signal 100a
May output "high level" with a window width of "FS / 16" near "0" and "± FS / 4", but when the analog input signal 100b is near "0", the previous window Since the output of the comparator 52a is "high level", as shown in (f) of FIG.
Only the vicinity of FS / 4 becomes "high level".

Window comparator 52b (AND
As can be seen from (b) in FIG. 5, the circuit 526) has a window width of "3FS / 16" near the analog input signal 100b of "0" and "± FS / 4", and is "high level".
May be output, but the analog input signal 100b
In the vicinity of "0", the output of the window comparator 52a in the previous stage is "high level", so that only "± FS / 4" vicinity becomes "high level" as shown in FIG. 2 (b). .

The window comparator 50c is shown in FIG.
As you can see from the middle (c), there is a possibility that it will become "high level" at 7 places, but the window comparator 5 in the previous stage
Since 0a and 50b are "high level", the window width "FS /" is eliminated as shown in FIG.
There are 4 "high levels" of 16 ".

Similarly, the window comparator 50d
As shown in (d) of FIG. 5, there is a possibility that it will be "high level" at 15 places, but since the "high level" part of the window comparators 50a-50c in the previous stage is excluded, As shown in (h), window width "
There are 8 "high levels" of FS / 16 ".

The output of the EOR circuits 18 to 20 outputs the gray code of the intermediate bit of the digital output signal 101b, but spike noise occurs as shown in (i) to (k) in FIG. You can see that This is because the output from the comparators 8a to 8d has a dull change from "high level" to "low level" or "low level" to "high level".

Here, the error correction circuit 51 corrects the portion where the spike-like noise is generated by the output of the window comparator, so that (m) to (m) in FIG.
As shown in (o), the spiked noise is removed.

That is, the spiked noise of (i) in FIG. 6 is output from the window comparator 52a, and the spiked noise of (j) in FIG.
With the outputs of the comparators 52a and 52b, the spiked noise of (k) in FIG. 6 can be removed by masking with the outputs of the window comparators 50a to 50c.

In this way, the window comparator 5
0a, 50b, 52a, and 52b detect the code change with the two-step window width, so that the error correction circuit 51 can selectively perform error removal for each bit. That is, by increasing the window width in the upper bits, it is possible to reduce the influence of noise and improve the accuracy.

The present invention may be applied not only to the cascade A / D converter that outputs the Gray code but also to the cascade A / D converter that outputs the binary code (binary code). Nor is it limited to the number of output bits.

Further, the code change vicinity detecting means for detecting the code change with the two-step window width (the width of the code change point vicinity detection) has been shown, but the code change vicinity for detecting the code change with three or more window widths is shown. It may be a detection means.

Then, the code change point vicinity detection means includes window comparators 50a to 50d, 52a and 52.
Although the configuration of b is shown, the configuration shown in FIG. 3 may be used. That is, the window comparator is composed of the absolute value circuit 12 and the comparator 13.

[0064]

The present invention has the following effects. Since the code change point vicinity detecting means detects the code change within the width of the code change point vicinity detection in two or more steps, it is possible to selectively perform error removal for each bit in the error correction circuit. That is, by increasing the width of the code change point vicinity detection in the upper bits, the influence of noise can be reduced and the accuracy can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a characteristic curve diagram showing the operation of the apparatus of FIG.

FIG. 3 is a configuration diagram showing another embodiment of the code change point vicinity detection means.

FIG. 4 is a configuration diagram showing a conventional cascade A / D converter.

5 is a characteristic curve diagram showing an operation of the device shown in FIG.

FIG. 6 is a characteristic curve diagram showing the operation of the device shown in FIG.

[Explanation of symbols]

8a to 8d Comparator 9a to 9e Latch circuit 10a to 10c D / A converter 11a to 11c Subtractor 12 Absolute value circuit 13 Comparator 50a to 50d, 52a, 52b Window comparator 51 Error correction circuit 100b Analog input signal 101b Digital Output signal

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-9-23077 (JP, A) JP-A-6-53832 (JP, A) JP-A-5-14199 (JP, A) JP-A-8- 195678 (JP, A) JP-A-9-69779 (JP, A) JP-A-9-69778 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03M 1/00-1 / 88

Claims (3)

(57) [Claims] 1. A comparator for converting an analog input signal into a digital signal, a latch circuit for holding the output of the comparator, and a D / A for converting the output of the comparator into an analog signal again.
A cascade A / D converter configured by cascade-connecting a plurality of stages of a converter and a subtractor that subtracts the output of the D / A converter from the analog signal, wherein a change in code of the plurality of stages of comparators At least one of a plurality of code change point vicinity detection means for detecting within two or more stages of code change point vicinity detection width, and noise generated at the code change point based on the output of the code change point vicinity detection means is removed. Yes and an error correction circuit for
However , the code change point vicinity detection means uses the code change in two or more stages.
At least one of the widths of near-point detection is near the code change point
Cascade A characterized by increasing the width of side detection
/ D converter. 2. A code change point near the detection means according to claim, characterized in that is constituted by window comparator 1
The described cascade A / D converter. 3. The code change point vicinity detection means is provided with an absolute value circuit for inputting a change waveform of a code and making it an absolute value, and a second comparator for comparing the output of this absolute value circuit. cascade a / D converter according to claim 1, wherein.