JP3358399B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a thin film transistor (TFT) structure on a substrate and a method of manufacturing the same, and more particularly, to a method of forming two or more polysilicon wiring layers constituting a thin film transistor at positions close to each other. And a method of manufacturing the same.

[0002]

2. Description of the Related Art Recently, in a liquid crystal display device or the like, a thin film transistor having a source and a drain region formed in a polycrystalline silicon layer has been used as a pixel transistor in order to achieve high integration.

[0003]

Since the thin film transistor is required to have a particularly high density in a liquid crystal display device, a large number of polycrystalline silicon wiring layers (including gate electrodes) are required with the high density. In between, pattern defects of polycrystalline silicon tend to occur. FIG. 13 specifically illustrates this pattern defect. As is clear from this figure, a pattern defect portion 103 having a line spacing or more is generated between the two polysilicon wiring layers 101 and 102 formed on the quartz substrate 100.

The cause of the occurrence of the pattern defect portion 103 is considered to be dust generated in the photolithography process, or a residue of the resist after the photolithography process. In particular, as shown in FIG. 14, the remaining resist is subjected to polycrystalline silicon wiring at the time of development, that is, by etching the polycrystalline silicon layer 105 (dry etching using CF4 and O2 gas) using the resist film 104 as a mask. Layer 101, 1
02, for example, the polysilicon wiring layer 10
Peeling of the resist occurs on the resist film 104 on the second side, and the peeled portion 104a moves to the polycrystalline silicon wiring layer 101 formed adjacently. As a result, the pattern defect portion 103 having a width equal to or larger than the line width of the polysilicon wiring layer (see FIG. 13 ).
Remains between the polysilicon wiring layers 101 and 102. Therefore, particularly in a portion where the line spacing between the polysilicon wiring layers 101 and 102 is smaller than the line width of the polysilicon wiring layer, a short-circuit accident (short) frequently occurs due to the polysilicon wiring layer itself. was there. When such a defect occurs, the current consumption of the driving circuit in the liquid crystal display device increases, so that the voltage in the circuit decreases,
There is a problem that an operation failure occurs or the image quality is adversely affected.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object the problem that a pattern defect generated between polysilicon wiring layers can be easily removed, and a short circuit accident due to the polysilicon wiring layer itself can be prevented. Without occurring
It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can prevent malfunction and deterioration of quality.

[0006]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device having two or more polysilicon wiring layers constituting a thin film transistor at positions close to each other on a substrate, wherein the thin film transistor is
The source and drain are located below the wiring layer via the gate insulating film.
And at least a region between the two or more adjacent polysilicon wiring layers adjacent to each other in the gate insulating film forming the thin film transistor is selectively removed and generated between the polysilicon wiring layers. It is characterized in that the pattern defect is removed.

Further, a method of manufacturing a semiconductor device according to the present invention
A method of manufacturing a semiconductor device having two or more polycrystalline silicon wiring layers constituting a thin film transistor at positions close to each other on a substrate, comprising: Forming a crystalline silicon layer, forming an insulating film serving as a gate insulating film on the first polycrystalline silicon layer, and then forming a second polycrystalline silicon wiring layer on the insulating film; Forming a crystalline silicon layer; forming a first resist film having a wiring pattern including a gate electrode on the second polycrystalline silicon layer; using the first resist film as a mask to form the second resist film; Selectively removing the crystalline silicon layer to form two or more polycrystalline silicon wiring layers; and removing the first resist film, and then removing the polycrystalline silicon wiring layer from the polycrystalline silicon wiring layer and the insulating film. To form a second resist film having a gate insulating layer pattern, performs the steps of forming a gate insulating film by selectively removing said insulating film the second resist film as a mask, the gate insulating film
Forming a, the insulating film, the step of removing the pattern defect generated in the polycrystalline silicon wiring layers by selectively removing the area corresponding to two or more adjacent polysilicon wiring layers Including, after this,
An interlayer insulating film on a polycrystalline silicon wiring layer
Contact holes for connection to source and drain
The step of forming is performed .

In the method for manufacturing a semiconductor device according to the present invention, the opening pattern corresponding to the region between at least two adjacent polysilicon wiring layers is formed in the second resist film together with the gate insulating film pattern. To form
By selectively removing the insulating film using the second resist film as a mask, a gate insulating film is formed, and at the same time, a pattern defect portion generated between the polycrystalline silicon wiring layers is removed. an opening pattern provided on the second resist film, than the wiring width of the distribution <br/> line spacing of the polycrystalline silicon wiring layers each polysilicon wiring layer may be a manner of providing a small area.

[0009]

In the semiconductor device of the present invention, at least a region between two or more adjacent polysilicon wiring layers of a gate insulating film constituting a thin film transistor is selectively removed, and a region between the adjacent polysilicon wiring layers is removed. Since the pattern defect generated in the above-mentioned process is removed, a short circuit accident between the polysilicon wiring layers is eliminated.

In the method of manufacturing a semiconductor device according to the present invention, after forming two or more polysilicon wiring layers, a region corresponding to the adjacent polysilicon wiring layers of the gate insulating film is selectively removed. Therefore, the pattern defect generated between the polysilicon wiring layers is removed. In particular, the second
In the case where an opening pattern corresponding to a region between two or more adjacent polysilicon wiring layers is formed together with a gate insulating film pattern on the resist film, the insulating film is formed using the second resist film as a mask. When selectively removed, a gate insulating film is formed, and at the same time, a pattern defect generated between the polysilicon wiring layers is removed.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Prior to the description of the embodiment, the basic principle of the present invention will be described with reference to FIG. That is, in the present invention, a thin film transistor 2 is formed at a position close to each other on a substrate, for example, a quartz substrate (transparent insulating substrate) 11.
After forming the above polycrystalline silicon wiring layers 12 and 13,
The pattern of the gate insulating film is formed by selectively removing (etching) the insulating film formed beforehand under the polycrystalline silicon wiring layers 12 and 13. At this time, a gate film is formed on a resist film serving as a mask. An opening is formed along with the insulating film pattern so as to correspond to the adjacent region between the polysilicon wiring layers 12 and 13, and the insulating film is selectively etched using the resist film as a mask to form the insulating film opening 14a. Form. Thus, in the present invention, the pattern defect portion 15 generated at the time of forming the polycrystalline silicon wiring layers 12 and 13 (photolithography step) can be removed at the same time as forming (patterning) the gate insulating film.

FIG. 2 is a plan view showing an example in which the present invention is specifically applied to a pixel transistor (thin film transistor) of a liquid crystal display device. As described above, high density is required in the thin film transistor of the liquid crystal display device, and a polycrystalline pattern defect portion 15 is likely to be generated in the vicinity of the polycrystalline silicon wiring layers 12 and 13, thereby causing a short circuit accident. Cheap. In FIG. 2, two polysilicon wiring layers 12 and 13 are arranged in parallel, and a part (gate electrode 12a) of one polysilicon wiring layer 12 and another polysilicon wiring layer 13 are formed. The gap is closest, and the pattern defect portion 15 is easily generated.

In this embodiment, the polysilicon wiring layer 1
Under the layers 2 and 13, a polycrystalline silicon layer 16 in which source, drain and channel regions constituting a thin film transistor are formed via an insulating film (gate insulating film). The source region of the polycrystalline silicon layer 16 is connected to the polycrystalline silicon wiring layer 12 through the contact hole 17.
(Al) wiring layer 1 formed on layer 13
The drain region of the polysilicon layer 16 is electrically connected to a transparent electrode (ITO (indium titanium nitride) formed on the polysilicon wiring layers 12 and 13 via the contact hole 19. (Oxide) It is electrically connected to the film 20).

In such a thin film transistor, when the gate insulating film under the polycrystalline silicon wiring layers 12 and 13 is patterned, a resist film serving as a mask is provided between the polycrystalline silicon wiring layers 12 and 13. An opening is formed corresponding to the adjacent region, and the insulating film is selectively etched using the resist film as a mask (that is, an insulating film opening 14b corresponding to the opening of the resist film is formed in the gate insulating film). Accordingly, the pattern defect portion 15 generated during the formation of the polysilicon wiring layers 12 and 13 is removed by etching together with the insulating film. Thereby, the polysilicon wiring layers 12 and 13 are formed.
There is no short circuit between them.

The distance between the insulating film opening 14b and the polysilicon wiring layer 12 is determined by the alignment accuracy and the etching accuracy of the photolithography apparatus. Incidentally, it is preferable that the same principal components of a gas for etching gas and polycrystalline silicon wiring layer 12 for etching the insulating film, for example, both CF ₄ / O
_It is preferable to use _two types of gas.

FIG. 3 shows the polycrystalline silicon wiring layers 12 and 13.
FIG. 3 shows the occurrence rate of short-circuit accidents (shorts) between the method according to the present invention and the conventional method. As described above, according to the method of the present invention, it can be seen that the short-circuit occurrence rate is significantly reduced. FIG. 4 shows an equivalent circuit of a test apparatus used for this evaluation. Two parallel polysilicon wiring layers 12 and 13 are connected to a positive electrode 21 and a negative electrode connected to a power supply 24, respectively. 22 is connected, and the current flowing therethrough is measured by an ammeter 23 to determine whether or not a short circuit has occurred.

Next, referring to FIGS. 5 and 6, a more specific structure of the thin film transistor of the present invention and a method of manufacturing the same will be described. FIG. 5 shows a cross-sectional structure of the thin film transistor taken along the line AA of FIG.

The thin film transistor 30 is provided on a substrate, for example, a quartz substrate 31. A polycrystalline silicon layer (first polycrystalline silicon layer) 32 is provided on a quartz substrate 31. In this polycrystalline silicon layer 32, n ⁺ regions 32 a and 32 b serving as a source and a drain and n ⁻ regions 32 c and 32 ⁻
32d are formed respectively. Polycrystalline silicon layer 3
The channel region is between the n ^- regions 32c and 32d of the second.

On the channel region of the polycrystalline silicon layer 32, a polycrystalline silicon wiring layer 34 serving as a gate electrode and a wiring is provided via a gate insulating film 33. A polysilicon wiring layer 41 is provided adjacent to the polysilicon wiring layer. Further, an interlayer insulating film 35 made of, for example, a PSG (phosphorus silicate glass) film is provided on the quartz substrate 31. A contact hole 36 is provided in the interlayer insulating film 35.
6, an aluminum (Al) wiring layer 37 is electrically connected to n ⁺ region 32a of polycrystalline silicon layer 32. On the interlayer insulating film 35, an interlayer insulating film 38 also made of a PSG film is formed. A contact hole 39 is formed in the interlayer insulating film 38, and a transparent electrode (ITO) is formed on an inner wall surface of the contact hole 39 and a peripheral portion thereof.
A membrane 40) is provided. On the interlayer insulating film 38, a silicon nitride film (hydrogen blocking layer) formed by plasma CVD (Chemical Vapor Deposition) facing the polycrystalline silicon wiring layer (gate electrode) 34 is used. Si ₃ N ₄ ) 41 are formed.

In the thin film transistor 30, at least the region between the adjacent polysilicon wiring layers 34 and 41 of the gate insulating film 33 is selectively removed, and the pattern defect portion of the polysilicon wiring layer thereon is removed. Is removed, the occurrence of a short circuit between the polysilicon wiring layers 34 and 41 is reduced as described above.

Next, a method of manufacturing the thin film transistor 30 having the above structure will be described in detail with reference to FIGS.

First, as shown in FIG. 7A, polycrystalline silicon is deposited on a quartz substrate 31 by, for example, a CVD method and patterned to form a polycrystalline silicon layer (first polycrystalline silicon layer) (film). (Thickness: 400 nm) 32 is formed.

Next, as shown in FIG. 7B, an oxide film (SiO ₂ ) (film thickness: 1 n) is formed on the polycrystalline silicon layer 32.
m) / nitride film (Si ₃ N ₄ ) (thickness: 1000 nm) /
An insulating film 33 </ _b > A to be a gate insulating film 33 is formed by a stacked film of an oxide film (SiO ₂ ) (thickness: 1000 nm). Here, the oxide film (SiO ₂ ) is formed by thermal oxidation, and the nitride film (Si ₃ N ₄ ) is formed by LPCVD (Low Pressure).
It is formed by a CVD method.

Next, as shown in FIG. 7C, a polycrystalline silicon layer (second polycrystalline silicon layer) 34A (film thickness: 40) serving as a polycrystalline silicon wiring layer 34 is formed on the insulating film 33A.
0 nm) is formed by the LPCVD method. Subsequently, although not shown, for example, CVD is performed on the polycrystalline silicon layer 34A.
By forming a PSG film by a method and performing an annealing process, impurities (phosphorus) are introduced into the polycrystalline silicon layer 34A to reduce the resistance.

Next, as shown in FIG. 8A, a resist film 42 having a pattern corresponding to the polysilicon wiring layer 34 is formed on the polysilicon layer 34A. Subsequently, as shown in FIG. 8B, the polysilicon layer 34A is selectively etched using the resist film 42 as a mask to form the polysilicon wiring layer 34. At this time, although not shown, simultaneously with the polysilicon wiring layer 41,
(See FIG. 6). As the etching method, for example, a dry etching method using CF ₄ and O ₂ as an etching gas is used. At this point, a pattern defect is likely to occur between the polycrystalline silicon wiring layer 34 and the polycrystalline silicon wiring layer 41 as described above, and they are connected to each other and short-circuited.

Next, after removing the resist film 42, FIG.
As shown in FIG. 1C, a resist film 43 serving as a mask for etching a gate insulating film is applied and formed so as to cover the polysilicon wiring layer. Although not shown in FIG. 8 (c), the resist film 43 includes the gate insulating film pattern and the polysilicon wiring layers 34 and 4 as described above.
An opening is formed in advance in correspondence with an adjacent region between the two (that is, a portion where a pattern defect portion has occurred). Therefore, by selectively etching the insulating film 33A using the resist film 42 as a mask, the pattern defect portion is removed at the same time that the gate insulating film 33 is formed. As an etching method, for example, CF is used as an etching gas.
A dry etching method using ₄ and O ₂ is used.

The following is the same as the conventional process. That is, as shown in FIG. 9A, the resist film 43 is removed, and then, as shown in FIG. 9B, the n-type impurities, for example, arsenic ions ( As ⁺ ) is implanted to form n ⁻ regions 32c and 32d to be LDD (Low Doped Drain) regions. Subsequently, although not shown, a resist film is formed so as to cover the polycrystalline silicon wiring layer 34 and the gate insulating film 33, and using this resist film as a mask, an n-type impurity such as arsenic ion (As ⁺ ) is similarly implanted to form a source. , N ⁺ to be the drain region
Regions 32a and 32b are formed. Thus, a thin film transistor 30 is formed.

Next, as shown in FIG. 10A, a quartz substrate 31 is
An interlayer insulating film (PSG film) 35 is formed by a CVD method. Subsequently, as shown in FIG. 10B, after a contact hole 36 is formed in the interlayer insulating film 35 by wet etching using HF, an aluminum wiring layer (thickness: 1000 nm) 37 is formed by a vapor deposition method. Aluminum (Al) wiring layer 37 is electrically connected to n ⁺ region 32a of polycrystalline silicon layer 32 through contact hole. Subsequently, as shown in FIG.
An interlayer insulating film (thickness: 1000 nm) 38 made of a PSG film is formed on the interlayer insulating film 35 by the same CVD method.

Next, as shown in FIG. 11A, a silicon nitride film 41 as a hydrogen blocking layer is formed on the interlayer insulating film 38 by plasma CVD so as to face the polycrystalline silicon wiring layer (gate electrode) 34. To form Subsequently, FIG.
As shown in (b), a contact hole 39 is formed in the interlayer insulating film 38 by wet etching using HF. Finally, as shown in FIG. 12, a transparent electrode (ITO film 40) is formed on the inner wall surface of the contact hole 39 and its peripheral portion by the CVD method, and is subjected to a heat treatment (annealing), as shown in FIG. The thin film transistor 30 can be manufactured.

As described above, according to the manufacturing method of this embodiment,
Polycrystalline silicon wiring layer 3 adjacent to gate insulating film 33
Since a region corresponding to a region between the polysilicon wiring layers 41 and 41 can be selectively removed, a pattern defect portion between the polysilicon wiring layers 34 and 41 can be easily removed.

The present invention has been described with reference to the embodiments.
The present invention is not limited to the above embodiment, and can be variously modified. For example, in the above embodiment, an example in which an insulating substrate (quartz substrate) is used as a substrate of a semiconductor device (thin film transistor) of the present invention and the present invention is applied to a liquid crystal display device has been described, but a semiconductor substrate may be used as a substrate. The present invention can be applied not only to the display device but also to other devices.

[0033]

As described above, according to the semiconductor device of the present invention, at least the region between the adjacent polysilicon wiring layers of the gate insulating film constituting the thin film transistor is selectively removed. Therefore, the pattern defect portion between the polysilicon wiring layers thereon is removed,
There is the effect that the short circuit accident between the polycrystalline silicon wiring layers is eliminated, the operation failure such as liquid crystal display is eliminated, and the quality is improved.

According to the method of manufacturing a semiconductor device of the present invention, after forming two or more polysilicon wiring layers, a region corresponding to the adjacent polysilicon wiring layers of the gate insulating film is selectively removed. Therefore, the pattern defect generated between the polycrystalline silicon wiring layers can be easily removed, and the production yield is improved.

In particular, when an opening pattern corresponding to a region between two or more adjacent polycrystalline silicon wiring layers is formed in the second resist film together with the gate insulating film pattern, the gate insulating film is formed. At the same time, the pattern defect generated between the polysilicon wiring layers can be removed, so that it is not necessary to newly add a manufacturing process.

[Brief description of the drawings]

FIG. 1 is a perspective view for explaining a basic principle of the present invention.

FIG. 2 is a plan view illustrating an example in which the present invention is applied to a liquid crystal display device.

FIG. 3 is a diagram for explaining a defect occurrence rate by comparing the present invention with a conventional method.

FIG. 4 is a circuit diagram illustrating a method for evaluating a thin film transistor according to the present invention.

FIG. 5 is a cross-sectional configuration diagram for explaining details of a thin film transistor shown in FIG. 2;

FIG. 6 is a plan view illustrating the details of the thin film transistor shown in FIG. 2;

FIG. 7 is a process chart for explaining a method of manufacturing the thin film transistor of FIG.

FIG. 8 is a cross-sectional view for explaining a step following the step shown in FIG. 7;

FIG. 9 is a cross-sectional view for explaining a step following the step shown in FIG. 8;

FIG. 10 is a cross-sectional view for explaining a step following the step shown in FIG. 9;

FIG. 11 is a cross-sectional view for explaining a step following the step shown in FIG. 10;

FIG. 12 is a cross-sectional view for explaining a step following the step shown in FIG. 11;

FIG. 13 is a perspective view for explaining a problem of a conventional thin film transistor.

FIG. 14 is a perspective view illustrating a problem of a conventional thin film transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Quartz substrate 12, 13, 34, 41 Polycrystalline silicon wiring layer 14a, 14b Insulating film opening 15 Pattern defect part 16 Polycrystalline silicon layer 17, 19 Contact hole 20 ITO film 15 Pattern defect part 16 Polycrystalline silicon layer 30 Thin film transistor 31 quartz substrate 32 polycrystalline silicon layer (first polysilicon layer) 32a, 32b n ⁺ region 32c, 32d n ^- region 33 a gate insulating film 34, 41 a polycrystalline silicon wiring layer 34A polycrystalline silicon layer (second Polycrystalline silicon layer) 35, 38 Interlayer insulating film 36, 39 Contact hole 37 Aluminum wiring layer 40 ITO film 41 Silicon nitride film

Claims (4)

(57) [Claims] 1. A semiconductor device having two or more polysilicon wiring layers constituting a thin film transistor at positions close to each other on a substrate, wherein the thin film transistor is a lower layer of the polysilicon wiring layer.
Source, drain and channel through the gate insulating film
At least the region between the two or more adjacent polysilicon wiring layers of the gate insulating film forming the thin film transistor is selectively removed, and the pattern defect generated between the polysilicon wiring layers is provided. A semiconductor device having a portion removed. 2. A method of manufacturing a semiconductor device having two or more polysilicon wiring layers constituting a thin film transistor at positions close to each other on a substrate, comprising: a source, a drain, and a channel region on the substrate; Forming a first polycrystalline silicon layer, and forming an insulating film to be a gate insulating film on the first polycrystalline silicon layer, and then forming two or more polycrystalline silicon wiring layers on the insulating film. Forming a second polycrystalline silicon layer comprising: forming a first resist film having a wiring pattern including a gate electrode on the second polycrystalline silicon layer;
Forming the two or more polysilicon wiring layers by selectively removing the second polysilicon layer using the first resist film as a mask; and removing the first polysilicon film after removing the first resist film. A second resist film having a gate insulating film pattern is formed on the wiring layer and the insulating film, and the gate insulating film is formed by selectively removing the insulating film using the second resist film as a mask. And forming a gate insulating film. The step of forming the gate insulating film is performed between the two or more adjacent polysilicon wiring layers by selectively removing a region of the insulating film between the two or more adjacent polysilicon wiring layers. comprising the step of removing the pattern defect, and thereafter, an interlayer insulating film on the polycrystalline silicon interconnect layer
Formed and connected to the source and drain
A method for manufacturing a semiconductor device, comprising performing a step of forming a contact hole . 3. An opening pattern corresponding to at least a region between two or more adjacent polysilicon wiring layers is formed in said second resist film together with a gate insulating film pattern. 3. The semiconductor according to claim 2, wherein a pattern defect portion generated between said polycrystalline silicon wiring layers is removed at the same time as forming a gate insulating film by selectively removing said insulating film using a film as a mask. Device manufacturing method. The wherein the opening pattern provided on the second resist film, wiring interval of the polycrystalline silicon wiring layers, characterized in that provided in a region smaller than the wiring width of each polycrystalline silicon wiring layer according Item 4. The method for manufacturing a semiconductor device according to Item 3.