JP3295178B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3295178B2 JP3295178B2 JP12351593A JP12351593A JP3295178B2 JP 3295178 B2 JP3295178 B2 JP 3295178B2 JP 12351593 A JP12351593 A JP 12351593A JP 12351593 A JP12351593 A JP 12351593A JP 3295178 B2 JP3295178 B2 JP 3295178B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- silicon nitride
- silicon
- oxynitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、キャパシタ誘電体膜や
ゲート絶縁膜に使用するＯＮＯ膜（酸化膜−窒化膜−酸
化膜）を有する半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an ONO film (oxide film-nitride film-oxide film) used for a capacitor dielectric film and a gate insulating film, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】ＯＮＯ膜を誘電体部分に使用するキャパ
シタは、"Oxidation Studies of Crystalline CVD Sili
con Nitride"（J.Electronchem.Soc.,Vol.136,No.5 ,19
89.5）に記載されている。2. Description of the Related Art A capacitor using an ONO film for a dielectric portion is disclosed in "Oxidation Studies of Crystalline CVD Silicon".
con Nitride "(J. Electronchem. Soc., Vol.136, No.5, 19
89.5).
【０００３】従来のＯＮＯ膜を誘電体部分に使用するキ
ャパシタは、図２に示すように、シリコン基板２１上に
下部電極用ポリシリコン２２を形成した後、自然酸化膜
２３、シリコン窒化膜２４を形成し、シリコン窒化膜２
４上部を熱酸化（ウエット酸化又はドライ酸化）するこ
とによって、シリコン窒化膜２４上にtop 酸化膜（オキ
シナイトライド（ＳｉＯx Ｎy ）膜２５、シリコン酸化
膜２６）を形成し、top 酸化膜形成後、top 酸化膜上に
上部電極用ポリシリコン２７を形成していた。In a conventional capacitor using an ONO film as a dielectric portion, as shown in FIG. 2, after forming a lower electrode polysilicon 22 on a silicon substrate 21, a natural oxide film 23 and a silicon nitride film 24 are formed. Formed and silicon nitride film 2
4 By thermally oxidizing (wet oxidation or dry oxidation) the upper portion, a top oxide film (oxynitride (SiO x N y ) film 25, silicon oxide film 26) is formed on the silicon nitride film 24, and the top oxide film is formed. After the formation, the upper electrode polysilicon 27 was formed on the top oxide film.
【０００４】[0004]
【発明が解決しようとする課題】従来のＯＮＯ膜（自然
酸化膜２３、シリコン窒化膜２４、top 酸化膜）におけ
るtop 酸化膜は、シリコン窒化膜２４上に形成されたオ
キシナイトライド膜２５とシリコン酸化膜２６との２層
構造からなる。このtop 酸化膜の上層部、シリコン酸化
膜２６は、top 酸化膜の下層部、オキシナイトライド膜
２５よりも比誘電率が低く、且つ結晶構造的にも粗いシ
リコン酸化膜を半導体の表層に含むため、絶縁性が劣
り、キャパシタ誘電体膜を有する半導体装置における容
量増加やリーク電流低減に限界が生じ、ゲート絶縁膜を
有する半導体装置におけるリーク電流低減に限界が生じ
るという問題があった。The top oxide film in the conventional ONO film (natural oxide film 23, silicon nitride film 24, top oxide film) is composed of an oxynitride film 25 formed on the silicon nitride film 24 and a silicon oxide film. It has a two-layer structure with an oxide film 26. The upper layer of the top oxide film, the silicon oxide film 26, has a lower dielectric constant than the lower layer of the top oxide film, the oxynitride film 25, and includes a silicon oxide film whose crystal structure is coarse in the surface layer of the semiconductor. Therefore, there is a problem in that the insulating property is poor, and the increase in capacitance and the reduction of leakage current in a semiconductor device having a capacitor dielectric film are limited, and the reduction in leakage current in a semiconductor device having a gate insulating film is limited.
【０００５】そこで、本発明は、キャパシタ誘電体膜と
してのＯＮＯ膜においては容量増加とリーク電流低減と
を両立させ、ゲート絶縁膜としてのＯＮＯ膜においては
リーク電流低減を図ることができる半導体装置及びその
製造方法を提供することを目的とする。Accordingly, the present invention provides a semiconductor device which can achieve both an increase in capacitance and a reduction in leakage current in an ONO film as a capacitor dielectric film and a reduction in leakage current in an ONO film as a gate insulating film. It is an object of the present invention to provide a manufacturing method thereof.
【０００６】[0006]
【課題を解決するための手段】本発明による半導体装置
は、半導体基板上に酸化膜とシリコン窒化膜とが形成さ
れた半導体装置において、前記シリコン窒化膜上に形成
されたオキシナイトライド膜と、このオキシナイトライ
ド膜上に直接接触して形成された導電膜とを有し、前記
酸化膜、前記シリコン窒化膜及び前記オキシナイトライ
ド膜からなるＯＮＯ膜がキャパシタ誘電体膜またはゲー
ト絶縁膜であるものである。According to the present invention, there is provided a semiconductor device in which an oxide film and a silicon nitride film are formed on a semiconductor substrate, wherein an oxynitride film formed on the silicon nitride film; A conductive film formed in direct contact with the oxynitride film, and the ONO film including the oxide film, the silicon nitride film, and the oxynitride film is a capacitor dielectric film or a gate insulating film. Things.
【０００７】また、本発明による半導体装置の製造方法
は、半導体基板上に酸化膜とシリコン窒化膜とを形成す
る工程と、前記シリコン窒化膜上部を酸化して該シリコ
ン窒化膜上にオキシナイトライド膜及びシリコン酸化膜
からなる上部膜を形成する工程と、前記上部膜厚の８／
１０〜９／１０をエッチング除去することにより、前記
シリコン酸化膜のみを除去する工程と、露出した前記オ
キシナイトライド膜上に直接接触するように導電膜を形
成する工程とを有するものである。In a method of manufacturing a semiconductor device according to the present invention, an oxide film and a silicon nitride film are formed on a semiconductor substrate, and an oxynitride is formed on the silicon nitride film by oxidizing an upper portion of the silicon nitride film. Forming an upper film comprising a film and a silicon oxide film;
The method includes a step of removing only the silicon oxide film by etching and removing 10 to 9/10, and a step of forming a conductive film so as to be in direct contact with the exposed oxynitride film.
【０００８】[0008]
【作用】本発明では、酸化膜とシリコン窒化膜とtop酸
化膜（上部膜：オキシナイトライド膜、シリコン酸化
膜）とからなるＯＮＯ膜のうち、top酸化膜上層にあた
るシリコン酸化膜は、オキシナイトライド膜よりも比誘
電率が低く、且つ絶縁性に劣るためtop酸化膜のシリコ
ン酸化膜をエッチングして取り除き、酸化膜とシリコン
窒化膜とオキシナイトライド膜のみのtop酸化膜とから
なるＯＮＯ膜にすることにより、絶縁性に優れたＯＮＯ
膜を得ることができる。従って、このＯＮＯ膜をキャパ
シタ誘電体膜を有する半導体装置に用いることにより、
容量増加とリーク電流低減との両立を図ることができ
る。又、このＯＮＯ膜をゲート絶縁膜を有する半導体装
置に用いれば、リーク電流低減を図ることができる。According to the present invention, of the ONO film composed of an oxide film, a silicon nitride film, and a top oxide film (upper film: oxynitride film, silicon oxide film), the silicon oxide film on the top oxide film is oxynitride. ONO film consisting of oxide film, silicon nitride film, and oxynitride film only top oxide film because silicon oxide film of top oxide film is removed by etching because it has lower relative dielectric constant and poorer insulation than nitride film ONO with excellent insulation properties
A membrane can be obtained. Therefore, by using this ONO film in a semiconductor device having a capacitor dielectric film,
It is possible to achieve both an increase in capacity and a reduction in leakage current. If this ONO film is used for a semiconductor device having a gate insulating film, leakage current can be reduced.
【０００９】[0009]
【実施例】以下、図１を用いて、本発明をキャパシタに
適用した場合の一実施例を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a capacitor will be described below with reference to FIG.
【００１０】まず、図１（ａ）に示すように、シリコン
基板１１上に、キャパシタの下部電極として、下部電極
用ポリシリコン１２をＣＶＤ法により厚さ例えば１００
〜３００ｎｍで成長させる。下部電極用ポリシリコン１
２成長後、下部電極用ポリシリコン１２上部には自然酸
化膜１３が厚さ約１〜２ｎｍで形成される。自然酸化膜
１３形成後、ＣＶＤ法によりシリコン窒化膜１４を成長
させる。このシリコン窒化膜１４の形成条件は、例え
ば、成長温度７００〜７５０℃、その厚さ１０〜２０ｎ
ｍを規定する。その後、シリコン窒化膜１４上部を熱酸
化することにより、top 酸化膜（オキシナイトライド膜
１５とシリコン酸化膜１６）を形成する。ここでのシリ
コン窒化膜１４の熱酸化条件は、例えばウエット酸化で
９００℃／３０分と規定する。First, as shown in FIG. 1A, a lower electrode polysilicon 12 is formed on a silicon substrate 11 as a lower electrode of a capacitor to a thickness of, for example, 100 by a CVD method.
Grow at ~ 300 nm. Polysilicon for lower electrode 1
After the second growth, a native oxide film 13 is formed on the lower electrode polysilicon 12 to a thickness of about 1 to 2 nm. After the formation of the natural oxide film 13, a silicon nitride film 14 is grown by a CVD method. The conditions for forming the silicon nitride film 14 are, for example, a growth temperature of 700 to 750 ° C. and a thickness of 10 to 20 n.
Define m. Thereafter, the top oxide film (oxynitride film 15 and silicon oxide film 16) is formed by thermally oxidizing the upper portion of silicon nitride film 14. Here, the thermal oxidation condition of the silicon nitride film 14 is defined as, for example, 900 ° C./30 minutes by wet oxidation.
【００１１】次に、図１（ｂ）に示すように、top 酸化
膜を形成後、top 酸化膜の上層にあたるシリコン酸化膜
１６部分をエッチングにより除去する。ここでのエッチ
ングの条件は、例えば、０．５％濃度のフッ化水素水溶
液で、２〜１０分と規定する。このエッチングは、シリ
コン窒化膜１４上部の熱酸化により形成されたtop 酸化
膜のうち、シリコン酸化膜１６部分のみをエッチングす
るものである。このシリコン酸化膜１６をエッチングす
る量は、top 酸化膜（オキシナイトライド膜、シリコン
酸化膜）厚の８／１０〜９／１０である。Next, as shown in FIG. 1B, after the top oxide film is formed, a portion of the silicon oxide film 16 above the top oxide film is removed by etching. The etching conditions here are defined as, for example, 2 to 10 minutes with a 0.5% aqueous solution of hydrogen fluoride. This etching is for etching only the silicon oxide film 16 of the top oxide film formed by thermal oxidation on the silicon nitride film 14. The etching amount of the silicon oxide film 16 is 8/10 to 9/10 of the thickness of the top oxide film (oxynitride film, silicon oxide film).
【００１２】次に、図１（ｃ）に示すように、シリコン
酸化膜１６をエッチングして取り除いた後に、オキシナ
イトライド膜１５上にキャパシタの上部電極として使用
する上部電極用ポリシリコン１７を形成することによ
り、キャパシタ構造を形成する。Next, as shown in FIG. 1C, after the silicon oxide film 16 is removed by etching, a polysilicon 17 for an upper electrode to be used as an upper electrode of a capacitor is formed on the oxynitride film 15. Thereby, a capacitor structure is formed.
【００１３】上記により、比誘電率が低く、絶縁性も劣
っているシリコン酸化膜１６を取り除くことができるの
で、比誘電率が高くなり絶縁性に優れたＯＮＯ膜を得る
ことができる。従って、キャパシタの容量が増加すると
共にリーク電流を低減することができる。なお、本実施
例ではキャパシタについて記述したが、このＯＮＯ膜を
ゲート絶縁膜に用いれば、絶縁性に優れるという該ＯＮ
Ｏ膜の特徴からゲート電極のリーク電流が減少する。As described above, since the silicon oxide film 16 having a low relative dielectric constant and poor insulation properties can be removed, an ONO film having a high relative dielectric constant and excellent insulation properties can be obtained. Therefore, the leakage current can be reduced while the capacitance of the capacitor increases. In this embodiment, a capacitor has been described. However, if this ONO film is used as a gate insulating film, the ON-type film having excellent insulation properties is obtained.
The leak current of the gate electrode is reduced due to the characteristics of the O film.
【００１４】[0014]
【発明の効果】本発明によれば、ＯＮＯ膜のtop 酸化膜
（オキシナイトライド膜，シリコン酸化膜）のシリコン
酸化膜は、オキシナイトライド膜よりも比誘電率が低
く、絶縁性も劣っているため、top 酸化膜のシリコン酸
化膜をエッチングして取り除くことにより、キャパシタ
誘電体膜としてＯＮＯ膜を有するＤＲＡＭ等の半導体装
置における容量増加とリーク電流低減とを図り、ゲート
絶縁膜としてＯＮＯ膜を有するＭＯＳトランジスタ等の
半導体装置におけるリーク電流低減を図ることができ
る。According to the present invention, the silicon oxide film of the top oxide film (oxynitride film, silicon oxide film) of the ONO film has a lower relative dielectric constant than the oxynitride film and has poor insulation properties. Therefore, by removing the silicon oxide film of the top oxide film by etching, it is possible to increase the capacity and reduce the leakage current in a semiconductor device such as a DRAM having an ONO film as a capacitor dielectric film, and to use the ONO film as a gate insulating film. Leakage current in a semiconductor device such as a MOS transistor can be reduced.
【図１】本発明をキャパシタに適用した場合の一実施例
を製造工程順に示す断面図である。FIG. 1 is a cross-sectional view showing an embodiment in which the present invention is applied to a capacitor in the order of manufacturing steps.
【図２】従来のＯＮＯ膜を使用したキャパシタの断面図
である。FIG. 2 is a cross-sectional view of a capacitor using a conventional ONO film.
１１ シリコン基板 １２ 下部電極用ポリシリコン １３ 自然酸化膜 １４ シリコン窒化膜 １５ オキシナイトライド膜 １６ シリコン酸化膜 １７ 上部電極用ポリシリコン Reference Signs List 11 silicon substrate 12 lower electrode polysilicon 13 natural oxide film 14 silicon nitride film 15 oxynitride film 16 silicon oxide film 17 upper electrode polysilicon
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０１Ｌ 29/78 (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/822 H01L 21/314 H01L 21/316 H01L 21/318 H01L 27/04 H01L 29/78 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 identification code FI H01L 29/78 (58) Investigated field (Int.Cl. 7 , DB name) H01L 21/822 H01L 21/314 H01L 21/316 H01L 21/318 H01L 27/04 H01L 29/78
Claims (3)
とを形成する工程と、 前記シリコン窒化膜上部を酸化して該シリコン窒化膜上
にオキシナイトライド膜及びシリコン酸化膜からなる上
部膜を形成する工程と、 前記上部膜厚の８／１０〜９／１０をエッチング除去す
ることにより、前記シリコン酸化膜のみを除去する工程
と、 露出した前記オキシナイトライド膜上に直接接触するよ
うに導電膜を形成する工程とを有することを特徴とする
半導体装置の製造方法。Forming an oxide film and a silicon nitride film on a semiconductor substrate; oxidizing an upper portion of the silicon nitride film to form an upper film comprising an oxynitride film and a silicon oxide film on the silicon nitride film; A step of forming, a step of removing only the silicon oxide film by etching away 8/10 to 9/10 of the upper film thickness, and a step of forming a conductive layer so as to directly contact the exposed oxynitride film. Forming a film.
る工程は、フッ化水素水溶液を用いてウエットエッチン
グする工程であることを特徴とする請求項１に記載の半
導体装置の製造方法。2. The method according to claim 1, wherein the step of etching and removing the silicon oxide film is a step of performing wet etching using a hydrogen fluoride aqueous solution.
記オキシナイトライド膜をゲート絶縁膜とする工程とを
更に有することを特徴とする請求項１に記載の半導体装
置の製造方法。3. The method according to claim 1, further comprising a step of using the oxide film, the silicon nitride film, and the oxynitride film as a gate insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12351593A JP3295178B2 (en) | 1993-04-27 | 1993-04-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12351593A JP3295178B2 (en) | 1993-04-27 | 1993-04-27 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06310654A JPH06310654A (en) | 1994-11-04 |
| JP3295178B2 true JP3295178B2 (en) | 2002-06-24 |
Family
ID=14862526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12351593A Expired - Lifetime JP3295178B2 (en) | 1993-04-27 | 1993-04-27 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3295178B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100282425B1 (en) * | 1997-10-10 | 2001-04-02 | 김영환 | Method for fabricating of capacitor |
| KR100459937B1 (en) * | 2002-06-11 | 2004-12-03 | 동부전자 주식회사 | Method for manufacturing semiconductor device with mim type capacitor |
| KR20040019512A (en) | 2002-08-28 | 2004-03-06 | 주식회사 하이닉스반도체 | Method for forming capacitor of semiconductor device |
| KR100665396B1 (en) | 2004-01-09 | 2007-01-04 | 에스티마이크로일렉트로닉스 엔.브이. | Manufacturing Method of Flash Memory Device |
| KR100833444B1 (en) | 2006-03-28 | 2008-05-29 | 주식회사 하이닉스반도체 | Manufacturing Method of Flash Memory Device |
| CN103606513B (en) * | 2013-11-08 | 2016-02-17 | 溧阳市江大技术转移中心有限公司 | A kind of manufacture method of semiconductor capacitor |
| CN103594354B (en) * | 2013-11-08 | 2016-07-06 | 溧阳市江大技术转移中心有限公司 | A kind of manufacture method of dielectric layer |
| CN105448886B (en) * | 2014-08-06 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | capacitor and preparation method |
-
1993
- 1993-04-27 JP JP12351593A patent/JP3295178B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06310654A (en) | 1994-11-04 |
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