JP3071268B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3071268B2 JP3071268B2 JP3275469A JP27546991A JP3071268B2 JP 3071268 B2 JP3071268 B2 JP 3071268B2 JP 3275469 A JP3275469 A JP 3275469A JP 27546991 A JP27546991 A JP 27546991A JP 3071268 B2 JP3071268 B2 JP 3071268B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- storage electrode
- forming
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 23
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 3
- 238000003860 storage Methods 0.000 description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000007774 longterm Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-IGMARMGPSA-N arsenic-75 atom Chemical compound [75As] RQNWIZPPADIBDY-IGMARMGPSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、メモリセルを有する
半導体装置のそのキャパシタ部のストレージ電極、特に
凹凸状の表面のシリコン膜による前記電極の形成方法に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a storage electrode in a capacitor portion of a semiconductor device having a memory cell, and more particularly to a method for forming the electrode using a silicon film having an uneven surface.
【０００２】[0002]
【従来の技術】図２に従来のスタック（積層）型メモリ
セルの製造方法を示し、以下に説明する。まず、シリコ
ン基板１の表面部にＬＯＣＯＳ法により厚いフィールド
酸化膜２を選択的に形成し素子分離を行なう。2. Description of the Related Art FIG. 2 shows a method of manufacturing a conventional stacked (stacked) memory cell, which will be described below. First, a thick field oxide film 2 is selectively formed on the surface of a silicon substrate 1 by a LOCOS method to perform element isolation.
【０００３】次に、ゲート絶縁膜となる薄い酸化膜３′
を形成し、さらに全面にゲート電極を形成するためのポ
リシリコン３を形成し、ＰｏＣｌ3 を拡散源としてリン
をドープして導電性を持たせる。次にゲートホトリソグ
ラフィ（以下ホトリソと略す）と異方性エッチングを行
いゲート電極３を形成する。Next, a thin oxide film 3 'serving as a gate insulating film is formed.
Is formed, and polysilicon 3 for forming a gate electrode is formed on the entire surface, and is doped with phosphorus using PoCl 3 as a diffusion source to have conductivity. Next, gate photolithography (hereinafter abbreviated as photolithography) and anisotropic etching are performed to form a gate electrode 3.
【０００４】次にこのゲート電極３をマスクとして、ヒ
素75Ａｓ+ をイオン注入することによりソース、ドレイ
ン４を形成することにより、図２（ａ）の如き構造を得
る。次に全面にＣＶＤ ＳｉＯ2 膜５を成長させ、ホト
リソと異方性エッチングを行いセルコンタクト５ａを形
成する。Next, using the gate electrode 3 as a mask, arsenic 75 As + is ion-implanted to form a source and a drain 4, thereby obtaining a structure as shown in FIG. 2A. Next, a CVD SiO 2 film 5 is grown on the entire surface, and photolithography and anisotropic etching are performed to form a cell contact 5a.
【０００５】次に、ストレージ電極形成のためのポリシ
リコン６を形成し、ＰｏＣｌ3 を拡散源としてリンをド
ープして導電性を持たせ、ホトリソ、エッチングを行い
ストレージ電極６を形成する。次にキャパシタ絶縁膜と
なる薄い熱酸化膜７を形成した後、セルプレート電極と
なるためのポリシリコン８を形成しＰｏＣｌ3 を拡散源
としてリンをドープして導電性を持たせホトリソ、エッ
チングを行ない、セルプレート電極８を形成することに
より図２（ｂ）の如き構造を得る。Next, polysilicon 6 for forming a storage electrode is formed, doped with phosphorus using PoCl 3 as a diffusion source to have conductivity, photolithography and etching are performed to form the storage electrode 6. Next, after a thin thermal oxide film 7 serving as a capacitor insulating film is formed, polysilicon 8 serving as a cell plate electrode is formed, and phosphorus is doped using PoCl 3 as a diffusion source to impart conductivity, and photolithography and etching are performed. Then, the structure as shown in FIG. 2B is obtained by forming the cell plate electrode 8.
【０００６】次に、全面にＢＰＳＧ(boron-phosphosili
cate glass) ９を成長させた後、９００℃程度の熱処理
を行ない、ホトリソ、エッチングを行なってコンタクト
を形成し、アルミ１０をスパッタ法により形成し、ホト
リソ、エッチングを行なうことにより図２（ｃ）の如き
構造となる。Next, BPSG (boron-phosphosili) is applied over the entire surface.
After growing the cate glass 9, a heat treatment is performed at about 900 ° C., photolithography and etching are performed to form contacts, aluminum 10 is formed by sputtering, photolithography and etching are performed, and FIG. The structure is as follows.
【０００７】しかしながら、高集積化、チップの縮小化
に伴ない、ストレージ電極６が縮小化することにより十
分なセル容量が得られなくなるため、ストレージ電極を
フィン型や円筒型にする等で、実効的なストレージ電極
の面積を増加させる方法が考えられている。その中で図
２（ｃ）のＤ部の拡大図である図２（ｄ）に示すよう
に、ストレージ電極６の表面を凹凸に形成する方法があ
り、この方法は、ポリシリコンを形成する時の形成条件
を変化させるだけで他の方法に比べて非常に容易に行え
て、６４Ｍb ＤＲＡＭ等に対しては、有望とされてい
る。However, with high integration and miniaturization of the chip, a sufficient cell capacity cannot be obtained due to the reduction in the size of the storage electrode 6. Therefore, the storage electrode 6 is made to be of a fin type or a cylindrical type, etc. A method of increasing the area of a typical storage electrode has been considered. As shown in FIG. 2D, which is an enlarged view of a portion D in FIG. 2C, there is a method of forming the surface of the storage electrode 6 with irregularities. This method is used when forming polysilicon. and only by changing the conditions for forming very easily performed compared to other methods, for 64M b DRAM or the like, and is promising.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、前述の
方法では、装置のＴＤＤＢ(Time dependent dielectric
breakdown)特性が劣化し、長期信頼性が保てないという
問題があった。この原因は、図２（ｄ）に示すような急
峻なエッジの凹部Ａのためである。いわば凹凸部の首の
部分（エッジ部）が極端に細く急角度になっているの
で、そこから劣化が促進される。However, in the above-mentioned method, the TDDB (Time Dependent Dielectric) of the device is not sufficient.
breakdown) characteristics are deteriorated, and long-term reliability cannot be maintained. This is due to the recess A having a steep edge as shown in FIG. In other words, the neck portion (edge portion) of the uneven portion is extremely thin and has a sharp angle, so that deterioration is promoted therefrom.
【０００９】この発明は、以上述べたＴＤＤＢ特性が劣
化し、長期信頼性が保てないという問題点を除去し、デ
バイス特性に優れた高歩留りの装置を提供することを目
的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a high-yield device excellent in device characteristics by eliminating the above-mentioned problems that the TDDB characteristics deteriorate and the long-term reliability cannot be maintained.
【００１０】[0010]
【課題を解決するための手段】この発明は前述の目的の
ため、半導体装置の表面に凹凸を有するストレージ電極
を形成後、以下の処理のいずれか或いは組合わせて行う
ようにしたものである。According to the present invention, for the above-mentioned object, after forming a storage electrode having irregularities on the surface of a semiconductor device, any one or a combination of the following processes is performed.
【００１１】（１）その表面を酸化して、その酸化膜を
除去する。(1) The surface is oxidized to remove the oxide film.
【００１２】（２）その表面に薄くポリシリコンを堆積
する。(2) Polysilicon is deposited thinly on the surface.
【００１３】（３）その表面に絶縁膜を形成後、異方性
エッチングにより凹部以外の絶縁膜を除去する。(3) After forming an insulating film on the surface, the insulating film other than the concave portions is removed by anisotropic etching.
【００１４】[0014]
【作用】本発明は前述のような処理を施すようにしたの
でストレージ電極の急峻なエッジ部分がなめらかにな
り、ＴＤＤＢ特性が改善でき、長期信頼性の向上が期待
できる。According to the present invention, since the above-described processing is performed, the steep edge portion of the storage electrode becomes smooth, the TDDB characteristic can be improved, and the long-term reliability can be expected.
【００１５】[0015]
【実施例】図１に本発明の実施例を示し、以下に説明す
る。FIG. 1 shows an embodiment of the present invention, which will be described below.
【００１６】図１（ａ）は従来技術同様の方法で凹凸状
のストレージ電極６まで形成した図である。即ち、シリ
コン基板１に、フィールド酸化膜２、ゲート絶縁膜
３′、ゲート電極３を形成し、ソース、ドレイン４を拡
散形成し、ＳｉＯ2 ５を堆積してセルコンタクト５ａを
開口した後、ストレージ電極６を形成した図である。FIG. 1A is a view showing the formation of the uneven storage electrode 6 by the same method as in the prior art. That is, the silicon substrate 1, field oxide film 2, the gate insulating film 3 ', the gate electrode 3 is formed, a source, a drain 4 diffuses formed, and after opening the cell contacts 5a by depositing SiO 2 5, storage FIG. 3 is a view showing an electrode 6 formed.
【００１７】この凹凸状のストレージ電極６の形成は、
周知のことであるが、ＬＰＣＶＤ（Low Pressure Chemi
cal Vapour Deposition)法により、シラン（ＳｉＨ4 ）
ガスを用いて、アモルファス状態からポリシリコンに変
わる遷移温度、例えば５７０℃でシリコン膜６を１００
０Å程度形成する。そうすると図１（ａ）に示すように
表面が凹凸状のシリコン膜（ストレージ電極）６が得ら
れる。The formation of the uneven storage electrode 6 is as follows.
It is well known that LPCVD (Low Pressure Chemi
cal vapor deposition) method, silane (SiH 4 )
Using a gas, the silicon film 6 is heated to 100 ° C. at a transition temperature at which the amorphous state is changed to polysilicon, for example, 570 ° C.
It is formed about 0 °. Then, as shown in FIG. 1A, a silicon film (storage electrode) 6 having an uneven surface is obtained.
【００１８】本実施例は、この後、図１（ｂ）（ｃ）
（ｄ）に示し、以下に述べるような処理を行なうように
したものである。前記各図は図１（ａ）のストレージ電
極６の一部（Ａ）を拡大したものである。以下文中「表
面」とはこのストレージ電極６の表面のことである。In the present embodiment, after that, FIGS.
The processing shown in (d) and described below is performed. Each of the above figures is an enlarged view of a part (A) of the storage electrode 6 in FIG. In the following description, “surface” means the surface of the storage electrode 6.
【００１９】第１の方法は、図１（ｂ）に示すように、
その表面を９５０〜１０５０℃の高温で、Ｏ2 （酸素）
とＮ2 （窒素）との比が０．１以下の希釈率で２００〜
３００Åの厚さ酸化する。このとき、酸化温度はできる
だけ高い方がよいが、高いと酸化速度が速くなるので酸
化膜厚制御のため希釈を行なう。次いで、その酸化膜を
ＨＦ（フッ化水素）で除去すると凹部（特にエッジ部）
がなめらかになる。The first method is as shown in FIG.
The surface is heated at a high temperature of 950 to 1050 ° C. with O 2 (oxygen).
And the ratio of N 2 (nitrogen) is 200-
Oxidize 300mm thick. At this time, the oxidation temperature is preferably as high as possible. However, if the oxidation temperature is high, the oxidation rate is increased. Next, when the oxide film is removed with HF (hydrogen fluoride), the concave portion (particularly, the edge portion) is formed.
Becomes smoother.
【００２０】その後、不純物を拡散し導電性を持たす。
この後は、従来同様キャパシタ絶縁膜、セルプレート電
極、中間絶縁膜、配線などを形成する。Thereafter, impurities are diffused to have conductivity.
Thereafter, a capacitor insulating film, a cell plate electrode, an intermediate insulating film, wiring, and the like are formed as in the conventional case.
【００２１】第２の方法は、図１（ｃ）に示すように、
その表面に、６００〜６３０℃の温度でＬＰＣＶＤ法に
よりポリシリコン膜６′を１００〜２００Å堆積する。
そうすると図に示すように凹部がなめらかになる。The second method is as shown in FIG.
On the surface thereof, a polysilicon film 6 'is deposited at a temperature of 600 to 630 DEG C. by LPCVD at a temperature of 100 to 200 DEG.
Then, the concave portion becomes smooth as shown in the figure.
【００２２】その後、不純物を拡散し導電性を持たす。
この後は第１の方法で述べたように従来同様キャパシタ
絶縁膜以降の形成を行なう。Thereafter, impurities are diffused to have conductivity.
Thereafter, as described in the first method, the formation after the capacitor insulating film is performed as in the conventional method.
【００２３】第３の方法は、図１（ｄ）に示すように、
その表面に先ず不純物を拡散して導電性を持たせる。そ
の後、キャパシタ絶縁膜となる膜と同じＳｉＯ2 （二酸
化シリコン）膜７を１００〜２００Å形成し、異方性エ
ッチングにより凹部（エッジ部）に前記絶縁膜７を残
し、他の部分の前記絶縁膜は除去する。The third method is as shown in FIG.
First, impurities are diffused on the surface to give conductivity. Thereafter, the same SiO 2 (silicon dioxide) film 7 as the film to be the capacitor insulating film is formed at 100 to 200 °, and the insulating film 7 is left in the concave portion (edge portion) by anisotropic etching. Is removed.
【００２４】次に、キャパシタ絶縁膜となるＳｉＯ2 あ
るいはＳｉ3 Ｎ4 を改めて５０〜６０Å形成する。この
後は従来同様セルプレート電極以降の形成を行なう。Next, anew 50~60Å form SiO 2 or Si 3 N 4 serving as a capacitor insulating film. Thereafter, the formation after the cell plate electrode is performed as in the conventional case.
【００２５】以上の各方法は、それぞれ単独で行っても
よいが、組み合わせて行なえばさらに凹部をなめらかに
する効果は大きくなる。Each of the above methods may be performed independently, but when combined, the effect of further smoothing the concave portion is increased.
【００２６】図３に、従来例と本実施例の各方法により
形成した装置のＴＤＤＢ特性を示しておく。図は印加電
界に対する寿命を酸化膜換算膜厚５３Åで表示したもの
であり、本実施例としては前記第１の方法（図１
（ｂ））と第２の方法（図１（ｃ））とを組み合わせた
ものと、第１の方法（図１（ｂ））のみの場合を示し
た。FIG. 3 shows the TDDB characteristics of the devices formed by the methods of the prior art and this embodiment. In the figure, the life with respect to the applied electric field is represented by an oxide film equivalent film thickness of 53 °. In this embodiment, the first method (FIG.
(B)) and the combination of the second method (FIG. 1 (c)) and the case of only the first method (FIG. 1 (b)).
【００２７】この図から解るように、本実施例の寿命つ
まりＴＤＤＢ特性は従来の凹凸状ストレージ電極のそれ
より２桁以上改善されている。As can be seen from this figure, the life of this embodiment, that is, the TDDB characteristic is improved by two orders of magnitude or more than that of the conventional uneven storage electrode.
【００２８】なお、前述した本実施例の第１、第２の方
法は、凸部のエッジをなめらかにすることにも有効であ
る。The above-described first and second methods of the present embodiment are also effective for smoothing the edges of the convex portions.
【００２９】[0029]
【発明の効果】以上述べたように本発明によれば、凹凸
状ストレージ電極の表面を酸化膜あるいはポリシリコン
膜で処理して、凹部の急峻なエッジ部分をなめらかにす
るようにしたので、装置としてのＴＤＤＢ特性が改善で
き長期信頼性の向上が図れる。As described above, according to the present invention, the surface of the uneven storage electrode is treated with an oxide film or a polysilicon film so that the steep edge portion of the concave portion is smoothed. TDDB characteristics can be improved, and long-term reliability can be improved.
【図１】本発明の実施例FIG. 1 shows an embodiment of the present invention.
【図２】従来例FIG. 2 Conventional example
【図３】ＴＤＤＢ特性比較図FIG. 3 is a TDDB characteristic comparison diagram
６ ストレージ電極 ６′ ポリシリコン膜 ７ 絶縁膜 6 storage electrode 6 'polysilicon film 7 insulating film
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０１Ｌ 27/04 (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/108 H01L 21/28 H01L 21/316 H01L 21/822 H01L 21/8242 H01L 27/04 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 identification code FI H01L 27/04 (58) Investigated field (Int.Cl. 7 , DB name) H01L 27/108 H01L 21/28 H01L 21/316 H01L 21/822 H01L 21/8242 H01L 27/04
Claims (1)
リコン膜を形成する工程と、 前記凹凸を有するシリコン膜の表面に第１の絶縁膜を形
成する工程と、 前記第１の絶縁膜に対して異方性エッチングを施すこと
により、前記シリコン膜の凹部に前記第１の絶縁膜を残
した状態で、前記シリコン膜上の第１の絶縁膜を除去す
る工程と、 残存する前記第１の絶縁膜および前記シリコン膜上に第
２の絶縁膜を形成する工程と、 を含むことを特徴とする半導体装置の製造方法。A step of forming a silicon film having an uneven surface on a semiconductor substrate; a step of forming a first insulating film on the surface of the silicon film having the uneven surface; Removing the first insulating film on the silicon film while performing the anisotropic etching on the silicon film while leaving the first insulating film in the concave portion of the silicon film; Forming a second insulating film on the insulating film and the silicon film. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3275469A JP3071268B2 (en) | 1991-10-23 | 1991-10-23 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3275469A JP3071268B2 (en) | 1991-10-23 | 1991-10-23 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05114712A JPH05114712A (en) | 1993-05-07 |
| JP3071268B2 true JP3071268B2 (en) | 2000-07-31 |
Family
ID=17555977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3275469A Expired - Fee Related JP3071268B2 (en) | 1991-10-23 | 1991-10-23 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3071268B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11233735A (en) * | 1998-02-16 | 1999-08-27 | Nec Corp | Lower electrode structure, capacitor using the same, and method of forming the same |
| JP4024940B2 (en) | 1998-09-04 | 2007-12-19 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
| KR100400326B1 (en) * | 2001-12-29 | 2003-10-01 | 주식회사 하이닉스반도체 | Forming method of lower electrode of semiconductor device |
-
1991
- 1991-10-23 JP JP3275469A patent/JP3071268B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05114712A (en) | 1993-05-07 |
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