JP3281502B2 - Display control device, information processing device, and control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device, an information processing device, and a control method.

[0002]

2. Description of the Related Art In general, an information processing system (or apparatus) uses a display device as a means for realizing a visual expression function of information.

Generally, the number of display dots of a display device in an information processing apparatus such as a personal computer is 640 × 40.
The size was from 0 to 640 × 480 dots, and most of the display colors were at most 16 colors.

However, in recent years, with the development of an OS (operating system) and hardware, a display-only board or card is mounted on an existing information processing apparatus, so that not only the number of display dots but also the number of colors are increased. It has become possible to increase. It is a so-called graphic accelerator board (card) (hereinafter referred to as a display control board).

[0005] Recently, in order to replace the conventional CRT device, a liquid crystal display (L) is used due to its space-saving feature.
CD) is attracting attention.

However, a liquid crystal display generally has a smaller number of colors than a CRT, and it is necessary to perform some processing on image data and display the result.

For example, the applicant has already proposed a display (hereinafter, referred to as FLCD) using a liquid crystal cell of ferroelectric liquid crystal (Ferroelectric Liquid Crystal), which is one of the LCDs. One of the features of the FLCD is that the liquid crystal cell has a preservability of a display state with respect to application of an electric field. That is, the FLCD has a sufficiently thin liquid crystal cell, and the elongated FLC elements therein maintain their respective alignment states even when an electric field is removed. Due to the bistability of such an FLC element, an FLCD utilizing it has a property of storing display contents. Details of such FLC and FLCD are described in, for example, Japanese Patent Application No. Sho 62
-76357.

The number of colors of this FLCD is 16 at present. However, by performing a binarization process such as an error diffusion process, it is possible to increase the apparent number of colors by several stages.

[0009]

Considering a graphic accelerator board for outputting a liquid crystal display such as an FLCD, a circuit for converting at least data to be displayed on the liquid crystal display is provided in the board. Is required.

[0010] Whether or not such a circuit operates properly can be determined by connecting an FLCD (of which the operation has been confirmed to be normal) to the board, displaying a sample image, and viewing it with the human eye. To determine if there is a defective part. This is a great burden on the inspector.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is intended to transfer image data after conversion corresponding to a display to a higher-level device for supplying image data. An object of the present invention is to provide a display control device, an information processing device, and a control method that can easily confirm that a circuit related to conversion is correctly operating.

In order to solve this problem, for example, a display control device of the present invention has the following configuration. That is, a display control device that performs display control of a display, a first storage unit that stores image data that is a source of a display image supplied from a higher-level device, and stores data in a display format of the display. A second storage unit for converting image data stored in the first storage unit into a data format corresponding to the display, and outputting the converted data to the second storage unit; Output means for outputting at least a part of the data transferred from the second storage means to the display unit to the higher-level device in accordance with a predetermined instruction from.

Here, according to a preferred embodiment of the present invention, it is desirable that the display has a memory retention of display contents, and it is particularly preferable that the display is a ferroelectric liquid crystal display.

Thus, the image transferred from the second storage means to the display can be at an arbitrary position, and the displayed image during the transfer does not become unnatural.

Preferably, the instruction from the higher-level device includes a line address of an image to be transferred to the display and a position address based on a transfer unit. This makes it possible to obtain image data at a desired position.

Further, it is preferable that the host device is a general-purpose information processing device, and the display control device is connected to an expansion bus provided in the general-purpose information processing device. Thus, the display control device is not limited to a dedicated information processing device, but can be used for a general information processing device.

[0017]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

<Configuration of Information Processing System> In the figure, reference numeral 101 denotes a CPU for controlling the entire information processing system;
102a is a bus (for example, a PCI bus) that enables high-speed transfer including an address bus, a control bus, and a data bus, and 102b is a medium-speed bus that performs data transfer, although not as fast as the bus 102a. A system ROM 103 stores a boot program, a BIOS, and the like.
Reference numeral 104 denotes a main memory which is constituted by a RAM and in which an OS and various applications are loaded. 105
a and 105b are bridges that perform arbitration between different buses. Reference numeral 106 denotes a video capture controller, which is a circuit for capturing an image output from the video camera 107 or the like into the apparatus.

Reference numeral 108 denotes a display controller which is a main part in the embodiment, and converts the image into an image to be displayed on the FLCD 109 (the details of the display controller 108 and the FLCD 109 will be described later).

Reference numeral 110 denotes an audio subsystem.
A signal from a sound source from a microphone or the like is sampled and converted into digital data, or the digital data is converted into an analog signal and output from a speaker or the like.

Reference numeral 111 denotes a real-time clock which is composed of a crystal oscillator or the like and also has a function of measuring time. Reference numeral 112 denotes a key board controller which receives a key input signal from a keyboard or an input signal from a pointing device and notifies the CPU 101 of the signal.

Reference numeral 113 denotes an I / O controller, which includes a floppy disk drive (FDD), a hard disk drive (HDD), a serial interface and a parallel interface as shown in FIG. ing. Where H
The DD stores the OS (operating system) and various applications of the system of the embodiment.

In the above configuration, a display RAM (VRAM) is provided inside the display controller 108.
And a circuit group for performing processing for displaying the image stored in the VRAM on the FLCD 109. The display controller 108 may be fixedly connected to the system, or a card (or board) may be provided in a portion called an expansion slot provided in an information processing apparatus typified by a workstation or a personal computer. It may be connected as. That is, the FLCD 109 and the display controller 108 of the embodiment may be incorporated in the system in any form, or may be connected to the outside as an independent device. When the FLCD 109 is separate from the information processing apparatus, the FLCD 109 is connected to the display controller 109 via a cable.

In any case, in the present system, an OS or an application is loaded into the main memory 104 via the I / O controller 113 and executed. The screen information during execution is displayed on the display controller 10.
8 is stored in the VRAM provided in the FLCD 1
09 is displayed. Any operating OS or application may be used. For example, MS-WINDOWS of Microsoft Corporation in the United States is available.
Applications that run on it.

As described above, when the present system is a personal computer or the like and the display controller 108 is connected to its general-purpose slot,
It is necessary to write an image to the VRAM in the controller 108, but this processing is performed by the FRAM stored in the HDD or the like.
This is performed by activating a device driver (a type of software) dedicated to the LCD.

<Explanation of Flow of Image Data> FIG. 2 shows the concept of the flow of data related to image display in the system of the above embodiment.

When the application or the OS writes data in the VRAM in the display controller 108, it performs a binary halftone process (error diffusion (ED) process in the embodiment) and writes it into the FLCD 109.
The data is written in a frame memory (4 bits for each pixel = R, G, B, I) having the capacity of the screen. The contents of the frame memory are transferred to the FLCD 109 and displayed. That is, in a general display device, the contents of the VRAM are directly transferred to the display device. On the other hand, the display controller 108 in the embodiment has a frame memory interposed between the VRAM and the FLCD 109 as a display. It is to let.

<Display Controller and FLCD
Description> FIG. 3 shows a specific block configuration of the display controller 108 in the embodiment.

In the figure, reference numeral 300 denotes a CPU provided in the display controller 108 and for controlling the entire controller. The CPU 300 has a ROM
It operates according to the program stored in 308.

Reference numeral 301 denotes a VRAM in which one byte (8 bits) is assigned to each pixel of R, G, and B (3 bytes = 24 bits = about 16.7 million colors). Generally, when 8 bits are given to each of the RGB color components, a color image reproduced by that is called a full color image. In the embodiment, 1280
It has a capacity capable of storing an image of × 1024 dot size (1280 × 1024 × 3 ≒ 4 Mbytes).

Reference numeral 302 denotes an SVGA for controlling access to the VRAM 301, which can perform drawing (writing) and reading on the VRAM 301 based on a command from the CPU 101 on the information processing system side. It also has a function of drawing a figure or the like based on a command from the CPU 101, and also has a function described later. An LSI for drawing various figures on a VRAM is widely used as a display control chip, and is itself known.

Reference numeral 303 denotes a write detection / flag generation circuit. When the SVGA chip 302 performs writing (drawing processing) on the VRAM 301, its write enable signal (actually including a chip select signal) is used as a trigger to change the write address. Detect and calculate what line has been updated and hold it.

The circuit 303 will be described in more detail.
Utilizes the write enable signal when the SVGA chip 302 writes data in the VRAM 301, and latches the address output at that time in a register (not shown). Then, from the latched address data, the number of the line on which the writing was performed is calculated (calculated by a circuit that divides the write address by the number of bytes of one line), and the area flag corresponding to the rewritten line is calculated. Is set to "1". FLCD 10 in the embodiment
9, the number of lines of the entire screen is 1024 (0th line to 10th line).
Since each area has 32 lines as one unit, the area flag is 32 (= 1024/3) in total.
2) Bits. That is, each bit in the 32-bit flag holds whether or not there has been a write to each area of the 0th to 31st lines, the 32nd to 63rd lines, ..., 992 to 1023.

The fact that a certain number of lines is used as a unit instead of holding whether or not rewriting has been performed for each line is generally the case when a display image is changed. Because it straddles. Note that the number of lines allocated to one area is not limited to 32, and may be other than this. However, if the number is too small, the number of bits of the area flag increases. In addition, the number of times of the instruction of the partial rewriting process to be described later is increased by that amount, and the rate of occurrence of overhead is increased. In addition, if the number of lines to be allocated is too large, there is also a problem that the possibility that unnecessary portions of the partial rewriting process increase is increased. For this reason, 32 lines were used.

The FLCD 109 will be described later.
Is 1280 × 1024, but in order to be able to display even other numbers of dots (for example, 10
24 × 768, 640 × 480, etc.), and the information amount of one line used for calculating the rewrite line is programmable. The change in the number of display dots is based on an instruction from the CPU 102 of the information processing apparatus (the program running at that time is the control driver of the display controller in this embodiment).

When the rewrite detection / flag generation circuit 303 described above detects that data has been rewritten in the area of 32 lines written in the VRAM 301,
The contents of the area flag are notified to the CPU 300. As will be described later, the area flag is also cleared to zero in response to a request from the CPU 300.

Reference numeral 304 denotes a line address generation circuit which receives a head address of a line specified by the CPU 300 and the number of offset lines from that line, and
An address for data transfer and its control signal are output to the VGA chip. The SVGA chip 302
Upon receiving the address data and the signal, the image data (8 bits / pixel for each of RGB) of the number of lines designated from the corresponding line is output to the binary halftone processing circuit 305 described below.

The binarized halftone processing circuit 305 is an SVGA
The image data (8 bits each for RGB per pixel) transferred from the chip 302 is converted into RGB data based on the error diffusion method.
And a luminance signal I (4 bits in each 1 bit). The present applicant has already proposed a technique of binarizing RGB into 1 bit from each 8 bits of RGB and generating a binary signal I indicating the level of luminance (for example,
Japanese Patent Application No. 4-126148). Further, the binarized halftone processing circuit 305 has a built-in buffer memory required for error diffusion processing in order to perform the processing.

The binarized halftone processing circuit 305
Receives an error diffusion table (parameter) serving as a parameter for binarization, a line position to be output, and the number of lines based on an instruction from the CPU 300, and outputs it in accordance with it. The error diffusion table is not fixed.
The reason why the setting can be dynamically set from the PU 300 is, for example, to enable the color scheme or the like to be changed based on an instruction from the CPU 101 of the information processing apparatus.

Reference numeral 306 denotes a frame memory for storing an image to be displayed on the FLCD 109 (1 bit of RGBI data per pixel). As described above, the FLCD 109 in the embodiment is 1280 × 1024 dots, and each dot is 4 bits, and thus has a capacity of 1 Mbyte (640 Kbytes in calculation).

Reference numeral 307 denotes a frame memory control unit which controls writing and reading of the frame memory and transfer to the FLCD 109. Although details will be described later, the RGBI data output from the binarization halftone processing circuit 305 is stored in the frame memory 306, and the CPU 30
A process for outputting the area designated by 0 to the FLCD 109 is performed (once one line is stored in the FIFO memory 307a and then transferred). Unless the image data of a certain number of lines is transferred to the FLCD 109 (that is, when the transfer of the image data instructed by the CPU 300 is completed and there is no next transfer instruction), the FLCD 109 is not processed. Receives a request for the transfer of the last one line from the CPU 3
00 is notified as an interrupt signal. The data format for transferring data to the FLCD is a set of a total of 4 bits of RGBI, and the frame memory 306 stores data in this format.

Further, the frame memory control circuit 30
7 also outputs an interrupt signal to the CPU 300 to that effect even when the image data from the binarized halftone processing circuit 305 has been completely stored in the frame memory. And again, CP
When the transfer of the image data of the line instructed from U300 is completed (if the transfer of a plurality of lines is instructed, and the transfer of the image data of the instructed number of lines is completed), an interrupt signal to that effect is also issued. Output to CPU300.

In the above-described configuration, when the CPU 101 of the information processing apparatus receives a drawing request of a character or a figure from the OS or an application, a command or image data corresponding to the request is sent to the CPU 10.
1 is output to the SVGA chip 302 in the display controller 108. When receiving the image data, the SVGA chip 302 stores the image in the VRAM3.
When the drawing command such as graphic data is received at the designated position of 01, the graphic image is drawn at the corresponding position in the VRAM 301. That is, SVGA
The chip 302 performs a writing process on the VRAM 301.

The rewrite detection / flag generation circuit 303 monitors the writing of the SVGA chip 302 as described above. As a result, the flag for the area where the writing is performed is set, and the flag is set to the CPU 300.
Inform

The CPU 300 reads the area flag stored in the rewrite detection / flag generation circuit 303, resets the area flag to the rewrite detection / flag generation circuit 303, and prepares for the next rewrite. Note that this reset operation may be performed by hardware means so as to be performed simultaneously with the reading.

Now, the CPU 300 determines which bit is set from the read area flag, that is,
It is determined which area (there may be a plurality) in which rewriting has been performed. Then, the area determined to have been rewritten is converted from the VRAM 301 into a binary halftone processing circuit 305.
To the line address generation circuit 304, the start address of the transfer start line (usually, the address at the left corner of the screen) and data indicating the number of lines to be transferred from that position are output to the line address generation circuit 304.

The point to be noted here is that when it is detected that writing has been performed in, for example, the tenth area of the VRAM 301, that is, the area of the 320th to 351st lines, the line address generation circuit supplies the first pixel of the 320th line to the line address generation circuit. Is transferred from the first pixel address of the line (line 315) five lines before the 320th line, instead of instructing the transfer of 32 lines from that address. That is, a transfer instruction is performed for the 315th to 351st lines. The reason is as follows.

In general, when an error diffusion process is performed, a two-dimensional matrix having weighting element values (values indicating distribution ratios) is used to diffuse generated errors into unprocessed pixel groups. The generated error propagates one after another. Here, assuming two pixels A and B, the influence of an error generated when the binarization processing is performed at the position of the pixel A on the position of the pixel B (unprocessed pixel) will be considered. In this case, the influence of the error generated in the A pixel on the B pixel becomes smaller as the distance between the AB pixels is larger. In other words, if there is a certain distance, the influence of the error from the A pixel on the B pixel position is so small as to be negligible. The above five lines are based on such a reason. Note that the distance at which the influence of the error can be ignored is determined depending on the size of the error diffusion matrix and the weighting element value. In addition, 2 in the embodiment
It can be understood from the above description that the error diffusion processing in the binarization processing circuit 305 is performed from the upper left corner to the lower right corner of the image.

The CPU 300 gives an instruction to the binarized halftone processing circuit 305 indicating which part of the line data resulting from the binarized halftone processing is to be output.

That is, as described above, the VRAM 3
When data is written in the area of the 320th line to the 351st line of No. 01, the data of the 315th to 351st lines is transferred to the binarized halftone processing circuit 305.
300 instructs the binarized halftone processing circuit 305 to output data of the lines 320 to 351.

As a result, the binary halftone processing circuit 305
After that, the data of the 320 to 351 lines affected by the image of the unchanged portion before the 319th line is output to the frame memory control unit 307.

The frame control memory circuit 307 includes a CPU
300, a binary halftone processing circuit 3
The line-by-line data (4 bits per pixel) output from 05 is written to the corresponding frame memory 306. That is, since the CPU 300 knows the number of lines output from the binarized halftone processing circuit and the number of the first line in the image, the CPU 300 inputs the line to the frame memory control circuit 307. The address of the line (the write start address for the frame memory 306) and the data indicating how many lines of data are to be continuously written are set.

In this way, an image of only the rewritten (updated image) portion, and an image having a natural junction with the unrewritten image, are written in the frame memory 306. Note that the frame memory control circuit 307 determines whether or not the area designated by the CPU 300
When the storage of the data transferred from the binarized halftone processing circuit 305 in the frame memory 306 is completed, the above-described interrupt signal is generated.

The processing speed of the binary halftone processing circuit 305 in the embodiment is about 1/30 second at present for one screen. This is about a half of the vertical synchronization signal of a CRT or the like at about 60 Hz. However, rewriting the entire screen is rare as long as a normal application is used. In other words, 2
The number of lines processed by the binarized halftone processing circuit 305 is not so large in fact, and inevitably the processing amount is small.
If it does not change much compared to the display update period, or is less than half the area, it is rather faster than the CRT.

Further, the frame memory control circuit 307
An output instruction to FLCD 109 is also received from CPU 300. The output instruction indicates which line (the head address of the line) and how many lines (the number of continuous lines) are to be transferred to the FLCD 109. Frame memory control circuit 307
Receives this instruction, reads the image data line by line from the frame memory into the FIFO memory 306a, and transfers it to the FLCD 109. When a series of transfer is completed in this manner, an interrupt signal for notifying the CPU 300 is generated. This is as described above.

Here, the frame memory control unit 307
The data format to be transferred to the LCD 109 is as shown in FIG. As shown in the figure, the data transfer in the embodiment is in units of 16 bits per word, a write line address is added at the beginning, and then image data of 4 pixels (data of 4 pixels continuous in the horizontal direction) is added. Transfer.

The FLCD 109 receives such data and uses the data immediately following it for driving the FLCD 109 in accordance with the head address.

Note that writing from the binarized halftone processing circuit 305 may output the processing results of a plurality of discontinuous areas, and the transfer instruction to the FLCD 109 to the frame memory control circuit 307 may be Since the completion of the transfer to the FLCD has been received, the image data written in the frame memory 306 is immediately stored in the FLCD.
The image data is not necessarily output to the image data 109. That is, as described above, by processing through the frame memory 306, writing to the VRAM 301 and FLC
The output to D109 will be processed completely asynchronously.

FIG. 4 shows a block diagram of the FLCD 109 in the embodiment. In the drawing, 400 is an FLCD
A controller 401 controls overall control, and 401 is an FLC
It is. Reference numeral 402 denotes the FLC 401 in the row direction (line).
403 is a register having a storage capacity for one line.

The controller 400 receives the format data shown in FIG. 6 from the display controller 108, checks the leading write address, and supplies the data of the pixel data RGBIRGBI... Then, the row direction selection circuit 40 selects the line indicated by the write address.
2 to update the FLC display. Further, the controller 400 generates a data transfer request signal to the display controller 108 at time intervals (variable in the range of 60 to 70 sec) depending on the temperature obtained from a temperature sensor (not shown).

When the CPU 300 instructs, for example, a transfer request for 32 lines, the frame memory control circuit 307 outputs the data in a line unit in accordance with the above-described format each time the data transfer request is received. Thus, the transfer of all the designated lines has been completed, and the next transfer request instruction has not been received.
When a data transfer request signal is received from the CD 109, the fact is notified to the CPU 300 as an interrupt signal.

Upon receiving this notification, the CPU 300 determines whether there is untransferred data of the partially rewritten image, and if not, the image data of the entire screen stored in the frame memory 306 is interlaced by the FLCD 109.
To instruct transfer. That is, every time the interrupt signal is received, the first line, the third line,..., The 1023 line, the second line,.
An instruction is given to the frame memory control unit 307 in order to transfer the data line by line. Incidentally, in practice, the FLCD 10
When the transfer request signal from 9 comes, the line to be transferred when the next transfer request signal comes is specified.

As described above, when there is no change in the image, the reason for performing the interlace transfer is as follows.

As described above, the FLCD 109 used in the embodiment has a function of storing and holding a display image, so that it is theoretically necessary to transfer only the changed portion. However, a slight difference may occur in the luminance at the boundary between an image that is not refreshed without any change and an image that has been changed and is newly driven and displayed (partially rewritten). is there.

That is, the FLCD 109 in the embodiment
When the display image is partially updated, the display of the FLCD is updated only with the updated portion, but when there is no change to the display image, the frame memory 30 is updated.
A process of transferring all the images in 6 to the FLCD 109 in an interlaced manner is performed. Instead of transferring each line sequentially,
The reason for interlaced transfer is to speed up the update of the apparent display image because the response of the liquid crystal display is generally not fast.

<Method of Checking Display Controller> In the display controller 108 in the above embodiment, the final image data transferred to the FLCD 109 is stored not in the VRAM 301 but in the frame memory 306.

In this embodiment, if it is checked that the FLCD 109 operates normally, it is not necessary to connect the FLCD 109 (or to check whether the operation of the display controller 108 is normal). Without auditing the display screen).

FIG. 5 shows a block configuration of the frame memory control circuit 306 of the embodiment for realizing this. It should be noted that FIG. 7 shows only a part related to this check, and does not show other parts. However, that part can be fully understood from the contents described above.

In FIG. 5, reference numeral 501 denotes a line address generating circuit, which is the head address information of the data to be transferred to the FLCD (information indicating which line of the FLCD 109 is the data, and the information of the head word in FIG. 6).
Is to occur. When the line address specified by the CPU 300 is set and the number of transfer lines is plural, the line address generation circuit 501 updates the address to the address of the next line every time one line is transferred.

Reference numeral 502 denotes a FIFO memory capable of storing image data (RGBI) data for one address information + 1 line. In the embodiment, one line has 1280 pixels and the transfer bus has 16 bits (= 1 word).
1280 x 4 (bits) = 640 bytes, FIF
O memory 502 has a total of 32 words of 320 words + 1 additional words.
It has a memory capacity of one word.

Reference numeral 504 denotes a latch circuit, and reference numeral 505 denotes a CP.
This register stores the address specified by U300. A counter 506 is a FIFO memory 502.
When the image data for one address + 1 line is transferred from the device to the FLCD 109 (a period in which a transfer enable signal (not shown) is active), a transfer clock (not shown) in the section is timed, and the address held in the register 505 is read. If they match, clock 2 is applied to latch 504.
The latch signal is output successively.

In the above configuration, the CPU 300 now has
If an arbitrary address of the transfer data is stored in the register 505 and the frame memory control circuit 307 is caused to transfer a desired line, as a result,
The latch 504 can hold data at an arbitrary address of the line (arbitrary address position in one line) and the next data. More specifically, it is possible to extract any two words (data of eight pixels) in the specified transfer data.

Therefore, the CPU 300 reads the data stored in the latch 504 at this time, thereby
It is possible to check the data to be transferred to the LCD 109. Of course, it is also possible to extract the contents of the write line address by setting the register 505 to “0”.

Now, the check processing of the display controller of the embodiment in the above configuration will be described with reference to the flowcharts of FIGS. The program according to the flowchart of FIG.
101 is executed and stored in the HDD or the like. A program corresponding to the flowchart of FIG.
This is stored in M308 and executed by the CPU 300.

First, the operation will be described with reference to the flowchart of FIG.

In step S1, sample image data or data for drawing the sample image is stored in HD.
D or the like, and the data is transferred or drawn to the display controller 108 (more precisely, the VRAM 301) of the present embodiment. In general, a graphic cursor linked to a pointing device is not displayed. The reason is that the cursor is displayed during the check period, and if it moves, the VRAM 30
This is because writing 1 is performed, and the conversion result exceeds the prediction.

When the process proceeds to step S2, it is determined whether the check has been completed. If it is determined that the reading has not been completed, the process proceeds to step S3, and the CPU 300 in the display controller 108 is instructed to read out what line number and what word address.

When the process proceeds to step S4, the converted data (in this embodiment, 2 words = 8 pixels data) of the previously designated position is received from the display controller 108 (CPU 300) and stored in the HDD or the like in advance. The stored sample image is compared with normal converted image data.

As a result of the comparison, if it is found that the data is correct, the process returns to step S2 to give the next instruction.

On the other hand, if it is determined that there is an inconsistency, the process proceeds to step S5, in which the inconsistent data and its location are stored in the main memory 104 (or HDD or the like), and then to step S2. Return.

When the check for one screen is completed, the process proceeds to step S6, in which the main memory 104
If there is no check result data, a message indicating that the data is normal, if any, a message indicating which position of the data is abnormal is displayed. In addition to the message display, a predetermined LED may be lit or blinked, or a buzzer may be used to notify the user.

Next, the operation procedure of the CPU 300 in the display controller 108 will be described with reference to the flowchart of FIG. It should be noted that this flowchart is for the CPU 10
1 shows an interrupt routine when an instruction is received from the CPU 1.

First, in step S11, the CPU 1
In step S12, the fetched word address in the line address indicated by the instruction data is taken into the frame memory control circuit 30.
7 is set in the register 505. Then, the designated line address is set, and the image data of the line is transferred to the FLCD 109 (step S13).

When the transfer is completed, the frame memory control unit 307 issues an interrupt signal to the CPU 300, so that it can be detected (step S14).

When the process proceeds to step S15, the data held in the latch of the frame memory control circuit 307 is read out, and in step S16, the C on the information processing system side is read.
Output it to PU.

As described above, according to the present embodiment,
It can be diagnosed whether the processing in the display controller 108 is performed normally. And FL
Since there is no need to perform inspection while looking at the screen of the CD 109, the inspection work becomes very easy.

Although the above inspection process has been described mainly on the assumption of the manufacturing stage, it may be performed in an environment actually used by a user. In this case, the processing may be performed at an initial stage when the power of the information processing apparatus is turned on, or may be performed when the user appropriately gives the instruction.

<Description of Second Embodiment> In the above embodiment,
This is to check whether or not the processing inside the display controller 109 operates normally. However, it is impossible to know whether or not the transfer between the FIFO memory 307 and the FLCD 109 is actually performed correctly. In fact, there is an interface cable between them, and
Each of the display controller 108 and the FLCD 109 is provided with a dedicated interface, line driver, and line receiver. Therefore, the soldering of the boards, the pattern of the boards, the filter for reducing the radiation noise, the mounting of the connector, and the like are not to be checked.

Therefore, in the second embodiment, an example in which this is also checked will be described.

FIG. 9 shows an FLCD 1 according to the second embodiment.
FIG. 9 is a block diagram showing the configuration of a system 09. 4 is different from FIG. 4 in that the serial interface 404 is provided with a FIFO that acts as a buffer for synchronizing the system and the system.

This serial interface 404 is
For example, a general-purpose interface such as RS232C. The reason for using the general-purpose interface is generally that F
This is because a device to which the LCD is connected (a personal computer, a workstation, or the like) is equipped with an interface such as RS232C as standard.

FIG. 10 shows an information processing system (apparatus),
9 illustrates a connection relationship between an FLCD 109 and a display controller in a second embodiment. As shown, F
A serial cable from the LCD 109 is connected to a serial interface (RS232C) on the information processing system side.

In the configuration shown in the figure, the CPU 101 of the information processing system sends a command for performing a test to the FLCD 109 via a serial port provided in its own device, and transmits a sample image to the display controller. The data is written in the VRAM 301 in the memory 108. The display controller 108 outputs line data to the FLCD 109 as a normal operation, or specifies a line address to be transferred to the CPU 300 in the display controller 108.

Controller 400 on FLCD 109
Output the data received from the display controller 108 to the information processing system via the serial interface 404 in order from the top. The CPU of the information processing system issues a transfer instruction and then receives the data (write line address + 1) received via the serial port.
Line data) and checks the consistency. The transfer order may be the case of interlace. In this case, since the line data is sent with the line address, the information processing system can assemble the display data according to the address.

During the check period, the FLCD 109 may or may not display the check image.

In the first embodiment, the amount of information to be checked is 2 words, that is, in units of 8 pixels. In the second embodiment, the entire transferred data is returned at one time. . The reason is that the serial communication generally has a lower transfer speed than that of the first embodiment, and if a request is made in units of 1 byte to be transferred, the overhead portion increases. . However, this does not apply to the case where the check processing is performed via an interface that does not have a problem in speed. For example, when the display controller 108 and the FLCD 109 are connected by an interface capable of two-way communication,
Thus, it is unnecessary to provide a separate interface on the FLCD.

In the above embodiment, when the CPU 300 receives a transfer instruction by partial rewriting from the CPU 300, the frame memory control circuit 307 transmits the partial rewriting image during transfer.
Although the interrupt signal due to the data transfer request signal from the FLCD 109 is not output to the CPU 300, the interrupt signal may be output irrespective of the operating state.

In this case, since the CPU 300 knows the number of lines to be transferred when a partial rewrite instruction is issued, every time an interrupt signal is received, the CPU 300 counts down and checks the value. This is because it can be determined whether the interrupt is an interrupt due to transfer completion or an interrupt during interlace transfer.

The processing procedure of the CPU 101 or the CPU 300 in the above embodiment is an example, and the present invention is not limited to this. In short, as described above, when transferring the partially rewritten image to the FLCD,
This is because it is only necessary to perform the processing asynchronously with the frame memory 306 interposed.

Note that the display controller 108 or the FLCD 109 in the embodiment may be configured to be integrated with the information processing apparatus from the beginning, or may be mounted in an expansion slot provided as a standard in a device represented by a personal computer.

The CPU 300 in the display controller 108 performs the processing according to the program stored in the ROM 308. However, instead of the ROM 308, for example, a RAM or a rewritable EE that can be stored and held.
It may be a PROM.

In the case of using a RAM, when the information processing apparatus is turned on, the CPU 300 in the display controller 108 corresponds to the initial stage of driver software for driving the present FLCD interface. Just download the program. still,
The advantage of using RAM or EEPROM is that C
This is to make it easy to change the processing program of the PU 300 and to make it easy to debug the program.

Therefore, the information processing device or the FLCD interface device in the present embodiment may be a single device or a combination of a plurality of devices, and is applicable to a case where a program is supplied from outside. It is.

Therefore, the present invention is not limited to the above embodiment, and can be applied to any case as long as the gist of the present invention is not changed.

In the embodiments, the FLCD, that is, the ferroelectric liquid crystal display has been described as an example. The display colors are described as being 16 colors, but the present invention is not limited thereto. The point is that the image data stored in the VRAM can be subjected to some processing and applied to a device that receives and displays the processed data.

[0106]

As described above, according to the present invention, the conversion-related circuit operates correctly by transferring the converted image data corresponding to the display to the host device that supplies the image data. Can be easily confirmed.

[0107]

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing system according to an embodiment.

FIG. 2 is a diagram illustrating a concept of a data flow relating to image display in the system according to the embodiment.

FIG. 3 is a diagram showing a specific block configuration of a display controller in the embodiment.

FIG. 4 is a block diagram of an FLCD in an embodiment.

FIG. 5 is a partial block configuration diagram of a frame memory control circuit in the embodiment.

FIG. 6 is a diagram showing a format of data transferred to an FLCD in the embodiment.

FIG. 7 is a flowchart illustrating the contents of a check process that operates on the information processing system side in the embodiment.

FIG. 8 is a flowchart illustrating an operation processing procedure of the CPU in the display controller at the time of the check processing in the embodiment.

FIG. 9 is a block diagram of an FLCD according to a second embodiment.

FIG. 10 shows an information processing system and F in the second embodiment.
FIG. 3 is a schematic diagram illustrating a connection relationship between an LCD and a display controller.

[Explanation of symbols]

 300 CPU 306 Frame memory 307 Frame memory control circuit 501 Line address generation circuit 502 FIFO memory 503 Synthesizer 504 Latch 506 Counter 505 Register

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-5-323930 (JP, A) JP-A-5-323904 (JP, A) JP-A-5-11723 (JP, A) JP-A-5-323930 160455 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/133 560 G02F 1/13 101 G09G 3/20 G09G 3/36 G09G 5/00

Claims (15)

(57) [Claims] 1. A display control device for controlling display of a display, comprising: first storage means for storing image data which is a source of a display image supplied from a host device ; A second storage unit that stores data, a conversion unit that converts image data stored in the first storage unit into a data format corresponding to the display, and outputs the data format to the second storage unit. wherein in accordance with a predetermined instruction from the host device, a display control device at least part of the data transferred to the display unit from the second storage means and an outputting means for outputting to the host device. 2. The apparatus according to claim 1, wherein the instruction from the host device includes a line address of an image to be transferred to the display and a position address based on a transfer unit.
A display control device according to the item. 3. The display control device according to claim 1, wherein the display is a ferroelectric liquid crystal display. 4. A display unit for displaying data; a first storage unit for storing image data which is a source of a display image supplied from a higher-level circuit; Conversion means for converting the data stored in the first storage means into a data format corresponding to the display means, and outputting the converted data to the second storage means; An information processing apparatus comprising: a return unit configured to return at least a part of data transferred from the second storage unit to the display unit to the upper circuit in accordance with an instruction. 5. The instruction from the upper circuit includes a line address of an image to be transferred to the display means and a position address based on a transfer unit.
The information processing device according to item. 6. The information processing apparatus according to claim 4, wherein the display unit has a storage property of display contents. 7. The information processing apparatus according to claim 6, wherein said display means is a ferroelectric liquid crystal display. 8. The apparatus according to claim 4, wherein said first and second storage means, said conversion means, and said return means are connected as a card to a bus of a higher-level circuit. Information processing device. 9. A first storage means for storing image data serving as a source of a display image supplied from a higher-level circuit; a second storage means for storing data in a display format of a display; A control method for an information processing apparatus having a display circuit comprising: a conversion unit that converts image data stored in a storage unit into a data format corresponding to the display, and outputs the converted data to the second storage unit. According to a predetermined instruction from the higher-level circuit, at least a part of the data transferred from the second storage unit to the display is returned to the higher-level device, and the returned data is inspected. A method for controlling an information processing device. 10. The information according to claim 9, wherein a sample image is recorded in the first storage unit, and the returned data is compared with predetermined data to perform an inspection. A method for controlling a processing device. 11. The instruction from the upper circuit includes a line address of an image to be transferred to the display and a position address based on a transfer unit.
Or a method for controlling an information processing apparatus according to item 10. 12. The control method for an information processing apparatus according to claim 9, wherein the display is a ferroelectric liquid crystal display. 13. A supply unit for supplying image data which is a source of a display image, a first storage unit for storing the image data which is a source of the supplied display image, and a display format data of a display device. A second storage unit that stores the image data, a conversion unit that converts the image data stored in the first storage unit into a data format corresponding to the display device, and outputs the data format to the second storage unit. Transfer means for transferring data stored in the storage means to the display device; extracting means for extracting at least a part of data from the data transferred by the transfer means; and inspecting the data extracted by the extracting means. An information processing apparatus comprising: 14. The information processing apparatus according to claim 13, wherein the display has a storage property of display contents. 15. The information processing apparatus according to claim 14, wherein the display is a ferroelectric liquid crystal display.