JP3271307B2 - Test pattern generator for semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern generator for inspecting a semiconductor memory circuit or a memory circuit in a semiconductor device and easily analyzing the inspection result.

[0002]

2. Description of the Related Art The configuration of a test pattern generator for a semiconductor memory according to the prior art will be described with reference to FIG. 2 is a program control unit, 2 is an address pattern generation unit,
Reference numeral 3 denotes a data pattern generator, 4 denotes an X inversion storage circuit, 5 denotes a Y inversion storage circuit, 6 denotes a logical operation circuit, and 7 denotes an inversion circuit.

A program control unit 1 stores a microprogram describing a test pattern, decodes the microprogram at the time of execution, issues an instruction D to an address pattern generation unit 2, and sends an instruction E to a data pattern generation unit 3. At the same time, status signals from the address pattern generator 2 and the data pattern generator 3 are obtained to control the progress of the microprogram.

The address pattern generator 2 generates an X address pattern A and a Y address pattern B in accordance with an instruction D of the program controller 1. The data pattern generator 3 generates a data pattern C according to an instruction E of the program controller 1.

The X inversion storage circuit 4 writes inversion information beforehand at a position corresponding to the X address of the memory under test to be inverted, and is accessed by the X address pattern A of the address pattern generation unit 2 to execute the data inversion. Data inversion information F corresponding to the X address of the memory under test to be inverted is output. In the Y inversion storage circuit 5, before execution, the inversion information is written in advance at a position corresponding to the Y address of the memory under test to be inverted, is accessed by the Y address pattern B of the address pattern generator 2, and the data should be inverted. The data inversion information G corresponding to the Y address of the memory under test is output.

The logical operation circuit 6 includes data inversion information F of the X inversion storage circuit 4 and data inversion information G of the Y inversion storage circuit 5.
And the logic selected by the logic selection signal K (eg, fixed at “0”, fixed at “1”, X, Y, X or Y,
X nor Y, X and Y, X and Y, X
eor Y, Xenor Y, etc.) to output data inversion information H to the inversion circuit 7.

The inversion circuit 7 inverts or non-inverts the data pattern C of the data pattern generation unit 3 with the data inversion information H from the logical operation circuit 6 to generate a data pattern J.
Is output. X address pattern A, Y address pattern B, and data pattern J are the X address of the memory under test,
It is supplied as Y address and data.

FIGS. 3A to 3E show write data in an arbitrary area of a test memory cell matrix such as a malfunction of an address circuit and a decoder circuit of a memory under test and an influence of interference between memory cells in the memory cell matrix. An example in which a test pattern that intentionally inverts a pattern is written in a memory under test is shown, and hatched portions in the drawing indicate that write data is inverted with respect to others. The test pattern of FIG. 3 is generated by a pattern generator as shown in FIG. The configuration shown in FIG. 2 is also described in Japanese Patent Publication No. 60-18948.

Next, the operation of FIG. 2 will be described with reference to FIG.
Before starting a test, a microprogram in which a test pattern is described in advance in the program control unit 1 and data in the memory under test 10 are inverted in the storage circuit 41 of the X-inversion storage circuit 4 and the storage circuit 51 of the Y-inversion storage circuit 5. The inversion information is written to the bit position corresponding to the area. 1
1 is one of the write data patterns. During operation, an arbitrary test pattern is generated by an instruction from the program control unit 1 by the address pattern generation unit 2 and the data pattern generation unit 3. However, the data pattern generator 3
, A pattern program is created without considering the data inversion area.

[0010] For example, in FIG.
Creates a pattern program that always outputs "0". The memory under test 10 is accessed by the X address pattern and the Y address pattern of the address pattern generation unit 2, and at the same time, the storage circuit 41
51 is accessed. As a result, the inverted data Dou corresponding to the address accessed from the storage circuits 41 and 51
tx and Duty are output.

The logic of the inverted data Doutx and Douty is obtained by the logical operation circuit 6 (X in the example of FIG. 4).
The logic of eor Y is assumed), and the inversion circuit 7 inverts or non-inverts the data pattern of the data pattern generation unit 3 based on the result. That is, when the contents of the storage circuits 41 and 51 are as shown in FIG. 4, the inversion information “1” is written in the data inversion area of the memory under test 10.

[0012]

With the increase in the capacity of the semiconductor memory, when testing the operation failure of the address circuit and the decoder circuit of the memory under test and the influence of interference between the memory cells of the memory cell matrix, etc. Inspection of all the memory cells with various test patterns increases the inspection time.

Most of the memory cell matrix of the semiconductor memory is composed of a plurality of identical plates (groups of memory cells), and the inspection time is reduced by supplying and inspecting various test patterns in plate units. be able to. In a logical operation system such as a conventional test pattern generator, data can be inverted only by one kind of logic. Although the logic of the logical operation circuit can be changed and the data can be inverted, the interruption time of the test is entered and the test efficiency is reduced. Further, it is difficult to switch the logic of the logic operation circuit in real time during the inspection.

According to the present invention, the logic of the logical operation circuit is switched in real time and the data can be inverted in a desired memory cell matrix area in order to efficiently analyze the influence of interference between memory cells of the memory under test. An object of the present invention is to provide a test pattern generator for a semiconductor memory.

[0015]

In order to achieve this object, according to the present invention, there is provided a program control unit for storing a microprogram in which a test pattern is described, and for decoding the microprogram and transmitting an instruction signal at the time of execution. When,
X address pattern A according to the instruction of program control unit 1
And an address pattern generator 2 for generating a Y address pattern B, a data pattern generator 3 for generating a data pattern in accordance with an instruction from the program controller 1, and an X address pattern A of the address pattern generator 2 to be accessed in advance. An X inversion storage circuit 4 for outputting inversion information written at a position corresponding to a position where the data of the test memory is to be inverted, and a Y address pattern B of the address pattern generator 2 are accessed to invert the data of the memory under test in advance. A Y-inversion storage circuit 5 that outputs the inversion information written at a position corresponding to a position to be written, an input of the X-inversion storage circuit 4 and an output of the Y-inversion storage circuit 5 are input, and a logical operation selected by a logic selection signal is performed. Logical operation circuit 6
An inverting circuit 7 for inverting or non-inverting the data pattern of the data pattern generating unit 3 by the output of the logical operation circuit 6; and an address selecting circuit 8 for selecting an address for area division from the address pattern of the address pattern generating unit 2. And a logic selection storage circuit 9 that is accessed by the address pattern selected by the address selection circuit 8 and outputs the previously written logic selection information to the logic operation circuit 6 as a logic selection signal.

[0016]

Next, the configuration of a test pattern generator for a semiconductor memory according to the present invention will be described with reference to FIG. In FIG. 1, reference numeral 8 denotes an address selection circuit, reference numeral 9 denotes a logic selection storage circuit, and the other components are the same as those in FIG. That is, FIG. 1 is obtained by adding an address selection circuit 8 and a logic selection storage circuit 9 to FIG.

The address selection circuit 8 selects an address for area division from the X address pattern A and the Y address pattern B generated from the address pattern generation section 2,
Output the address pattern L. Logic selection storage circuit 9
Is a logic selection signal for accessing the logic selection information written in advance before execution by the address pattern L selected by the address selection circuit 8 and selecting the logic of the logic operation circuit 6 in an arbitrary area of the memory cell matrix of the memory under test. Output K.

The logic operation circuit 6 receives the data inversion information F from the X inversion storage circuit 4 and the data inversion information G from the Y inversion storage circuit 5, and is selected by the logic selection signal K from the logic selection storage circuit 9. Logic (for example, fixed to "0",
"1" fixed, X, Y, X or Y, X nor Y, X
and Y, X and Y, X eor Y, X
(enor Y, etc.) to output data inversion information H to the inversion circuit 7. The inversion circuit 7 converts the data pattern C of the data pattern generation unit 3 into a logical operation circuit 6
Invert or non-invert based on the data inversion information H from, and outputs a data pattern J.

Next, the operation of FIG. 1 will be described with reference to FIGS. Before starting the test, a microprogram describing a test pattern in the program control unit 1 in advance, and X
The storage circuit 41 of the inverted storage circuit 4 and the storage circuit 51 of the Y inverted storage circuit 5 store the inverted information “1” in the bit position corresponding to the data inverted area of the memory under test 10 in consideration of the logic of the logical operation circuit 6. Write.

At the same time, the selection circuit 81 of the address selection circuit 8
First, an address bit for dividing the memory under test 10 into regions 13 is selected, the region is divided into 13 in the storage circuit 91 of the logic selection storage circuit 9, the logic of the logical operation circuit 6 is selected for each region, and the type of logic for inverting data is selected. Write the logical selection information for selecting No. 14. Note that reference numeral 11 denotes one of the write data patterns.

In operation, an arbitrary test pattern is generated by an instruction from the program control unit 1 by the address pattern generation unit 2 and the data pattern generation unit 3. However,
For the data pattern generation unit 3, a pattern program is created without considering the data inversion area. For example, in the examples of FIGS. 5 to 7, the data pattern generation unit 3 is always “0”.
Create a pattern program that outputs

The X address pattern and the Y address pattern generated by the address pattern generating section 2 access the memory under test 10 and at the same time, the decoders 42 and 5 respectively.
2, the storage circuits 41 and 51 are accessed. Also,
At the same time, the memory circuit 91 is accessed via the decoder 92 in accordance with the address pattern selected by the selection circuit 81 of the address selection circuit 8 (in the example of FIG. 5, X3, X4, and Y3 are selected).

As a result, the inverted data Doutx, corresponding to the address accessed by the storage circuits 41 and 51,
Duty is output. In addition, the storage circuit 91
The logic selection data Dout alu mode corresponding to the accessed address is output. These inverted data Doutx and Douty are captured by the logic operation circuit 6 by logic selection data Dout alu mode (fixed to “0”, Y, X
eor Y, X, "1" fixed, X, Y, Xenor
Assume that the logic of Y is taken. ) Based on the result, the inversion circuit 7 inverts or non-inverts the data pattern of the data pattern generation unit 3. That is, the storage circuit 4
1. The contents of 1.51 are divided into regions by the contents of the selection circuit 81,
The logic is selected for each area based on the contents of the storage circuit 91, and in the case shown in FIG. 7, "1" can be written in the data inversion area of the memory under test 10.

[0024]

According to the present invention, it is possible to select the logic of the logic operation circuit in an arbitrary area when testing the influence of interference between the memory cells of the memory cell matrix of the memory under test. Registering in advance the address bits for dividing the area in plate units (groups of memory cells) in the address selection circuit and the logic selection information for selecting the logic of the logical operation circuit in plate units in the logic selection storage circuit, various types of plate units can be used. Test pattern data can be provided. Instead of supplying the same test pattern to all the plates as in the related art, various test patterns can be supplied to each plate, and the efficiency of inspection processing can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a test pattern generator for a semiconductor memory according to the present invention.

FIG. 2 is a configuration diagram of a conventional semiconductor memory test pattern generator.

FIG. 3 is an example of a test pattern for intentionally inverting a write data pattern.

FIG. 4 is an operation explanatory view of FIG. 2;

FIG. 5 is an operation explanatory view of FIG. 1;

FIG. 6 is an operation explanatory view of FIG. 1;

FIG. 7 is an operation explanatory view of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Program control part 2 Address pattern generation part 3 Data pattern generation part 4 X inversion storage circuit 5 Y inversion storage circuit 6 Logical operation circuit 7 Inversion circuit 8 Address selection circuit 9 Logical selection storage circuit

Claims (1)

(57) [Claims] 1. A program control unit (1) for storing a microprogram describing a test pattern, decoding the microprogram at the time of execution and sending a command signal, and an X address pattern by a command of the program control unit (1). A and Y: an address pattern generator (2) for generating an address pattern B; a data pattern generator (3) for generating a data pattern in accordance with an instruction from a program controller (1); and an X for the address pattern generator (2). An X inversion storage circuit (4) which is accessed by the address pattern A and outputs inversion information previously written at a position corresponding to the position where the data of the memory under test is to be inverted; and a Y address pattern of the address pattern generator (2). B, and writes the inversion information previously written at the position corresponding to the position where the data of the memory under test should be inverted. A Y-inversion storage circuit (5) to output, a logic operation circuit (6) which receives the outputs of the X-inversion storage circuit (4) and the Y-inversion storage circuit (5) and performs a logic operation selected by a logic selection signal; An inverting circuit (7) for inverting or non-inverting the data pattern of the data pattern generator (3) by the output of the logical operation circuit (6); and an address for dividing the area from the address pattern of the address pattern generator (2). Address selection circuit (8)
And a logic selection storage circuit (9) accessed by the address pattern selected by the address selection circuit (8) and outputting the previously written logic selection information as a logic selection signal to the logic operation circuit (6). Characteristic test pattern generator for semiconductor memory.