JP2877505B2 - LSI mounting board and data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI mounting board on which an LSI element of an address scan system is mounted, and a data processing apparatus provided with at least one of the LSI mounting boards.

"Prior art" In LSI devices, internal flip-flops, latch circuits, registers, and other storage elements can be addressed, data can be written to the storage elements, and data from the storage elements can be read and tested. LSI
There is an element, and this LSI element is called an address scan type LSI element.

This address scan type LSI element will be briefly described with reference to FIG. The LSI element 11 is a logic element that performs various processes as a whole by combining a storage element section 12 including a plurality of storage elements such as flip-flops and latch circuits, and a storage element in the storage element section 12 with various logic elements. It consists of a combinational circuit 13 for configuring the circuit, inputs a clear signal as necessary, inputs a clock, inputs data as a system input, processes the data and outputs it as a system output, and LS
It is configured to exhibit the function as an I element.

Furthermore, in order to test this LSI element 11, this LSI element
An X decoder 14 and a Y decoder 15 are provided in the storage element 11 so that the storage elements in the storage element section 12 can be individually addressed and selected, and a scan address is sent to the X decoder 14 and the Y decoder 15 through a scan address terminal 16. When a scan enable signal is applied to the scan enable terminal 17 and one of the storage elements is selected according to the input scan address, and when data “1” is input to the scan set terminal 18, the selected storage element is When data “1” is written to the memory element and data “1” is input to the scan reset terminal 19, data “0” is written to the selected memory element and the selected memory element is supplied with the scan enable signal. The data can be read and output to the scan read terminal 21.

By configuring the LSI element in this manner, automatic generation of a failure detection test pattern for the LSI element is facilitated, and the test of the LSI element is also facilitated.

[Problems to be Solved by the Invention] Conventionally, after mounting a scan address type LSI element on a board or further configuring a data processing device (system) using the LSI mounting board, the LSI mounting board Scan address terminal 16, scan enable terminal 17, scan set terminal 1
8, scan reset terminal 19 and scan read terminal 21 (these are referred to as scan terminals) were not used at all. In other words, the function that uses the scan address method is
It was used only for the element itself, and was not used at all after mounting.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an LSI mounting board and a data processing device that can effectively use the functions of the scan address system even after mounting the scan address system LSI elements.

[Means for Solving the Problems] According to the invention of claim 1, an address scan LS
On an LSI mounting board on which an I element is mounted, a scan address decoder circuit, a scan address line commonly connected to a scan address terminal of each LSI element, a scan write data circuit, and a scan read circuit are mounted. The address decoder circuit can be operated by the board scan enable signal, the board scan address can be decoded, one of the LSI elements can be selected and the test can be performed, and the scan write data circuit is controlled by the write enable signal. Scan data is commonly supplied to the scan data write terminal of the LSI element, that is, the scan set terminal or the scan reset terminal,
The scan read circuit outputs the logical sum of the data from the scan read terminal of each LSI element.

According to the second aspect of the present invention, at least one of the LSI mounting boards used in the data processing device is the mounting board according to the first aspect of the present invention, wherein the data processing device has a scan board register and a scan address register. And scan data register means are provided, the scan board register can select one of the LSI mounting boards and supply a board scan enable signal, and the scan address register is provided to the scan address decoder circuit of each LSI mounting board. The scan address is given to the scan address line while the scan address is given to the scan address line, and the scan data register means can supply the scan data to the scan write data circuit of each LSI mounting board and input the output of the scan read circuit.

According to the third aspect of the present invention, at least one LSI mounting board of the data processing device includes an address scan type LSI.
The LSI mounting board further includes a scan address decoder circuit, a scan address line commonly connected to a scan address terminal of each LSI element, and a scan readout circuit. Becomes operable when a board scan enable signal is applied, and can decode one of the board scan addresses to select one of the LSI elements.The scan read circuit calculates the logical sum of the data from the scan read terminal of each LSI element. Output. Also, the data processing device includes a scan board register for selecting one of the LSI mounting boards and providing a board scan enable signal,
A scan address register is provided for giving a board scan address to a scan address decoder circuit of each LSI mounting board and for giving a scan address to a scan address line.

[Embodiment] Fig. 1 shows an embodiment of the first aspect of the present invention. The LSI mounting board 22 has the scan address method shown in FIG.
Implements the LSI device 11 ₁ to 11 _n, these LSI devices 11 ₁ to 11 _n, in order to perform the original data processing, although not shown in the figure, the system between the LSI elements 11 ₁ to 11 _n The input terminal and the system output terminal are connected, or these system input terminal and system output terminal are connected to a board terminal for external connection of the board 22. Here, only the parts related to the present invention are shown.

In the present invention, the scan address decoder circuit 23 is mounted on the board 22. The scan address decoder circuit 23 is operable by a board scan enable signal from the board terminal 24, operable and became state of decoded LSI element 11 ₁ to 11 _n boards scan address from the board terminal 25 one Scan enable terminal 1
7 is supplied with a scan enable signal, and the LSI element can be tested.

A scan data writing circuit 26 is mounted on the board 22. Scan data is input from the board terminal 28 to the buffer 27 in the scan data writing circuit 26, and the buffer 27
Outputs data of the same polarity as the input and data of the opposite polarity, and these are supplied to gates 29 and 31, respectively,
The gates 29 and 31 are both supplied with a write enable signal from the board terminal 32. The output of gate 29 is LSI device 11 ₁ to 11
_n it is the supplied to each scan set terminal 18, the output of gate 31 is supplied to each of the scan reset terminal 19 of the LSI device 11 ₁ to 11 _n.

Scan address lines 33 connected in common to each of the scan address terminal 16 of the LSI device 11 ₁ to 11 _n are mounted on the board 22. The scan address line 33 is connected to the board terminal 25. Board scan address for selecting the LSI device applied to the board terminal 25 is supplied to the scan address decoder circuit 23, the scan address is a scan address line 33 to be supplied to each of the scan address terminal 16 of the LSI device 11 ₁ to 11 _n Supplied to

Scan read circuit 34 is mounted on the board 22, the output of each scan reading terminal 21 of the LSI device 11 ₁ to 11 _n is the logical sum is taken by the scan readout circuit 34, it is outputted to the board terminal 35. In this example, the output of the scan readout circuit 34 is a gate
The board scan enable signal from the board terminal 24 is supplied to the gate 36 as a gate signal, and the output of the gate 36 is output to the board terminal 37.

Since such configuration, even after the LSI device 11 ₁ to 11 _n of the scan address scheme is implemented on the board 22, provide the board scan enable signal to the board terminal 24 if necessary, the board terminals 25 giving board scan address, and decoded by the scan address decoder circuit 23, one of the LSI device 11 ₁ to 11 _n, for example, select 11 _2, giving a scan enable signal to the scan enable terminal 17 In the test ready state, the scan address is transferred from the board terminal 25 to the scan address line in this state.
When applied to 33, one of the storage elements in the LSI element 11 _2, which is a test state is selected by the scan address, if you give a "1" to the board terminal 28 as scan data in this state, this is through the gate 29, LS that can be tested
It is applied to the I element 11 ₂ of the scan set terminal 17, data "1" is written to the selected memory element. At that time, the output of the gate 31 when the board terminals 28 is "0" as the scan data given, i.e. the scan reset terminal 19 is "1", the selection memory element LSI element 11 ₂ data "0" is written .

Data read from the storage device test state and has been selected for LSI element 11 ₂ is outputted from the scan reading terminal 21 to the board terminal 35 through the scan read circuit 34. Even after mounted on the board 22 can thus be tested by effectively utilizing the stripped scan terminals of LSI device 11 ₁ to 11 _n. During the test, the board scan enable signal may be supplied to the board terminal 24 only when necessary, that is, only when data is read from or written to the selected storage element, but the board scan enable signal is always supplied to the board terminal 24. , The board 22 in the normal data processing state, the board scan address and the data state of the selected storage element of the LSI element selected by the scan address are obtained from the gate 36, and the board terminal 37
By observing the output of the oscilloscope, for example,
The transition of the internal state during operation can be observed.

FIG. 2 shows an embodiment of the second aspect of the present invention. Multiple LSI
The mounting boards 22 _{1 to} 22 _m and the control unit 38 are interconnected via a system bus 39, and the control unit 38 controls the LSI mounting board 22 ₁
M22 _m is controlled to perform data processing. This processing result is output from an output terminal not shown. In this embodiment, each of the LSI mounting boards 22 _{1 to} 22 _m is provided with a scan address type LSI element as shown in FIG. 1 and the scan terminals can be effectively used while mounted on the board. Boards are used. In this embodiment, a scan board register 41, a scan address register 42, and a scan data register means 43 are provided as a scan control unit 44, and these scan board registers 41, scan address registers 42, and scan data register means 43 are connected to a system bus 39. Have been. The scan board register 41 selects one of the LSI mounting boards 22 _{1 to} 22 _m according to the signal given from the control unit 38, and outputs a board scan enable signal through the board terminal 24 to each of the scans not shown in the figure. It can be supplied to the address decoder circuit 23 (FIG. 1).

The scan address register 42 is set with the board scan address and scan address from the control unit 38, and
The board scan address is sent to the scan address decoder circuit 23 through each board terminal 25 of the mounting board 22 _{1 to} 22 _m ,
And a scan address to the scan address line. Scan data register means 43 LSI mounting board 22 ₁ through 22 _m each board terminal 28 according to an instruction of the control unit 38
, And the output data of each readout circuit 34 can be taken in through each board terminal 35. Write enable from read / write control unit 45 to each LSI
Supplied to the scan data write circuit 26 through the mounting board 22 ₁ through 22 _m board terminal 32. Each LSI mounting board 22 _{1 to} 22
Each board terminal 37 of _m is separately led to the outside.

Since such configuration, in the test data processing apparatus, sets a signal indicating the LSI mounting board to be tested to the scan board register 41, giving the board scan enable signal its LSI implementation boards, for example, 22 _2, the Set the board scan address and scan address in the scan address register 42 in the
One of the mounting boards 22 _{1 to} 22 _m , for example, 22 ₂ is selected, further, one LSI element in the board 22 ₂ is selected, and one storage element in the LSI element is selected. The stored contents can be taken into the scan data register means 43 from the board terminal 35, and then the scan data can be written from the scan data register means 43 to the selected storage element. In this manner, a test can be performed by effectively utilizing the scan terminals of the scan address type LSI elements mounted in the data processing device.

As the scan data register means 43, one register is used to store the scan data read from the LSI element, read this by the control unit 38, and store the scan data to be written in the register. Alternatively, a register for storing read data and a register for storing scan data to be written may be separately provided.

Furthermore, when normal data processing is performed by this data processing device, the scan board register
Set the signal indicating the LSI mounting board to be selected in 41,
A board scan enable signal is output to the board, and in this state, the board scan address set in the scan address register 42 and the state change of the selected storage element in the selected LSI element in the LSI mounting board selected by the scan address are determined. It can be known by observing the output of the board terminal 37. LSI mounting board 22 _{1 to} 22 _m
, A board scan enable signal may be simultaneously applied to all the terminals 24 so that the state of the selected storage element among the selected LSI elements in each board is simultaneously output to each board terminal 37 so as to be simultaneously observed.

The third aspect of the present invention requires the configuration shown in FIG. 2 to monitor the internal state of the selected storage element during actual data processing. Therefore, when only the monitoring function using the scan terminal is required, the scan data writing circuit 26 can be omitted in FIG. 1, and the scan data register means 43 and the read / write control unit 44 are omitted in FIG. The status of the selected storage element of the selected LSI element of the selected board is monitored. The scan board register 41 may also be omitted, and the board scan enable signal “1” may be constantly supplied to the terminal 24 of each board, that is, the board may be always operable, and the boards may be simultaneously observed. Further, the output of the scan reading circuit 34 may be directly supplied to the board terminal 37.

[Effects of the Invention] As described above, according to the first aspect of the present invention, a scan address decoder circuit, a scan address line, a scan data write circuit, and a scan read circuit are mounted on a board on which a scan address type LSI element is mounted. By doing so, the test can be performed by effectively using the scan terminal of the LSI element.

According to the invention of claim 2, the LS in the data processing device
By using the I-mounted board as the LSI-mounted board according to the first aspect of the present invention and providing a scan board register, a scan address register, and a scan data register, the scan terminals of the LSI elements can be effectively used when testing the data processing device. be able to.

According to the invention of claim 3, in the data processing device,
By mounting a scan address decoder circuit, a scan address line, and a scan readout circuit on a board on which a scan address LSI element is mounted, using the scan terminal of the LSI element during actual operation of the data processing device,
The state of the data in the selected internal storage element can be monitored.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the invention of claim 1, FIG. 2 is a block diagram showing an embodiment of the invention of claim 2, and FIG.
The figure is a block diagram functionally showing a scan address type LSI element.

Claims (3)

(57) [Claims] In a board on which an LSI element of an address scan system is mounted, a board scan address can be decoded, one of the LSI elements can be tested, and an operation can be performed by a board scan enable signal. A scan address decoder circuit, a scan address line commonly connected to the scan address terminals of the respective LSI elements, and a scan which is controlled by a write enable signal and provides scan data to the scan data write terminals of the respective LSI elements in common An LSI mounting board comprising: a write data circuit; and a scan read circuit to which data from a scan read terminal of each of the above-described LSI elements is input. 2. A data processing device for performing data processing by operating at least one LSI mounting board by a control unit, wherein the LSI mounting board is constituted by the LSI mounting board according to claim 1. A scan board register that selects one of the above and supplies the board scan enable signal thereto; and a scan that applies the board scan address to the scan address decoder circuit of each of the LSI mounting boards and the scan address to the address line. A data processing device, comprising: an address register; and scan data register means for supplying scan data to the scan write data circuit of each of the LSI mounting boards and receiving an output of the scan read circuit. . 3. A data processing device for performing data processing by operating at least one LSI mounting board by a control unit, wherein at least one of the LSI mounting boards has an LSI element of an address scan system mounted thereon, and , Decode the board scan address and
A scan address decoder circuit capable of selecting one of the elements and operable by a board scan enable signal, a scan address line commonly connected to a scan address terminal of each of the LSI elements, and each of the LSI elements A scan readout circuit to which data from the scan readout terminal is input; a scan board register for selecting one of the above-mentioned LSI mounting boards and supplying the board scan enable signal thereto; A data processing apparatus, further comprising: a scan address register for providing the board scan address to the scan address decoder circuit and a scan address to the scan address line.