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JP3139523B2 - Radiation fin - Google Patents

Radiation fin

Info

Publication number
JP3139523B2
JP3139523B2 JP16372594A JP16372594A JP3139523B2 JP 3139523 B2 JP3139523 B2 JP 3139523B2 JP 16372594 A JP16372594 A JP 16372594A JP 16372594 A JP16372594 A JP 16372594A JP 3139523 B2 JP3139523 B2 JP 3139523B2
Authority
JP
Japan
Prior art keywords
metal layer
ceramic
fin
aluminum material
covering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP16372594A
Other languages
Japanese (ja)
Other versions
JPH0831990A (en
Inventor
敏之 長瀬
義雄 神田
昌文 初鹿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP16372594A priority Critical patent/JP3139523B2/en
Publication of JPH0831990A publication Critical patent/JPH0831990A/en
Application granted granted Critical
Publication of JP3139523B2 publication Critical patent/JP3139523B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、セラミック回路基板に
実装されたシリコン半導体チップから発生する熱を大気
に放散させるための放熱フィンに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radiating fin for dissipating heat generated from a silicon semiconductor chip mounted on a ceramic circuit board to the atmosphere.

【0002】[0002]

【従来の技術】従来、この種の放熱フィンとして、窒化
アルミニウム(以下、AlNという)等の高熱伝導性セ
ラミックスを切削加工することにより形成されたフィン
本体を接着剤によりシリコン半導体チップ又はセラミッ
ク基板に接着したものが知られている。この放熱フィン
では、フィン本体が半導体チップ又はセラミック基板と
熱膨張係数が整合されているため、半導体チップ又はセ
ラミック基板とフィン本体とに熱が加わっても反りが発
生しないようになっている。
2. Description of the Related Art Heretofore, as a heat radiation fin of this kind, a fin body formed by cutting a high thermal conductive ceramic such as aluminum nitride (hereinafter, referred to as AlN) is attached to a silicon semiconductor chip or a ceramic substrate with an adhesive. Bonded ones are known. In this radiating fin, since the fin main body and the semiconductor chip or the ceramic substrate have the same coefficient of thermal expansion, even if heat is applied to the semiconductor chip or the ceramic substrate and the fin main body, no warping occurs.

【0003】[0003]

【発明が解決しようとする課題】しかし、上記従来の放
熱フィンでは、フィン本体が硬くて脆いAlNを切削加
工して形成されるため、フィン本体の加工工数が増大し
て製造コストを押上げる不具合があり、フィン本体が比
較的小さい衝撃で欠ける恐れがあった。また、上記従来
の放熱フィンの熱伝導率は比較的小さいため、フィン本
体の放熱特性があまり良くない問題点もあった。更に、
上記従来の放熱フィンにて、フィン本体をシリコン半導
体チップ又はセラミック基板にはんだを介して接着する
場合、予め接着面にメタライズ処理を施す必要があり、
これがフィン本体の変形の原因になっていた。
However, in the conventional radiating fins described above, since the fin main body is formed by cutting hard and brittle AlN, the number of processing steps of the fin main body is increased and the manufacturing cost is increased. There was a possibility that the fin body might be chipped by a relatively small impact. In addition, since the heat conductivity of the above-described conventional radiating fin is relatively small, there is a problem that the radiating characteristic of the fin body is not very good. Furthermore,
When the fin body is bonded to the silicon semiconductor chip or the ceramic substrate via solder with the above-described conventional radiating fins, it is necessary to perform a metallizing process on the bonding surface in advance,
This caused the deformation of the fin body.

【0004】本発明の目的は、熱変形を吸収して反りを
防止でき、フィン本体の加工工数を低減でき、かつ衝撃
が作用しても破損し難い放熱フィンを提供することにあ
る。また本発明の別の目的は、放熱特性を向上でき、か
つセラミック回路基板に半導体チップが実装された後で
も接着できる放熱フィンを提供することにある。
An object of the present invention is to provide a heat radiation fin that can absorb thermal deformation and prevent warpage, reduce the number of processing steps of the fin body, and is not easily damaged by an impact. Another object of the present invention is to provide a heat radiation fin that can improve heat radiation characteristics and can be adhered even after a semiconductor chip is mounted on a ceramic circuit board.

【0005】[0005]

【0006】[0006]

【課題を解決するための手段】 本発明の請求項1に係る
発明は、図3に示すようにセラミック回路基板13に実
装したチップ12の外面にはんだ又は接着剤を介して直
接接着される放熱フィン11であって、チップ12の外
面を被覆可能な面積を有するアルミニウム材からなる第
1金属層21と、第1金属層21を被覆可能な面積を有
するセラミック基板18と、セラミック基板18を被覆
可能な面積を有するアルミニウム材からなる第2金属層
22と、第2金属層22を被覆可能な面積を有するアル
ミニウム材からなるフィン本体19とがそれぞれAl系
ろう材を介してこの順に積層接着されたものである。本
発明の請求項2に係る発明は、セラミック回路基板に実
装したチップの外面にはんだ又は接着剤を介して直接接
着される放熱フィンであって、チップの外面を被覆可能
な面積を有するアルミニウム材からなる第1金属層と、
第1金属層を被覆可能な面積を有するセラミック基板
と、セラミック基板を被覆可能な面積を有するアルミニ
ウム材からなるフィン本体とがそれぞれAl系ろう材を
介してこの順に積層接着されたものである。
Means for Solving the Problems According to claim 1 of the present invention.
The present invention is a radiation fin 11 directly bonded to the outer surface of a chip 12 mounted on a ceramic circuit board 13 via solder or an adhesive as shown in FIG. 3, and has an area capable of covering the outer surface of the chip 12. A first metal layer 21 made of an aluminum material, a ceramic substrate 18 having an area capable of covering the first metal layer 21, a second metal layer 22 made of an aluminum material having an area capable of covering the ceramic substrate 18, The fin body 19 made of an aluminum material having an area capable of covering the two metal layers 22 is laminated and bonded in this order via an Al-based brazing material. According to a second aspect of the present invention, there is provided a heat radiation fin directly bonded to an outer surface of a chip mounted on a ceramic circuit board via a solder or an adhesive, the aluminum material having an area capable of covering the outer surface of the chip. A first metal layer comprising:
A ceramic substrate having an area capable of covering the first metal layer and a fin body made of an aluminum material having an area capable of covering the ceramic substrate are laminated and bonded in this order via an Al-based brazing material.

【0007】また、請求項3に係る発明は、請求項1又
は2に係る発明であって、更にセラミック基板のチッ
対向する位置に複数の熱伝導用スルーホールが設けら
、複数の熱伝導用スルーホールにアルミニウム材
れぞれ充填されたことを特徴とする本発明の請求項4
に係る発明は、図6に示すように、表面にチップ12を
実装したセラミック回路基板13の裏面にはんだ又は接
着剤を介して直接接着される放熱フィン11であって、
セラミック回路基板13の裏面を被覆可能な面積を有す
るアルミニウム材からなる第1金属層21と、第1金属
層21を被覆可能な面積を有するセラミック基板18
と、セラミック基板18を被覆可能な面積を有するアル
ミニウム材からなる第2金属層22と、第2金属層22
を被覆可能な面積を有するアルミニウム材からなるフィ
ン本体19とがそれぞれAl系ろう材を介してこの順に
積層接着され、セラミック基板18のチップ12に対向
する位置に複数の熱伝導用スルーホール111が設けら
れ、複数の熱伝導用スルーホール111にアルミニウム
材112がそれぞれ充填されたことを特徴とする。 請求
項5に係る発明は、表面にチップを実装したセラミック
回路基板の裏面にはんだ又は接着剤を介して直接接着さ
れる放熱フィンであって、セラミック回路基板の裏面を
被覆可能な面積を有するアルミニウム材からなる第1金
属層と、第1金属層を被覆可能な面積を有するセラミッ
ク基板と、セラミック基板を被覆可能な面積を有するア
ルミニウム材からなるフィン本体とがそれぞれAl系ろ
う材を介してこの順に積層接着され、セラミック基板の
チップに対向する位置に複数の熱伝導用スルーホールが
設けられ、複数の熱伝導用スルーホールにアルミニウム
材がそれぞれ充填されたことを特徴とする。また、図1
及び図3に示すように第2金属層22の厚さは第1金属
層21の厚さの2/3以下であることが好ましい。更
に、図5に示すようにフィン本体99が凸条99aを有
するコルゲートフィンであって、フィン本体99を凸条
99aに直交する方向に切断することにより複数分割す
ることが好ましい。
[0007] The invention according to claim 3 is based on claim 1 or
Is an invention according to 2, further chip ceramic board
Et provided with through holes for a plurality of heat conduction in a position opposed to
Is characterized in that the aluminum material is filled their <br/> respectively to a plurality of heat conduction Suruho Le. Claim 4 of the present invention
According to the invention according to the present invention, as shown in FIG.
Solder or contact the back of the mounted ceramic circuit board 13
A radiation fin 11 directly adhered via an adhesive,
It has an area that can cover the back surface of the ceramic circuit board 13
A first metal layer 21 made of aluminum material and a first metal
Ceramic substrate 18 having an area capable of covering layer 21
And an area having an area capable of covering the ceramic substrate 18.
A second metal layer 22 made of a minium material;
Of aluminum material with an area that can cover
And the main body 19 in this order via the Al-based brazing material.
Laminated and opposed to the chip 12 of the ceramic substrate 18
Are provided with a plurality of through holes 111 for heat conduction.
And a plurality of heat conduction through holes 111
It is characterized in that each of the materials 112 is filled. Claim
Item 5 relates to a ceramic having a chip mounted on the surface.
Directly bonded to the back of the circuit board via solder or adhesive
Radiating fins,
First gold made of aluminum material having an area that can be covered
A ceramic having an area capable of covering the metal layer and the first metal layer.
With an area that can cover the ceramic substrate and the ceramic substrate.
The fin body made of Luminium material is an Al filter
Laminated in this order via the filler material,
Multiple heat conduction through holes at the position facing the chip
Aluminum heat transfer through holes
It is characterized by being filled with materials. FIG.
As shown in FIG. 3, the thickness of the second metal layer 22 is preferably not more than / of the thickness of the first metal layer 21. Further, as shown in FIG. 5, the fin body 99 is a corrugated fin having a ridge 99a, and it is preferable that the fin body 99 is divided into a plurality by cutting in a direction orthogonal to the ridge 99a.

【0008】[0008]

【作用】図に示される放熱フィンでは、チップ12よ
り発生した熱が直接熱伝導率の大きい第1金属層21内
で全面に広がるとともに、セラミック基板18を介して
熱伝導率の大きい第2金属層22に伝わり、更に第2金
属層22内で全面に広がってフィン本体19に伝わり、
このフィン本体19から大気に放散される。
In the heat radiation fin shown in FIG. 3 , the heat generated from the chip 12 spreads directly over the entire surface of the first metal layer 21 having a high thermal conductivity, and the second heat fin has a high thermal conductivity via the ceramic substrate 18. Transmitted to the metal layer 22, further spread over the entire surface in the second metal layer 22 and transmitted to the fin body 19,
Ru is dissipated to the atmosphere from the fin body 19.

【0009】[0009]

【実施例】次に本発明の第1実施例を図面に基づいて詳
しく説明する。図1に示すように、放熱フィン11は表
面にシリコン半導体チップ12を実装する薄膜多層セラ
ミック回路基板13の裏面に接着剤を介して直接接着さ
れる。セラミック回路基板13は複数のAl23基板1
4と回路を形成する複数のタングステン導体16とを1
600℃前後の高温で同時焼成して積層接着することに
より形成される。セラミック回路基板13の表面には半
導体チップ12がAl−Siはんだを用いて420℃で
ダイボンディングされた後、300℃でAuワイヤ17
によりワイヤボンディングを行うことにより実装され
る。この例では半導体チップ12はセラミック回路基板
13の表面に所定の間隔をあけて3個実装される。これ
らの半導体チップ12は一辺が33mmの正方形をな
す。
Next, a first embodiment of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, the radiation fins 11 are directly bonded to the back surface of a thin-film multilayer ceramic circuit board 13 on which a silicon semiconductor chip 12 is mounted via an adhesive. The ceramic circuit board 13 includes a plurality of Al 2 O 3 substrates 1
4 and a plurality of tungsten conductors 16 forming a circuit
It is formed by simultaneous firing at a high temperature of about 600 ° C. and laminating and bonding. After the semiconductor chip 12 is die-bonded on the surface of the ceramic circuit board 13 at 420 ° C. using Al—Si solder, the Au wire 17 is formed at 300 ° C.
And is implemented by performing wire bonding. In this example, three semiconductor chips 12 are mounted on the surface of the ceramic circuit board 13 at predetermined intervals. These semiconductor chips 12 form a square having a side of 33 mm.

【0010】放熱フィン11はセラミック回路基板13
の裏面のうち半導体チップ12に対向する位置に配設さ
れセラミック回路基板13の裏面を被覆可能な面積を有
する3枚の第1金属層21と、3枚の第1金属層21を
それぞれ被覆可能な面積を有する3枚のセラミック基板
18と、3枚のセラミック基板18を被覆可能な面積を
有する3枚の第2金属層22と、3枚の第2金属層22
を被覆可能な面積を有する3個のフィン本体19とを備
える。第1及び第2金属層21,22は97%以上のア
ルミニウムを含むアルミニウム合金により形成され、セ
ラミック基板18はこの例ではAl23により形成され
る。第1金属層21、第2金属層22及びセラミック基
板18は一辺が40mmの正方形をなし、第1金属層2
1、第2金属層22及びセラミック基板18の厚さはそ
れぞれ0.4mm、0.2mm及び0.635mmであ
る。
The radiating fins 11 are formed on a ceramic circuit board 13.
Three first metal layers 21 which are disposed at positions facing the semiconductor chip 12 on the back surface of the semiconductor chip 12 and have an area capable of covering the back surface of the ceramic circuit board 13, and which can cover the three first metal layers 21, respectively. Ceramic substrates 18 having different areas, three second metal layers 22 having an area capable of covering the three ceramic substrates 18, and three second metal layers 22
And three fin bodies 19 having an area capable of covering the fin body 19. The first and second metal layers 21 and 22 are formed of an aluminum alloy containing 97% or more of aluminum, and the ceramic substrate 18 is formed of Al 2 O 3 in this example. The first metal layer 21, the second metal layer 22, and the ceramic substrate 18 form a square having a side of 40 mm.
The thicknesses of the first, second metal layers 22 and the ceramic substrate 18 are 0.4 mm, 0.2 mm and 0.635 mm, respectively.

【0011】第1金属層21の上にセラミック基板18
が厚さ30μmのAl−7.5%Si箔(重量%、以下
同じ)を挟んで載せられ、このセラミック基板18の上
に第2金属層22が厚さ30μmのAl−7.5%Si
箔を挟んで載せられ、この状態でこれらに2kgf/c
2の荷重を加えて真空炉中で630℃、30分加熱す
ることにより、第1金属層21とセラミック基板18と
第2金属層22とが積層接着される。
The ceramic substrate 18 is provided on the first metal layer 21.
Is placed with a 30 μm thick Al-7.5% Si foil (weight%, the same applies hereinafter). A second metal layer 22 is formed on the ceramic substrate 18 with a 30 μm thick Al-7.5% Si foil.
Placed on top of a foil, and in this state, 2kgf / c
By applying a load of m 2 and heating at 630 ° C. for 30 minutes in a vacuum furnace, the first metal layer 21, the ceramic substrate 18 and the second metal layer 22 are laminated and bonded.

【0012】フィン本体19は図1及び図2に示すよう
に、横方向に所定の間隔をあけて設けられた複数の第1
突起19aと、第1突起19aに連設され第1突起19
aより横方向に所定の距離だけずらして設けられた複数
の第2突起19bと、第1及び第2突起19a,19b
間に形成された窓19cとを有するアルミニウム製のコ
ルゲートルーバフィンである。第1突起19aと第2突
起19bは縦方向に交互に連設される。フィン本体19
は厚さ0.3mmの87%以上のアルミニウムを含むア
ルミニウム合金板をプレス加工することにより形成さ
れ、その縦及び横は上記金属層21,22と略同一寸法
であり、高さは6mmである。上記積層接着された第2
金属層22の上にフィン本体19が60μmのAl−
7.5%Si箔を挟んで載せられ、この状態でこれらに
20g/cm2の荷重を加えて真空炉中で630℃、3
0分加熱することにより、フィン本体19が第2金属層
22に接着されて放熱フィン11が形成される。上記3
個の放熱フィン19は第1金属層21をセラミック回路
基板13の裏面、即ち最も下方に位置するAl23基板
14の裏面に3個の半導体チップ12の真下にそれぞれ
位置するように接着剤であるエポキシ系の樹脂により接
着することによりセラミック回路基板13に直接接着さ
れる。
As shown in FIGS. 1 and 2, the fin body 19 has a plurality of first fins provided at predetermined intervals in the lateral direction.
A projection 19a, a first projection 19 connected to the first projection 19a,
a, a plurality of second protrusions 19b provided in the lateral direction with a predetermined distance from the first protrusion 19a, and first and second protrusions 19a, 19b.
It is an aluminum corrugated louver fin having a window 19c formed therebetween. The first projections 19a and the second projections 19b are alternately provided in the vertical direction. Fin body 19
Is formed by pressing an aluminum alloy plate containing 87% or more of aluminum having a thickness of 0.3 mm, its length and width are substantially the same as those of the metal layers 21 and 22, and its height is 6 mm. . The second laminated and bonded
On the metal layer 22, the fin body 19 is made of 60 μm Al-
In this state, a load of 20 g / cm 2 is applied to these at a temperature of 630 ° C. in a vacuum furnace.
By heating for 0 minutes, the fin body 19 is adhered to the second metal layer 22 to form the radiation fin 11. 3 above
The heat dissipating fins 19 are bonded to the first metal layer 21 such that the first metal layer 21 is located on the back surface of the ceramic circuit board 13, that is, on the back surface of the lowermost Al 2 O 3 substrate 14, directly below the three semiconductor chips 12. Is bonded directly to the ceramic circuit board 13 by bonding with an epoxy resin.

【0013】このように構成された放熱フィンの動作を
説明する。シリコン半導体チップ12より発生した熱
は、薄膜多層セラミック回路基板13を介して熱伝導率
の大きい第1金属層21内で全面に広がるとともに、セ
ラミック基板18を介して熱伝導率の大きい第2金属層
22に伝わる。この熱は更に第2金属層22内で全面に
広がってフィン本体19に伝わり、このフィン本体19
から大気にスムーズに放散される。この結果、半導体チ
ップ12の温度上昇を低く抑えることができる。またセ
ラミック回路基板13及びフィン本体19は熱膨張係数
に違いがあるが、セラミック基板18の両面に変形抵抗
の小さい第1及び第2金属層21,22を接着し、かつ
セラミック基板18の熱膨張係数がセラミック回路基板
13と略同等であるため、接着材で接着しても、その接
着面での熱サイクルによる剥がれを防止できる。
The operation of the radiation fin thus configured will be described. The heat generated from the silicon semiconductor chip 12 spreads over the entire surface of the first metal layer 21 having a high thermal conductivity via the thin-film multilayer ceramic circuit board 13 and the second metal having a high thermal conductivity via the ceramic substrate 18. Transfer to layer 22. This heat further spreads over the entire surface in the second metal layer 22 and is transmitted to the fin body 19, and the fin body 19
From the air to the atmosphere. As a result, the temperature rise of the semiconductor chip 12 can be suppressed low. Although the ceramic circuit board 13 and the fin body 19 have different coefficients of thermal expansion, the first and second metal layers 21 and 22 having low deformation resistance are bonded to both surfaces of the ceramic substrate 18 and the thermal expansion of the ceramic substrate 18 is improved. Since the coefficient is substantially the same as that of the ceramic circuit board 13, peeling due to thermal cycling on the bonding surface can be prevented even when bonding is performed with an adhesive.

【0014】図3は本発明の第2実施例を示す。図3に
おいて図1と同一符号は同一部品を示す。この例では、
放熱フィン11は第1実施例と同様に形成された薄膜多
層セラミック回路基板13に実装したシリコン半導体チ
ップ12の外面にはんだを介して直接接着される。半導
体チップ12はセラミック回路基板13の表面にはんだ
バンプ51を介して実装される。はんだバンプ51は半
導体チップ12の表面の電極上にはんだを突起状に盛り
上げたものであり、Ni及びAuの複合めっきが施され
たCuボールにより、或いはPb及びSnの合金により
形成される。半導体チップ12の電極上に盛り上げられ
たはんだバンプ51をセラミック回路基板13のタング
ステン導体16の端子にフラックスの粘着力で仮固定
し、この状態で加熱してはんだバンプ51を溶融するこ
とにより、半導体チップ12がセラミック回路基板13
に実装される。半導体チップ12は一辺が33mmの正
方形をなす。
FIG. 3 shows a second embodiment of the present invention. 3, the same reference numerals as those in FIG. 1 indicate the same parts. In this example,
The radiation fins 11 are directly bonded to the outer surface of the silicon semiconductor chip 12 mounted on the thin-film multilayer ceramic circuit board 13 formed in the same manner as in the first embodiment via solder. The semiconductor chip 12 is mounted on the surface of the ceramic circuit board 13 via solder bumps 51. The solder bumps 51 are formed by projecting solder on the electrodes on the surface of the semiconductor chip 12 in a protruding manner, and are formed by a Cu ball plated with a composite plating of Ni and Au or by an alloy of Pb and Sn. The solder bumps 51 raised on the electrodes of the semiconductor chip 12 are temporarily fixed to the terminals of the tungsten conductors 16 of the ceramic circuit board 13 by the adhesive force of the flux, and the solder bumps 51 are melted by heating in this state. The chip 12 is a ceramic circuit board 13
Implemented in The semiconductor chip 12 forms a square having a side of 33 mm.

【0015】放熱フィン19は半導体チップ12の外面
を被覆可能な面積を有する第1金属層21と、第1金属
層21を被覆可能な面積を有するセラミック基板18
と、セラミック基板18を被覆可能な面積を有する第2
金属層22と、第2金属層22を被覆可能な面積を有す
るフィン本体19とを備える。第1金属層21、第2金
属層22及びセラミック基板18は第1実施例の第1金
属層、第2金属層及びセラミック基板とそれぞれ同一材
料により同一寸法に形成され、第1金属層21、第2金
属層22及びセラミック基板18は第1実施例の第1金
属層、第2金属層及びセラミック基板と同様にして積層
接着される。
The radiating fins 19 have a first metal layer 21 having an area capable of covering the outer surface of the semiconductor chip 12 and a ceramic substrate 18 having an area capable of covering the first metal layer 21.
And a second having an area capable of covering the ceramic substrate 18.
The fin body includes a metal layer and a fin body having an area capable of covering the second metal layer. The first metal layer 21, the second metal layer 22, and the ceramic substrate 18 are formed of the same material and have the same dimensions as the first metal layer, the second metal layer, and the ceramic substrate of the first embodiment. The second metal layer 22 and the ceramic substrate 18 are laminated and bonded in the same manner as the first metal layer, the second metal layer, and the ceramic substrate of the first embodiment.

【0016】またフィン本体19は第1実施例と同一材
料により同一形状に形成されたコルゲートルーバフィン
であり、フィン本体19は第1実施例と同様にして上記
積層接着された第2金属層22の上に接着されて放熱フ
ィン11が形成される。放熱フィン19のうち半導体チ
ップ12の外面にはんだを介して接着される面、即ち第
1金属層21の裏面には予めNiめっきが施され、半導
体チップ12の外面には予めNiメタライズ等の裏面処
理が施される。放熱フィン19は半導体チップ12の外
面に厚さ50〜100μmのSn−3.5%Agはんだ
箔を介して載せられ、この状態で10g/cm2の荷重
を加えてリフロー炉中で260℃、1〜3分加熱するこ
とにより、半導体チップ12の外面に直接接着される。
The fin body 19 is a corrugated louver fin formed of the same material and in the same shape as in the first embodiment, and the fin body 19 is formed by laminating and bonding the second metal layer 22 in the same manner as in the first embodiment. The heat radiation fins 11 are formed by being bonded on the fins. The surface of the radiating fins 19 that is bonded to the outer surface of the semiconductor chip 12 via solder, that is, the back surface of the first metal layer 21 is pre-plated with Ni, and the outer surface of the semiconductor chip 12 is back surface such as Ni metallized. Processing is performed. The radiating fins 19 are placed on the outer surface of the semiconductor chip 12 via a Sn-3.5% Ag solder foil having a thickness of 50 to 100 μm. In this state, a load of 10 g / cm 2 is applied, and the radiating fins 19 are heated at 260 ° C. By heating for 1 to 3 minutes, the semiconductor chip 12 is directly bonded to the outer surface.

【0017】このように構成された放熱フィンでは、シ
リコン半導体チップ12より発生した熱が直接熱伝導率
の大きい第1金属層21内で全面に広がることを除い
て、動作が第1実施例と同様であるので、繰返しの説明
を省略する。
The operation of the radiation fin thus configured is the same as that of the first embodiment except that the heat generated from the silicon semiconductor chip 12 directly spreads over the entire surface in the first metal layer 21 having a high thermal conductivity. Since it is the same, a repeated description is omitted.

【0018】なお、上記第1及び第2実施例ではフィン
本体として第1突起と第1突起より横方向にずらして設
けられた第2突起と第1及び第2突起間に形成された窓
とを有するアルミニウム製のコルゲートルーバフィンを
挙げたが、図4に示すようにフィン本体79が断面略蜂
の巣状のアルミニウム製のコルゲートハニカムフィンで
もよく、また図5に示すようにフィン本体99が横方向
に所定の間隔をあけて縦方向に伸びる複数の凸条99a
とこれらの凸条99aの両端に形成された開口99bと
を有するアルミニウム製のコルゲートフィンでもよい。
このフィン本体99を図1のセラミック基板に第2金属
層を介して接着する場合、凸条99aに直交する方向に
切断することにより複数分割しておくと、フィン本体9
9を上記セラミック基板に接着したときの熱膨張係数の
相違に起因した反りを減少することができ、好ましい。
また図示しないがフィン本体は取付板から多数のピンが
突設されたアルミニウム製のピンフィンでもよい。
In the first and second embodiments, the fin body includes a first projection, a second projection provided laterally shifted from the first projection, and a window formed between the first and second projections. Although the aluminum corrugated louver fins having the above-mentioned structure are mentioned, the fin body 79 may be an aluminum corrugated honeycomb fin having a substantially honeycomb shape as shown in FIG. A plurality of ridges 99a extending in the vertical direction at predetermined intervals
And aluminum corrugated fins having openings 99b formed at both ends of the ridges 99a.
When the fin body 99 is bonded to the ceramic substrate of FIG. 1 via the second metal layer, the fin body 9 is cut into a plurality of sections by cutting in a direction perpendicular to the ridges 99a.
This is preferable because warpage caused by a difference in the coefficient of thermal expansion when the substrate 9 is bonded to the ceramic substrate can be reduced.
Although not shown, the fin body may be an aluminum pin fin having a large number of pins projecting from the mounting plate.

【0019】また、図6に示すように第1実施例のセラ
ミック基板18のチップ12に対向する位置に複数の熱
伝導用スルーホール111を設け、これらのスルーホー
ル111にアルミニウム材112をそれぞれ充填しても
よい。この場合、第1金属層21の熱がアルミニウム材
112を通ってよりスムーズに第2金属層22に伝わる
ことができる。また図示しないが第2実施例のセラミッ
ク基板18にアルミニウム材が充填される熱伝導用スル
ーホールを設けてもよい。また、上記第1実施例では放
熱フィンをエポキシ系の接着剤によりセラミック回路基
板に直接接着したが、厚さ50〜100μmのSn−
3.5%Agはんだを介して直接接着してもよい。ま
た、上記第2実施例では放熱フィンを厚さ50〜100
μmのSn−3.5%Agはんだ箔を介してシリコン半
導体チップの外面に直接接着したが、ペースト状のクリ
ームはんだを介して直接接着してもよく、或いはエポキ
シ系の接着剤により直接接着してもよい。また、上記第
1及び第2実施例では第1及び第2金属層の間に位置す
るセラミック基板としてAl23により形成されたもの
を挙げたが、これは一例であってAlN又はSiCによ
り形成してもよい。
As shown in FIG. 6, a plurality of through holes 111 for heat conduction are provided at positions facing the chips 12 of the ceramic substrate 18 of the first embodiment, and these through holes 111 are filled with an aluminum material 112, respectively. May be. In this case, the heat of the first metal layer 21 can be transmitted to the second metal layer 22 more smoothly through the aluminum material 112. Although not shown, a through hole for heat conduction filled with an aluminum material may be provided in the ceramic substrate 18 of the second embodiment. In the first embodiment, the radiation fins are directly adhered to the ceramic circuit board with an epoxy-based adhesive.
It may be bonded directly via 3.5% Ag solder. In the second embodiment, the radiation fins have a thickness of 50 to 100.
Although it was directly bonded to the outer surface of the silicon semiconductor chip via the Sn-3.5% Ag solder foil of μm, it may be directly bonded via a paste-like cream solder, or directly by an epoxy-based adhesive. You may. In the first and second embodiments, the ceramic substrate located between the first and second metal layers is made of Al 2 O 3. However, this is an example, and the ceramic substrate is made of AlN or SiC. It may be formed.

【0020】また、上記第1及び第2実施例では第1金
属層、第2金属層及びセラミック基板の厚さをそれぞれ
0.4mm、0.2mm及び0.635mmに形成した
が、第1金属層の厚さは0.1〜1.0mmの範囲内に
あればよく、第2金属層の厚さは第1金属層の厚さの2
/3以下であって0〜0.5mmの範囲内にあればよ
く、更にセラミック基板の厚さは第1金属層の厚さの1
〜10倍であって0.1〜1.0mmの範囲内にあれば
よい。従って、図7に示すように第2金属層を用いずに
セラミック基板18の裏面に直接フィン本体19をAl
系ろう材を介して接着してもよい。この場合、フィン本
体19のセラミック基板18への接着部が第2金属層の
役割を果たす。上記のように厚さを限定したのは、第1
金属層の厚さが0.1mm未満であるとチップにて発生
した熱の放熱性が十分でなく、第1及び第2金属層の厚
さがそれぞれ1.0mm及び0.5mmを越えると接着
後の応力緩和時のクラック、割れが生じ易くなるためで
ある。またセラミック基板の厚さが0.1mm未満であ
ると絶縁特性及び機械的強度に劣り、1.0mmを越え
るとAl23の場合は熱抵抗が大きくなる問題点がある
ためである。しかしアルミニウムと同等な高熱伝導性を
有するセラミックスであるAlNやSiCを用いた場合
はこの限りではない。更に、上記第1及び第2実施例で
はAl系ろう材としてAl−7.5%Si箔を例示した
が、これ以外にAl−13%Si、Al−9.5%Si
−1.0%Mg、Al−7.5%Si−10%Ge等か
らなる箔を用いることもできる。
In the first and second embodiments, the thicknesses of the first metal layer, the second metal layer and the ceramic substrate are 0.4 mm, 0.2 mm and 0.635 mm, respectively. The thickness of the layer may be in the range of 0.1 to 1.0 mm, and the thickness of the second metal layer is two times the thickness of the first metal layer.
/ 3 or less and within a range of 0 to 0.5 mm, and the thickness of the ceramic substrate is 1 to the thickness of the first metal layer.
It is sufficient that it is 10 to 10 times and within the range of 0.1 to 1.0 mm. Therefore, as shown in FIG. 7, the fin body 19 is directly formed on the back surface of the ceramic substrate 18 without using the second metal layer.
It may be bonded via a brazing filler metal. In this case, the bonding portion of the fin body 19 to the ceramic substrate 18 plays the role of the second metal layer. The reason for limiting the thickness as described above is that
When the thickness of the metal layer is less than 0.1 mm, the heat generated from the chip is not sufficiently dissipated, and when the thickness of the first and second metal layers exceeds 1.0 mm and 0.5 mm, respectively, the bonding is performed. This is because cracks and cracks are likely to occur when the stress is relaxed later. If the thickness of the ceramic substrate is less than 0.1 mm, the insulating properties and mechanical strength are inferior. If the thickness exceeds 1.0 mm, the thermal resistance of Al 2 O 3 increases. However, this is not the case when AlN or SiC, which is a ceramic having high thermal conductivity equivalent to aluminum, is used. Further, in the first and second embodiments, the Al-7.5% Si foil is exemplified as the Al-based brazing material, but in addition to this, Al-13% Si, Al-9.5% Si foil is used.
A foil made of -1.0% Mg, Al-7.5% Si-10% Ge, or the like can also be used.

【0021】[0021]

【発明の効果】以上述べたように、本発明によれば、
ラミック回路基板に実装したチップの外面に、アルミニ
ウム材からなる第1金属層、セラミック基板、アルミニ
ウム材からなる第2金属層及びフィン本体をこの順にそ
れぞれAl系ろう材を介して積層接着したので、フィン
本体とセラミック基板との熱膨張係数の差による熱変形
を変形抵抗の小さい第1及び第2金属層により吸収でき
る。またAlNにより形成されたフィン本体を有する従
来の放熱フィンと比較して、本発明ではフィン本体の加
工工数を低減でき、フィン本体に衝撃が作用しても破損
し難く、更にフィン本体の放熱特性を向上できる。
As described above, according to the present invention, the cell
The first metal layer made of aluminum material, the ceramic substrate, the second metal layer made of aluminum material, and the fin body were laminated and bonded in this order to the outer surface of the chip mounted on the lamic circuit board via an Al-based brazing material. Thermal deformation due to the difference in thermal expansion coefficient between the fin body and the ceramic substrate can be absorbed by the first and second metal layers having low deformation resistance.
You. Also, in comparison with a conventional heat dissipating fin having a fin body made of AlN, the present invention can reduce the number of processing steps of the fin body, is less likely to be damaged even when an impact is applied to the fin body, and furthermore has a heat radiation characteristic of the fin body. Can be improved.

【0022】またセラミック回路基板に半導体チップを
実装した後でも、半導体チップやセラミック回路基板の
既にはんだ付けされた箇所が溶け剥がれることなくセラ
ミック回路基板に放熱フィンを接着できる。更にセラミ
ック基板のチップに対向する位置に複数の熱伝導用スル
ーホールを設け、これらのスルーホールにアルミニウム
材をそれぞれ充填すれば、第1金属層の熱がアルミニウ
ム材を通ってよりスムーズに第2金属層又はフィン本体
に伝わる。
Further, even after the semiconductor chip is mounted on the ceramic circuit board, the radiating fins can be bonded to the ceramic circuit board without melting and peeling the soldered portion of the semiconductor chip or the ceramic circuit board. Further, by providing a plurality of through holes for heat conduction at positions facing the chips on the ceramic substrate, and filling these through holes with aluminum material, heat of the first metal layer can pass through the aluminum material more smoothly through the second material. that Tsutawa the metal layer or the fin body.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明第1実施例の放熱フィンを含むセラミッ
ク回路基板の断面図。
FIG. 1 is a cross-sectional view of a ceramic circuit board including a radiation fin according to a first embodiment of the present invention.

【図2】図1のA矢視図。FIG. 2 is a view taken in the direction of arrow A in FIG.

【図3】本発明の第2実施例を示す図1に対応する断面
図。
FIG. 3 is a sectional view showing a second embodiment of the present invention and corresponding to FIG. 1;

【図4】本発明の第3実施例を示すフィン本体の断面
図。
FIG. 4 is a sectional view of a fin body showing a third embodiment of the present invention.

【図5】本発明の第4実施例を示す図4に対応する断面
図。
FIG. 5 is a sectional view showing a fourth embodiment of the present invention and corresponding to FIG. 4;

【図6】本発明の第5実施例を示す図1に対応する断面
図。
FIG. 6 is a sectional view showing a fifth embodiment of the present invention and corresponding to FIG. 1;

【図7】本発明の第6実施例を示す図1に対応する断面
図。
FIG. 7 is a sectional view showing a sixth embodiment of the present invention and corresponding to FIG. 1;

【符号の説明】[Explanation of symbols]

11,79,99 放熱フィン 12 シリコン半導体チップ 13 薄膜多層セラミック回路基板 18 セラミック基板 19 フィン本体 21 第1金属層 22 第2金属層 111 熱伝導用スルーホール 112 アルミニウム材 11, 79, 99 Heat radiation fins 12 Silicon semiconductor chip 13 Thin film multilayer ceramic circuit board 18 Ceramic substrate 19 Fin body 21 First metal layer 22 Second metal layer 111 Through hole for heat conduction 112 Aluminum material

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平4−363052(JP,A) 特開 昭57−138198(JP,A) 特開 昭62−287649(JP,A) 特開 平5−41471(JP,A) 特開 平6−188329(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 23/36 H05K 7/20 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-363052 (JP, A) JP-A-57-138198 (JP, A) JP-A-62-287649 (JP, A) JP-A-5-138649 41471 (JP, A) JP-A-6-188329 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 23/36 H05K 7/20

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 セラミック回路基板(13)に実装したチッ
プ(12)の外面にはんだ又は接着剤を介して直接接着され
る放熱フィン(11)であって、 前記チップ(12)の外面を被覆可能な面積を有するアルミ
ニウム材からなる第1金属層(21)と、前記第1金属層(2
1)を被覆可能な面積を有するセラミック基板(18)と、前
記セラミック基板(18)を被覆可能な面積を有するアルミ
ニウム材からなる第2金属層(22)と、前記第2金属層(2
2)を被覆可能な面積を有するアルミニウム材からなるフ
ィン本体(19)とがそれぞれAl系ろう材を介してこの順
に積層接着されたことを特徴とする放熱フィン。
A radiating fin (11) directly bonded to an outer surface of a chip (12) mounted on a ceramic circuit board (13) via solder or an adhesive, and covering the outer surface of the chip (12). A first metal layer (21) made of an aluminum material having a possible area;
1) a ceramic substrate (18) having an area capable of covering the ceramic substrate (18), a second metal layer (22) made of an aluminum material having an area capable of covering the ceramic substrate (18), and a second metal layer (2).
A radiating fin characterized in that a fin body (19) made of an aluminum material having an area capable of covering 2) is laminated and bonded in this order via an Al-based brazing material.
【請求項2】 セラミック回路基板に実装したチップの
外面にはんだ又は接着剤を介して直接接着される放熱フ
ンであって、 前記チップの外面を被覆可能な面積を有するアルミニウ
ム材からなる第1金属層と、前記第1金属層を被覆可能
な面積を有するセラミック基板と、前記セラミック基
被覆可能な面積を有するアルミニウム材からなるフィ
ン本体とがそれぞれAl系ろう材を介してこの順に積層
接着されたことを特徴とする放熱フィン。
2. A radiator off <br/> fin that is bonded directly via a solder or adhesive <br/> outer surface of the chip mounted on the ceramic circuit board, the outer surface of the chip a first metal layer made of aluminum material having a coatable surface area, a ceramic board having an area capable of covering the first metal layer, wherein the ceramic base plate
Radiating fins, characterized in that the fins present made of an aluminum material having an area capable coating are laminated and bonded in this order via the Al based brazing material, respectively.
【請求項3】 セラミック基板のチップに対向する位置
に複数の熱伝導用スルーホールが設けられ、前記複数の
熱伝導用スルーホールにアルミニウム材がそれぞれ充填
された請求項1又は2記載の放熱フィン。
3. A plurality of heat conduction Suruho Le at a position opposite to the chip of the ceramic base plate is provided, the aluminum material to the plurality of heat conduction Suruho Le is filled according to claim 1, wherein each Radiation fins.
【請求項4】 表面にチップ(12)を実装したセラミック4. A ceramic having a chip (12) mounted on its surface.
回路基板(13)の裏面にはんだ又は接着剤を介して直接接Direct connection to the back of the circuit board (13) via solder or adhesive
着される放熱フィン(11)であって、Radiation fins (11) to be worn, 前記セラミック回路基板(13)の裏面を被覆可能な面積をThe area that can cover the back surface of the ceramic circuit board (13) is
有するアルミニウム材からなる第1金属層(21)と、前記A first metal layer (21) made of an aluminum material,
第1金属層(21)を被覆可能な面積を有するセラミック基A ceramic base having an area capable of covering the first metal layer (21);
板(18)と、前記セラミック基板(18)を被覆可能な面積をPlate (18) and the area that can cover the ceramic substrate (18)
有するアルミニウム材からなる第2金属層(22)と、前記A second metal layer (22) made of an aluminum material having
第2金属層(22)を被覆可能な面積を有するアルミニウムAluminum having an area capable of covering the second metal layer (22)
材からなるフィン本体(19)とがそれぞれAl系ろう材をThe fin body (19) made of a brazing material
介してこの順に積層接着され、Laminated in this order via 前記セラミック基板(18)の前記チップ(12)に対向する位A position of the ceramic substrate (18) facing the chip (12).
置に複数の熱伝導用スルーホール(111)が設けられ、前Multiple through holes (111) for heat conduction
記複数の熱伝導用スルーホール(111)にアルミニThe aluminum through holes for multiple heat conduction holes (111) ウム材Um material
(112)がそれぞれ充填されたことを特徴とする放熱フィ(112)
ン。N.
【請求項5】 表面にチップを実装したセラミック回路5. A ceramic circuit having a chip mounted on its surface.
基板の裏面にはんだ又は接着剤を介して直接接着されるDirectly bonded to the back of the board via solder or adhesive
放熱フィンであって、Radiation fins, 前記セラミック回路基板の裏面を被覆可能な面積を有すIt has an area that can cover the back surface of the ceramic circuit board
るアルミニウム材からなる第1金属層と、前記第1金属A first metal layer made of an aluminum material, and the first metal
層を被覆可能な面積を有するセラミック基板と、前記セA ceramic substrate having an area capable of covering the layer;
ラミック基板を被覆可能な面積を有するアルミニウム材Aluminum material with an area that can cover the lamic substrate
からなるフィン本体とがそれぞれAl系ろう材を介してAnd the fin body consisting of
この順に積層接着され、Laminated and bonded in this order, 前記セラミック基板の前記チップに対向する位置に複数A plurality of ceramic substrates are provided at positions facing the chips.
の熱伝導用スルーホールが設けられ、前記複数の熱伝導A plurality of through holes for heat conduction are provided;
用スルーホールにアルミニウム材がそれぞれ充填されたAluminum material was filled in through holes for
ことを特徴とする放熱フィン。A radiation fin characterized by the above.
【請求項6】 第2金属層(22)の厚さが第1金属層(21)
の厚さの2/3以下である請求項1、3又は4いずれか
記載の放熱フィン。
6. The thickness of the second metal layer (22) is equal to that of the first metal layer (21).
The heat radiation fin according to claim 1 , wherein the thickness of the heat radiation fin is not more than / of the thickness of the heat radiation fin.
【請求項7】 フィン本体(99)が凸条(99a)を有するコ
ルゲートフィンであって、前記フィン本体(99)が前記凸
条(99a)に直交する方向に切断することにより複数分割
された請求項1ないし6いずれか記載の放熱フィン。
7. The fin body (99) is a corrugated fin having a ridge (99a), and the fin body (99) is divided into a plurality by cutting in a direction orthogonal to the ridge (99a). A heat radiation fin according to any one of claims 1 to 6.
JP16372594A 1994-07-15 1994-07-15 Radiation fin Expired - Fee Related JP3139523B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16372594A JP3139523B2 (en) 1994-07-15 1994-07-15 Radiation fin

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16372594A JP3139523B2 (en) 1994-07-15 1994-07-15 Radiation fin

Publications (2)

Publication Number Publication Date
JPH0831990A JPH0831990A (en) 1996-02-02
JP3139523B2 true JP3139523B2 (en) 2001-03-05

Family

ID=15779484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16372594A Expired - Fee Related JP3139523B2 (en) 1994-07-15 1994-07-15 Radiation fin

Country Status (1)

Country Link
JP (1) JP3139523B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006004961A (en) * 2004-06-15 2006-01-05 Hitachi Ltd Semiconductor module
WO2008078788A1 (en) * 2006-12-26 2008-07-03 Kyocera Corporation Heat dissipating substrate and electronic device using the same
JP2008288411A (en) * 2007-05-18 2008-11-27 Calsonic Kansei Corp Heat dissipator
JP4692908B2 (en) * 2008-04-14 2011-06-01 電気化学工業株式会社 Module structure
JP2013115202A (en) * 2011-11-28 2013-06-10 Toyota Industries Corp Semiconductor device
WO2023149774A1 (en) * 2022-02-07 2023-08-10 주식회사 아모그린텍 Ceramic substrate unit and manufacturing method therefor
KR20230126340A (en) * 2022-02-23 2023-08-30 주식회사 아모그린텍 Ceramic substrate unit and manufacturing method thereof

Also Published As

Publication number Publication date
JPH0831990A (en) 1996-02-02

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