JP3105396B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor having crystallinity,
In particular, the present invention relates to a thin film silicon semiconductor, a semiconductor device using the same, and a method for manufacturing them.

[0002]

2. Description of the Related Art Thin film transistors used as thin film devices are broadly classified into two types: a planar type and a stagger type. Among them, a staggered thin film transistor (TFT) is manufactured as follows. First, an N-type or P-type amorphous silicon region 41 serving as a source / drain region is formed. (FIG. 4 (A))

Then, the intrinsic amorphous silicon layer 42 serving as a channel formation region is formed by a plasma CVD method or a low pressure C
The film is formed by means such as a VD method, a photo CVD method, and a sputtering method. The thickness of the intrinsic amorphous silicon layer 42 is set to 1000 ° or more, preferably 1500 ° or more in order to obtain good crystals. (FIG. 4 (B))

Then, a crystalline silicon film 43 is obtained by performing a solid phase growth method (thermal annealing method). The conditions for the solid phase growth method were generally at 600 to 750 ° C. for 24 to 72 hours. (FIG. 4C) Thereafter, a gate insulating film 44 is formed to a thickness of several thousand Å by a sputtering method, a plasma CVD method, or the like.
The crystalline silicon film 43 and the gate insulating film 44 are etched to make contact holes in the source / drain regions 41. (FIG. 4 (D))

After that, the metal electrodes 45a,
45b and 45c are formed. Here, 45a and 45c are source / drain electrodes, and 45b is a gate electrode. Thus, a TFT is manufactured. (FIG. 4 (D))

[0006]

Conventionally, in the above-described process, the solid phase growth method requires a long-time thermal annealing at a temperature of at least 600 ° C. for 12 hours or more.
There was a problem that an expensive quartz substrate had to be used and the cost was high. In addition, since thermal annealing is performed at a high temperature, there is a problem that n ⁺ or p ⁺ diffuses into a channel from an N-type or P-type amorphous silicon region serving as a source / drain region. In addition, during crystallization, the crystal growth direction is random, so that the crystalline direction of the crystalline silicon semiconductor thin film serving as a channel formation region is varied, which causes a problem that TFT characteristics are deteriorated.

[0007]

SUMMARY OF THE INVENTION According to the present invention, a crystallization temperature of normal amorphous silicon is increased by adding a layer containing a catalytic element such as nickel to promote crystallization of amorphous silicon to an amorphous silicon film. The object of the present invention is to solve the above-mentioned problem by utilizing the fact that a crystalline silicon semiconductor thin film can be obtained by thermal annealing at a low temperature for a short time. The present inventors have found that crystallization is promoted by adding a small amount of nickel to an amorphous silicon film. It is presumed that the crystallization easily proceeds by the amorphous silicon and nickel being easily combined to form nickel silicide, which reacts with the adjacent amorphous silicon as follows.

Amorphous silicon (silicon A) + nickel silicide (silicon B) → nickel silicide (silicon A) + crystalline silicon (silicon B) (silicon A and silicon B indicate the position of silicon) Shows that the process proceeds while converting amorphous silicon into crystalline silicon. Actually, the reaction starts below 580 ° C.
It is clear that the reaction is observed even at 0 ° C.
As a result of this reaction, 1 × 10 ¹⁶ / c is contained in silicon.
m ³ or more of nickel remained.

[0009] This also means that crystallization proceeds in one direction, that is, that the direction of crystallization can be controlled. In particular, when the movement of nickel occurs in the lateral direction, the crystallization proceeds in the lateral direction (this is called a lateral growth process of a nickel-added low-temperature crystallization process). Elements that promote the crystallization of amorphous silicon include nickel (Ni),
Group 8 elements iron (Fe), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (P
d), osmium (Os), iridium (Ir), platinum (Pt), and 3d element scandium (Sc);
Vanadium (V), manganese (Mn), copper (Cu), zinc (Zn), gold (Au), and silver (Ag) can also be used. The present invention utilizes the characteristic of crystallization by the addition of an element that promotes the crystallization of amorphous silicon (hereinafter referred to as a catalyst element) as described above to reduce the thermal annealing temperature, which is a problem in the conventional method. And control of the crystallization direction at the same time.

In the present invention, in order to align the crystallographic direction of the crystalline silicon semiconductor thin film serving as a channel forming region, a layer of a catalytic element or a catalytic element compound (below or above an amorphous silicon region serving as a source / drain region). A catalyst element-containing layer), and the catalyst element contains a source /
The crystallization is performed in the direction from the source / drain to the channel by proceeding from the drain to the channel. Since the current of the TFT flows from the source to the drain (or vice versa), crystallization in the above-described direction is effective in improving the characteristics of the TFT.

In general, it has been found that the thinner the channel forming region, the better the characteristics can be obtained.
In the conventional solid-phase growth method, in order to obtain a good crystalline silicon film, it is necessary to reduce the influence of the interface, so that the thickness of the silicon film needs to be at least 1000 ° or more, preferably 1500 ° or more. This has been a factor limiting the characteristics of the thin film transistor. However, when the catalyst element is added as described above, 300 to 10
It has been found that a thin amorphous silicon film as thin as 00 ° also crystallizes. Therefore, by adding a catalytic element, the thickness of the channel formation region of the thin film transistor can be reduced, so that characteristics can be improved.

In the first aspect of the present invention, the above object is achieved through the following steps. First, a catalytic element or catalytic element compound layer (catalytic element-containing layer) is formed on a substrate. Under the catalytic element-containing layer, a coating of an appropriate metal material may be formed. Such a coating is effective in improving the source / drain conductivity later. As the metal material to be used at this time, a material that does not react with silicon in a subsequent thermal annealing step and has excellent heat resistance is desirable. For example, tungsten (W), molybdenum (Mo), titanium (Ti), chromium (Cr) ) Is desirable. (Step 1-
1) After forming the catalyst element-containing layer, N-type or P-type amorphous silicon to which impurities are added is formed to a thickness of several hundreds to several thousand に よ っ て by a chemical vapor deposition method. Alternatively, an amorphous silicon film is formed by sputtering or plasma C.
N-type or P-type amorphous silicon may be formed by forming a film by a VD method or the like and then adding an impurity by an ion doping method. (Step 1-
2)

In this state, patterning, etching of the amorphous silicon film and the catalytic element layer are performed,
An N-type or P-type amorphous silicon region serving as a drain region is formed. Below the N-type or P-type amorphous silicon region is a catalytic element-containing layer, whose shape is substantially the same as that of the source / drain regions. In the case where a film of an appropriate metal material is formed under the catalytic element-containing layer in step 1-1, the film is also etched at the same time, and the shape is substantially the same as that of the source / drain regions. I do. (Step 1-3) Next, an intrinsic amorphous silicon layer serving as a channel formation region is formed by plasma CVD or LPCVD to a thickness of 500 nm.
A film is formed to a thickness of about 1000 °. (Step 1-4)

And, at 400-580 ° C., preferably
Thermal annealing is performed at 450 to 550 ° C. By this step, nickel diffuses from the catalytic element-containing layer into the intrinsic amorphous silicon layer and the source / drain regions and crystallizes. In particular, in the intrinsic amorphous silicon layer, where it is sandwiched between the source / drain regions (this portion will later become a channel of the TFT), crystallization proceeds in the direction of the source / drain current. In this way,
The crystallization of the channel region and the source / drain region is performed. (Step 1-5)

In the above step 1-1, in order to form a catalyst element-containing layer, a method of applying a solution containing the catalyst element and then drying it (for example, a spin coating method or a dipping method), A method of forming a film of an elemental compound by a sputtering method, or
A method of decomposing and depositing gaseous organic nickel by heat, light, or plasma (gas phase growth method) may be used. In any method, the thickness of the layer may be determined according to the required amount of the catalytic element. In general, the allowable concentration of nickel in a silicon film is 1 × 10 ¹⁹ atoms / cm ³ or less, so that the thickness of the catalyst element or the catalyst element compound layer is extremely small. Therefore, it may not actually be in the form of a film.

When the catalyst element or the catalyst element compound layer is deposited by a sputtering method, a catalyst element silicide may be used as a material of the sputtering target in addition to the catalyst element alone. Among the methods for forming the catalyst element or the catalyst element compound layer, with respect to the method of applying and drying a solution, an aqueous solution, an organic solvent solution, or the like may be used as the solution. Here, “containing” includes both the meaning of being included as a compound and the meaning of being included simply by being dispersed.

When the solvent used is selected from polar solvents such as water, alcohol, acid and ammonia,
As the catalyst element compound to be a solute, typically, bromide, acetate, oxalate, carbonate, iodide, nitrate, sulfate, formate, acetylacetonate compound of the catalyst element,
Those selected from 4-cyclohexyl butyrate, oxides and hydroxides are used.

When a non-polar solvent selected from benzene, toluene, xylene, carbon tetrachloride, chloroform and ether is used, the catalyst element compound is typically acetylacetonate, a catalyst element. 2─
Those selected from ethylhexanoates can be used. Of course, other solvents and solutes may be used.

It is also useful to add a surfactant to the solution containing the catalyst element. This is to increase the adhesion to the surface to be coated and control the adsorption. This surfactant may be applied in advance on the surface to be coated.

The above is an example in which a solution in which the catalytic element is completely dissolved is used. However, even if the catalytic element is not completely dissolved, the powder composed of the catalytic element alone or the compound of the catalytic element is dispersed in the dispersion medium. A material such as an emulsion which is uniformly dispersed in the emulsion may be used. The amount of the catalyst element contained in the solution depends on the type of the solution, but as a general tendency, the amount of the catalyst element is 200 ppm to 1 pp relative to the solution.
m, preferably 50 ppm to 1 ppm (in terms of weight). This is a value determined in view of the concentration of the catalyst element in the film after the crystallization and the resistance to hydrofluoric acid.

In the above step 1-5, after thermal annealing, to improve the crystallinity of the crystalline silicon,
A laser or an equivalent strong light may be irradiated. As a laser used at this time, an ultraviolet laser such as various excimer lasers, Nd: YAG
Laser, Nd: infrared rays such as glass laser and ruby laser. Visible light lasers are preferred. Both are preferably pulse lasers. Further, the above step 1-
5, a gate insulating film is formed before thermal annealing;
Thereafter, thermal annealing may be performed.

The second aspect of the present invention has the following configuration. First, N-type or P-type amorphous silicon to which impurities are added is formed to a thickness of several hundred to several thousand Å by a chemical vapor deposition method. Alternatively, N-type or P-type amorphous silicon may be formed by forming an amorphous silicon film by a sputtering method, a plasma CVD method, or the like, and then adding an impurity by an ion doping method. Further, a film of an appropriate metal material may be formed under the N-type or P-type amorphous silicon film. Such a coating is effective in improving the source / drain conductivity later. As the metal material to be used at this time, a material that does not react with silicon in a subsequent thermal annealing step and has excellent heat resistance is desirable. For example, tungsten (W), molybdenum (Mo), titanium (Ti), chromium (Cr) ) Is desirable. (Step 2-1)

Thereafter, a catalytic element or catalytic element compound layer (catalytic element-containing layer) is formed on the N-type or P-type amorphous silicon film. Here, when using a spin coating method, a dipping method, or the like to form the catalyst element-containing layer, when a polar solvent such as water is used as a solution solvent and directly applied to the amorphous silicon film, the solution is repelled. It cannot be applied uniformly. In such a case, a thin oxide film having a thickness of 100 ° or less is first formed, and a solution containing a catalyst element is applied thereon, whereby the solution can be applied uniformly. It is also effective to improve the wetting by adding a material such as a surfactant to the solution.

By using a non-polar solvent such as a toluene solution of nickel 2-ethylhexanoate as a solution, it can be directly applied to an amorphous silicon film. In this case, it is effective to apply a material such as an adhesive used in applying the resist in advance. However, care must be taken when the amount of coating is too large, since this would hinder the addition of the catalytic element into the amorphous silicon. (Step 2-2)

In this state, patterning, etching of the amorphous silicon film and the catalytic element layer are performed,
An N-type or P-type amorphous silicon region serving as a drain region is formed. A catalyst element-containing layer is provided on the N-type or P-type amorphous silicon region, and its shape is substantially the same as that of the source / drain region. In the case where a film of a metal material is formed under the N-type or P-type amorphous silicon region, this film is also etched at the same time to make the shape substantially the same as the source / drain regions. (Step 2-3) Next, an intrinsic amorphous silicon layer serving as a channel formation region is formed by a plasma CVD method or an LPCVD method to a thickness of 500 nm.
A film is formed to a thickness of about 1000 °. (Step 2-4)

And, at 400-580 ° C., preferably,
Thermal annealing is performed at 450 to 550 ° C. By this step, nickel diffuses from the catalytic element-containing layer into the intrinsic amorphous silicon layer and the source / drain regions and crystallizes. In particular, in the intrinsic amorphous silicon layer, where it is sandwiched between the source / drain regions (this portion will later become a channel of the TFT), crystallization proceeds in the direction of the source / drain current. In this way,
The crystallization of the channel region and the source / drain region is performed. Also in this case, a gate insulating film may be formed before thermal annealing, and then thermal annealing may be performed. Further, after the thermal annealing, a laser or a strong light equivalent thereto may be irradiated to further improve the crystallization. (Step 2-5)

The third aspect of the present invention has the following configuration. First, N-type or P-type amorphous silicon to which impurities are added is formed to a thickness of several hundred to several thousand Å by a chemical vapor deposition method. Alternatively, N-type or P-type amorphous silicon may be formed by forming an amorphous silicon film by a sputtering method, a plasma CVD method, or the like, and then adding an impurity by an ion doping method. Further, a film of an appropriate metal material may be formed under the N-type or P-type amorphous silicon film. Such a coating is effective in improving the source / drain conductivity later. As the metal material to be used at this time, a material that does not react with silicon in a subsequent thermal annealing step and has excellent heat resistance is desirable. For example, tungsten (W), molybdenum (Mo), titanium (Ti), chromium (Cr) ) Is desirable. (Step 3-1) Thereafter, the amorphous silicon film is etched,
An N-type or P-type amorphous silicon region serving as a source / drain region is formed. When a film of a metal material is formed under the N-type or P-type amorphous silicon region, this film is also etched at the same time to make the shape substantially the same as that of the source / drain regions. (Step 3-2)

Next, an intrinsic amorphous silicon layer serving as a channel formation region is formed to a thickness of 500 to 1000 ° by a plasma CVD method or an LPCVD method. (Step 3-3) Further, an insulating film serving as a gate insulating film is formed, and this is etched to form a contact hole for the source / drain region. (Step 3-4) After that, a catalyst element or a catalyst element compound layer (catalyst element-containing layer) is formed on the entire surface. You will be in direct contact. (Step 3-
5)

Then, at 400 to 580 ° C., preferably,
Thermal annealing is performed at 450 to 550 ° C. By this step, the catalyst element is first diffused from the catalyst element-containing layer into the source / drain regions, and this region is crystallized. Next, the catalyst element diffuses into the intrinsic amorphous silicon layer,
This part crystallizes. As in the first and second embodiments of the present invention, when the intrinsic amorphous silicon layer is sandwiched between the source / drain regions (this portion will later become a channel of the TFT), the crystal is oriented in the direction of the source / drain current. Progress. Thus, crystallization of the channel region and the source / drain regions is performed. Also in this case, crystallization may be further improved by irradiating a laser or an equivalent strong light after the thermal annealing.
(Step 3-6)

[0030]

【Example】

[Embodiment 1] This embodiment uses nickel as a catalyst element, and is a staggered thin film transistor (TFT).
This is an example in which a lateral growth process of a nickel-added low-temperature crystallization process is used in a step of crystallizing a semiconductor layer to be a channel formation region when fabricating the semiconductor device. In this embodiment, Corning 7059 glass is used as the substrate. The size is 100 mm × 100 mm.

First, a few to several tens of nickel-containing layer is formed on a glass substrate 1. In order to form a layer containing nickel, a method of applying a solution containing nickel and then drying (for example, a spin coating method or a dipping method), a method of forming a film of nickel or a nickel compound by a sputtering method, or Alternatively, it may be formed by a method of decomposing and depositing gaseous organic nickel by heat, light or plasma (gas phase growth method). Here, a nickel layer is formed by sputtering to a thickness of 20 °.
To a film thickness of At this time, since the thickness of the nickel or nickel compound layer is extremely small, it may not actually be a film.

Thereafter, N-type or P-type amorphous silicon to which impurities are added is formed in a thickness of several hundreds of .mu.m to 1 .mu.m by chemical vapor deposition. Here, PH ₃ , S
N by plasma CVD using iH ₄ and H ₂ mixed gas
A type amorphous silicon film is formed to a thickness of 3000 °. In this state, patterning is performed, the amorphous silicon film and the nickel layer are etched, and an N-type amorphous silicon region serving as the source / drain region 3 is formed. The nickel region 2 is located below the N-type amorphous silicon region. (Fig. 1 (A))

Next, an intrinsic amorphous silicon layer 4 serving as a channel forming region is formed to a thickness of 300 to 1000 ° by a plasma CVD method or an LPCVD method. In this embodiment, the film is formed to a thickness of 500 ° by the plasma CVD method. In this state, the N-type amorphous silicon region 3 which is a semiconductor layer serving as a source / drain region is entirely covered with the amorphous silicon layer 4. (Figure 1
(B))

Next, dehydration is performed at 450 ° C. for 1 hour, followed by thermal annealing at 550 ° C. for 4 hours.
As a result, nickel diffuses into the amorphous silicon layer 4 and the source / drain regions 3 and crystallizes. In particular,
Where the amorphous silicon layer 4 is sandwiched between the source / drain regions 3 (this portion will later become a channel of the TFT), crystallization proceeds in the lateral direction. Thus, the crystalline silicon film 5 is obtained.

After this step, a gate insulating film is formed to a thickness of several hundreds to several thousand degrees by a sputtering method, a plasma CVD method, or the like. In this embodiment, a silicon oxide film 6 is formed to a thickness of 1000 ° by a plasma CVD method. Further, a contact hole is opened in the source / drain region 3. (FIG. 1 (C)) Thereafter, an Al film is deposited at 7000 ° by a sputtering method and etched to form Al electrodes 7a, 7b and 7c. Here, 7a and 7c are source / drain electrodes, and 7b is a gate electrode. Thus, a TFT is manufactured. (Figure 1
(D))

[Embodiment 2] In this embodiment, nickel is used as a catalyst element, and amorphous silicon is crystallized by thermal annealing in the same manner as in Embodiment 1, and then laser annealing is further performed. This is an example for further improving the characteristics. In this case, although the number of laser irradiation steps is increased as compared with Example 1, there is an advantage that the performance (in particular, mobility, threshold voltage, and sub-threshold characteristics) of the manufactured TFT is improved.

In the present embodiment, Corning 7059 glass is used as the substrate as in the first embodiment. The size is 100 mm × 100 mm. First, a nickel compound film is formed on a glass substrate 21 to a thickness of 20 ° by a spin coating method. In this embodiment, a nickel acetate layer is formed. This is produced as follows. First, an acetate solution is prepared by adding nickel to the acetate solution. The concentration of nickel is 25 ppm. Then, 2 ml of this acetate solution is dropped on the surface of the rotated substrate, and this state is maintained for 5 minutes to spread the nickel acetate solution uniformly over the substrate. Thereafter, the number of rotations of the substrate is increased and spin dry (2000 rpm, 60
Seconds).

The nickel concentration in the acetate solution is 1
If it is at least ppm, it will be practical. By performing this nickel solution application step once to a plurality of times, a nickel acetate layer having an average thickness of 20 ° can be formed on the surface of the amorphous silicon film after spin drying. The same can be done using other nickel compounds. Then, the N-type amorphous silicon film to which
A film is formed to a thickness of 2000 ° by a plasma CVD method using a mixed gas of H ₃ , SiH ₄ and H ₂ .

In this state, patterning and etching are performed to etch the amorphous silicon film and the nickel layer, thereby forming an N-type amorphous silicon region serving as the source / drain region 23. Below the N-type amorphous silicon region, there is a region (nickel region) 22 made of a nickel acetate layer. (Fig. 2 (A))

Next, the intrinsic amorphous silicon layer 24 serving as a channel formation region is formed by plasma CVD.
The film is formed to a thickness of 0 °. In this state, the entire surface of the N-type amorphous silicon region 23 which is a semiconductor layer serving as a source / drain region is covered with the amorphous silicon layer 24. (FIG. 2 (B))

Next, dehydration is performed at 450 ° C. for 1 hour, followed by thermal annealing at 550 ° C. for 4 hours.
As a result, nickel diffuses into the amorphous silicon layer 24 and the source / drain regions 23 and crystallizes. In particular, a portion sandwiched between the source / drain regions 23 in the amorphous silicon layer 24 (this portion will be
In this case, crystallization proceeds in the lateral direction.
Thus, the crystalline silicon film 25 is obtained.

Thereafter, a silicon film 25 having better crystallinity can be obtained by performing laser annealing. As a laser used at this time, an ultraviolet laser such as various excimer lasers, Nd: YAG
Laser, Nd: infrared rays such as glass laser and ruby laser. Visible light lasers are preferred. Both are preferably pulse lasers. In this embodiment, KrF
Excimer laser (wavelength 248 nm, pulse width 30 ns
ec) is irradiated in the air at a power density of 200 to 350 mJ / cm ² for 1 to 50 shots, preferably 1 to 10 shots, to further improve the crystallinity of the silicon layer.
(Fig. 2 (C))

The reason that the performance of the TFT is improved by performing such laser irradiation is that a portion of the amorphous silicon component remains in the crystalline silicon only by thermal annealing.
It is considered that the residual component is crystallized by performing the laser annealing. After this step, a silicon oxide film 26 is formed as a gate insulating film to a thickness of 1000 ° by a plasma CVD method. After contact hole opening and patterning (Fig. 2
(D)) The Al electrodes 27a to 27c are formed to complete the TFT. (FIG. 2 (E))

[Embodiment 3] This embodiment shows a case where a CMOS type TFT is manufactured using nickel as a catalyst element. First, a nickel film 32 is formed to a thickness of 20 ° on a glass substrate 31 by a sputtering method, and further, an amorphous silicon film of 1500 ° is formed.
An amorphous silicon film is formed by a sputtering method, a plasma CVD method, or the like.

Next, an impurity is diffused into the amorphous silicon film thus obtained by ion doping to form an N-type impurity region 33a and a P-type impurity region 33b. At this time, for example, phosphorus (doping gas is PH ₃ ) is used as an N-type impurity,
Doping is performed on the entire surface at an acceleration voltage of kV, and then the region of the N-channel type TFT is covered with a photoresist, and a P-type impurity, for example, boron (doping gas is B ₂ H ₆ ) is used, and acceleration is performed at 10 to 30 kV. The entire surface may be doped with a voltage. At this time, the dose is, for example, 1 × 10 ¹⁵ phosphorus.
cm ⁻² , and boron is 4 × 10 ¹⁵ cm ⁻² . Area 33b
Is doped with both phosphorus and boron, but becomes a P-type since the dose of phosphorus is smaller than the dose of boron.
(FIG. 3 (A))

In this state, patterning is performed, and the amorphous silicon film and the nickel layer are etched to form N-type and P-type amorphous silicon regions serving as source / drain regions. Below the N-type and P-type amorphous silicon regions, there is a region (nickel region) composed of a nickel acetate layer. Next, an intrinsic amorphous silicon layer 34 serving as a channel formation region is formed to a thickness of 500 ° by a plasma CVD method. In this state, the N-type and P-type amorphous silicon layers, which are the semiconductor layers serving as the source / drain regions, are in a state where the entire surface is covered with the amorphous silicon layer. (FIG. 3 (B))

Next, dehydration is performed at 450 ° C. for 1 hour, followed by thermal annealing at 550 ° C. for 4 hours.
As a result, nickel diffuses into the amorphous silicon layer 34 and the source / drain regions and crystallizes. Thereafter, by performing laser annealing, a silicon film 35 having better crystallinity can be obtained, and the N-type and P-type amorphous silicon layers are activated. In this embodiment, an excimer laser is used. (FIG. 3
(C))

After this step, a silicon oxide film 36 as a gate insulating film is
Å thickness. Further, after patterning by opening contact holes (FIG. 3D), the Al electrodes 37a to
e, an N-channel TFT 38a and a P-channel TFT 38b are manufactured, and a TFT of a CMOS circuit is manufactured. (FIG. 3 (E))

Embodiment 4 In this embodiment, in a step of manufacturing a staggered thin film transistor (TFT) using nickel as a catalyst element, a semiconductor layer serving as a channel formation region is crystallized after forming a gate insulating film. It is an example. First, the glass substrate 51
A nickel compound layer is formed thereon by spin coating to a thickness of 20 °. After that, the N-type amorphous silicon film to which the impurities are added is made of PH ₃ , SiH ₄ , H ₂
A film is formed to a thickness of 3500 ° by a plasma CVD method using a mixed gas.

In this state, patterning and etching are performed to etch the amorphous silicon film and the nickel layer, thereby forming an N-type amorphous silicon region serving as the source / drain region 53. Below the N-type amorphous silicon region, there is a region (nickel region) 52 made of a nickel acetate layer. (FIG. 5 (A))

Next, the intrinsic amorphous silicon layer 54 serving as a channel formation region is formed by plasma CVD to a thickness of 50 nm.
The film is formed to a thickness of 0 °. In this state, the entire surface of the N-type amorphous silicon region 53 which is a semiconductor layer serving as a source / drain region is covered with the amorphous silicon layer 54. After this step, a gate insulating film is formed to a thickness of several thousand Å by a sputtering method, a plasma CVD method, or the like. In this embodiment, a silicon oxide film 56 is formed to a thickness of 1000 ° by a plasma CVD method. (FIG. 5 (B))

Next, dehydration is performed at 450 ° C. for 1 hour, followed by thermal annealing at 550 ° C. for 4 hours.
As a result, nickel diffuses into the amorphous silicon layer 54 and the source / drain regions 53 and crystallizes. In particular, a portion sandwiched between the source / drain regions 53 in the amorphous silicon layer 54 (this portion will be
In this case, crystallization proceeds in the lateral direction.
Thus, a crystalline silicon film 55 is obtained. (FIG. 5
(C))

Further, the silicon oxide film 56 and the crystalline silicon film 55 are etched to form a contact hole in the source / drain region 53. (FIG. 5D) Thereafter, an Al film is deposited at 7000 ° by a sputtering method, and etching is performed to form Al electrodes 57a, 57b, and 57c. Here, 57a and 57c are source / drain electrodes, 5
7b is a gate electrode. Thus, a TFT is manufactured. (FIG. 5E)

Embodiment 5 In this embodiment, nickel is used as a catalyst element. This embodiment is shown in FIG. First, N-type or P-type amorphous silicon to which an impurity is added is formed on a glass substrate 61 to a thickness of several hundred Å by a chemical vapor deposition method. Here, an N-type amorphous silicon film is formed to a thickness of 1500 ° by a plasma CVD method using a mixed gas of PH ₃ , SiH ₄ , and H ₂ .

Thereafter, a nickel layer of several to several tens of mm is formed. Here, a nickel layer is formed to a thickness of 20 ° on average by a sputtering method. At this time, since the thickness of the nickel layer is extremely thin, the nickel layer may not actually be formed into a film. After that, the amorphous silicon film and the nickel layer are etched to form an N-type amorphous silicon region serving as the source / drain region 63. Above the N-type amorphous silicon region is a nickel region 62. (FIG. 6 (A))

Next, the intrinsic amorphous silicon layer 64 serving as a channel formation region is formed by plasma CVD or LPCV.
The film is formed to a thickness of 300 to 1000 ° by Method D. In this embodiment, the film is formed to a thickness of 500 ° by the plasma CVD method. In this state, the N-type amorphous silicon region 63 which is a semiconductor layer serving as a source / drain region
Are entirely covered with an intrinsic amorphous silicon layer 64. (FIG. 6 (B))

Next, dehydration is performed at 450 ° C. for 1 hour, followed by thermal annealing at 530 ° C. for 8 hours.
As a result, nickel diffuses into the amorphous silicon layer 64 and the source / drain regions 63 and crystallizes. In particular, a portion sandwiched between the source / drain regions 63 in the amorphous silicon layer 64 (this portion will be
In this case, crystallization proceeds in the lateral direction.
Thus, a crystalline silicon film 65 is obtained.

After this step, a gate insulating film is formed to a thickness of several thousand Å by a sputtering method, a plasma CVD method or the like. In this embodiment, a silicon oxide film 66 is formed to a thickness of 1000 ° by a plasma CVD method. Further, a contact hole is formed in the source / drain region 63. (FIG. 6 (C))

Thereafter, the Al film was formed by sputtering at 7000 ° C.
After depositing and etching, the Al electrodes 67a, 67b, 6
7c is formed. Here, 67a and 67c are source / drain electrodes, and 67b is a gate electrode. Thus, a TFT is manufactured. (FIG. 6 (D))

Embodiment 6 In this embodiment, nickel is used as a catalyst element. This embodiment is shown in FIG. First, N-type or P-type amorphous silicon is formed on a glass substrate 71 by a chemical vapor deposition method to a thickness of several hundreds of square meters. Here, P
An N-type amorphous silicon film is formed to a thickness of 3000 ° by a plasma CVD method using a mixed gas of H ₃ , SiH ₄ and H ₂ .

Thereafter, patterning is performed in this state, and the amorphous silicon film is etched to form an N-type amorphous silicon region serving as the source / drain region 73. Next, an intrinsic amorphous silicon layer 74 serving as a channel formation region is formed to a thickness of 500 ° by a plasma CVD method. Subsequently, a silicon oxide film 76 is formed as a gate insulating film to a thickness of 1000 ° by a plasma CVD method. Form. (FIG. 7 (A))

Thereafter, the intrinsic amorphous silicon layer 74
Then, the silicon oxide film 76 is etched to form a contact hole in the source / drain region 73. (FIG. 7
(B)) Thereafter, a nickel-containing layer 72 of several to several tens of degrees is formed.
Here, the nickel layer is formed by sputtering to a thickness of 20 nm.
The film is formed to a thickness of Å. At this time, the nickel-containing layer is also deposited in the contact hole, and the nickel region 72 is formed on the N-type amorphous silicon region. (FIG. 7
(C))

Next, dehydration is performed at 450 ° C. for 1 hour, followed by thermal annealing at 550 ° C. for 8 hours.
As a result, nickel diffuses into the source / drain region 73 from the portion in contact with the source / drain region 73,
Then, the diffusion into the amorphous silicon layer 74 occurs, and these regions are crystallized. In particular, where the amorphous silicon layer 74 is sandwiched between the source / drain regions 73 (this portion will later become a channel of the TFT), crystallization proceeds in the lateral direction. Thus, a crystalline silicon film 75 is obtained. However, in the above thermal annealing step, the nickel film formed on the gate insulating film 76 is blocked by the gate insulating film and does not diffuse.
It remains as it is. After completion of the thermal annealing step, etching is performed using a hydrochloric acid-based etchant to remove nickel remaining on the gate insulating film. (FIG. 7 (D))

Then, the Al film is formed by sputtering at 7000 ° C.
After depositing and etching, the Al electrodes 77a, 77b, 7
7c is formed. Here, 77a and 77c are source / drain electrodes, and 67b is a gate electrode. Thus, a TFT is manufactured. (FIG. 7 (D))

[Embodiment 7] In this embodiment, nickel is used as a catalyst element. In order to improve the conductivity of the source / drain of a staggered thin film transistor (TFT), a titanium film is formed under the source / drain. Is formed. This embodiment is shown in FIG. First, a titanium film having a thickness of 500 ° is formed on a glass substrate 81 by a sputtering method. Then, several to several tens of nickel-containing layers are formed by the spin coating method described in the second embodiment.

Thereafter, an N-type amorphous silicon film is formed to a thickness of 1000 ° by a plasma CVD method.
In this state, patterning is performed, and the amorphous silicon film, the nickel-containing layer, and the titanium film are etched to form an N-type amorphous silicon region serving as the source / drain region 83. Below the N-type amorphous silicon region is a nickel-containing region 82, and further below is a titanium region 80. (FIG. 8A)

Next, the intrinsic amorphous silicon layer 84 serving as a channel formation region is formed by plasma CVD or LPCVD.
The film is formed to a thickness of 300 to 1000 ° by the method. In this embodiment, the film is formed to a thickness of 500 ° by the plasma CVD method. In this state, an N-type amorphous silicon region 83 which is a semiconductor layer to be a source / drain region
Are entirely covered with an amorphous silicon layer 84. (FIG. 1 (B))

Next, dehydration is performed at 450 ° C. for 1 hour, followed by thermal annealing at 550 ° C. for 4 hours.
As a result, nickel diffuses into the amorphous silicon layer 4 and the source / drain regions 83 and crystallizes. In particular, in a portion sandwiched between the source / drain regions 3 in the amorphous silicon layer 84 (this portion will later become a channel of the TFT), crystallization proceeds in the lateral direction. Thus, a crystalline silicon film 85 is obtained.

After this step, a silicon oxide film 86 is formed to a thickness of 1000 ° by a plasma CVD method. Further, a contact hole is opened in the source / drain region 3. At this time, the contact holes are different from those of the other embodiments in that the silicon oxide film 84 and the intrinsic silicon film 85 are formed.
In addition, etching is performed up to the N-type silicon region (source / drain region) 83. (FIG. 1 (C)) Thereafter, an Al film is deposited at 7000 ° by a sputtering method and etched to form Al electrodes 7a, 7b and 7c. Here, 7a and 7c are source / drain electrodes, and 7b is a gate electrode. Thus, a TFT is manufactured. (Figure 1
(D))

This embodiment is different from the other embodiments in the step of forming a contact hole. In another embodiment, it is necessary to stop the etching near the boundary between the intrinsic silicon film and the source / drain regions. Since the intrinsic silicon and the source / drain regions are made of the same material, it is very difficult to stop the etching at the boundary. Therefore, it is necessary to increase the etching margin by increasing the thickness of the source / drain regions. Also, for the purpose of increasing the conductivity of the source / drain regions, it is necessary to increase the thickness of the source / drain regions.

On the other hand, in this embodiment, the titanium region 8
The etching is stopped at the boundary between 0 and the source / drain region 83. Since titanium and the source / drain are dissimilar materials, the etching selectivity is high, and therefore, it is not necessary to provide a large margin for the etching. That is, both the titanium region and the source / drain region can be made thin. As a result, the step coverage of the intrinsic silicon film can be improved. Further, since titanium has high conductivity, even if the source / drain regions are thinned, the function of the element is not hindered. It is effective to provide a highly conductive metal film below the source / drain regions as in this embodiment.

[0072]

As described above, the present invention is epoch-making in that it promotes lowering the temperature and shortening the time of crystallization of amorphous silicon, and also aims to reduce the thickness of the channel region. Since the equipment, devices and methods for this are very common and excellent in mass productivity, the benefits brought to the industry are inevitable. In the embodiment, an example in which nickel is used as a catalyst element is shown. However, the same effect as that of the embodiment, although there is a difference in magnitude, other catalyst elements,
Iron (Fe), cobalt (Co), ruthenium (Ru),
Rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), scandium (Sc), titanium (Ti), vanadium (V),
It will be obvious that chromium (Cr), manganese (Mn), copper (Cu), zinc (Zn), gold (Au) and silver (Ag) can be used. Thus, the present invention is industrially useful and deserves a patent.

[Brief description of the drawings]

FIG. 1 shows a cross-sectional view of a process of an embodiment. (Example 1
reference)

FIG. 2 shows a cross-sectional view of a process of the embodiment. (Example 2
reference)

FIG. 3 shows a cross-sectional view of a process of the embodiment. (Example 3
reference)

FIG. 4 shows a conventional process.

FIG. 5 shows a cross-sectional view of the process of the embodiment. (Example 4
reference)

FIG. 6 shows a cross-sectional view of a process in the example. (Example 5
reference)

FIG. 7 shows a cross-sectional view of a step in the example. (Example 6
reference)

FIG. 8 shows a cross-sectional view of the process of the example. (Example 7
reference)

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Glass substrate 2 ... Nickel containing area 3 ... Source / drain area 4 ... Intrinsic amorphous silicon layer 5 ... Crystalline silicon layer 6 ... Silicon oxide film 7a: source / drain electrode 7b: gate electrode 7c: source / drain electrode

Continuation of the front page (56) References JP-A-2-128432 (JP, A) JP-A-2-84772 (JP, A) JP-A-2-222546 (JP, A) (58) Fields investigated (Int) .Cl. ⁷ , DB name) H01L 29/786 H01L 21/20 H01L 21/336

Claims (18)

(57) [Claims] 1. A N-type or 2 containing P-type impurities
One of the semiconductor region, disposed above or below the two semiconductor regions, the
Covering the two semiconductor regions and the same shape, and a layer containing a catalytic element allowed to promote the crystallization of amorphous silicon, a crystalline semiconductor layer provided to cover the two semiconductor regions, the crystalline semiconductor layer an insulating film provided Te, have a, a gate electrode provided on the insulating film, the crystalline semiconductor layer, a lower portion of the gate electrode
Crystallize in the direction connecting the two semiconductor regions
Wherein a it is. 2. A N-type or 2 containing P-type impurities
Yes and One semiconductor region, and the crystalline semiconductor layer provided over said semiconductor region, an insulating film provided to cover the crystalline semiconductor layer, and a gate electrode provided on the insulating film The crystalline semiconductor layer has a thickness of 1 × 10 ¹⁶ to 1 × 1.
A semiconductor device comprising a catalytic element for promoting crystallization of amorphous silicon of 0 ¹⁹ atoms / cm ³ . 3. A method according to claim 2 , wherein said impurity contains N-type or P-type impurities.
It has a One semiconductor region, and the crystalline semiconductor layer provided over said semiconductor region, an insulating film provided to cover the crystalline semiconductor layer, and a gate electrode provided on the insulating film The crystalline semiconductor layer is located below the gate electrode
Crystallized in a direction connecting the two semiconductor regions in 且
1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / cm ³ amorphous
A semiconductor device containing a catalytic element for promoting crystallization of silicon . 4. A source region and a drain region provided on the substrate, provided above or below the source region and the drain region, the source region and the drain region and the same shape, the crystallization of the amorphous silicon a layer containing a promoting allowed to catalyst element, provided so as to cover the source and drain regions
A crystalline semiconductor layer, wherein the crystalline semiconductor layer overlying provided insulating film, wherein a gate electrode provided on the insulating film, was perforated, 1 × 10 ¹⁶ to 1 in the crystalline semiconductor layer × 10
Promotes crystallization of amorphous silicon of ¹⁹ atoms / cm ³
A semiconductor device characterized by containing a catalytic element . 5. A source region and a drain region provided on the substrate, provided above or below the source region and the drain region, the source and drain regions and the same shape,
A layer containing a catalytic element allowed to promote the crystallization of amorphous silicon, is provided so as to cover the source and drain regions
A crystalline semiconductor layer, wherein the includes a crystalline semiconductor layer overlying provided an insulating film, and a gate electrode provided on the insulating film, the crystalline semiconductor layer, a lower portion of the gate electrode
Wherein a are crystallized in a direction connecting the drain region and the source region in. 6. A first step of forming a layer containing a catalytic element for promoting crystallization of amorphous silicon on a substrate; a second step of forming an N-type or P-type amorphous silicon film; A third step of forming two semiconductor regions serving as source / drain regions by etching a type or P type amorphous silicon film, a fourth step of forming an intrinsic amorphous silicon film, and thermal annealing , and allowed to crystallize the amorphous silicon film of the intrinsic, a fifth step of forming a sintered crystallized silicon film, a sixth step of forming an insulating film, the insulating film and forming crystallized silicon film is etched A seventh step of forming a contact hole with respect to the source / drain region; and an eighth step of forming a gate electrode and a source / drain electrode.
And a method for manufacturing a semiconductor device comprising: 7. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of irradiating a laser or a strong light equivalent thereto after the thermal annealing in the fifth step. 8. The method for manufacturing a semiconductor device according to claim 6, wherein the layer containing a catalyst element for promoting crystallization of amorphous silicon is formed by a spin coating method. 9. The method for manufacturing a semiconductor device according to claim 1, wherein the layer containing a catalytic element for promoting crystallization of amorphous silicon is formed by a sputtering method. 10. A first method for forming a layer containing a catalytic element for promoting crystallization of amorphous silicon on a substrate.
A second step of forming an N-type or P-type amorphous silicon film; and etching the N-type or P-type amorphous silicon film to form two semiconductor regions serving as source / drain regions. a third step of the fourth step of forming an amorphous silicon film of intrinsic, and a fifth step of forming an insulating film by thermal annealing, and allowed to crystallize the amorphous silicon film of the intrinsic, crystals of a sixth step of forming a silicon film, by etching the insulating film and forming crystallized silicon film, and a seventh step of forming a contact hole to the source / drain regions, a gate electrode and source / Eighth forming the drain electrode
And a method for manufacturing a semiconductor device comprising: 11. A first step of forming an N-type or P-type amorphous silicon film, a second step of forming a layer containing a catalytic element for promoting crystallization of amorphous silicon, A third step of etching the P-type amorphous silicon film to form two semiconductor regions serving as source / drain regions; a fourth step of forming an intrinsic amorphous silicon film; and allowed to crystallize the amorphous silicon film of intrinsic, and a fifth step of forming a sintered crystallized silicon film, a sixth step of forming an insulating film, by etching the insulating film and forming crystallized silicon film, A seventh step of forming a contact hole with respect to the source / drain region; and an eighth step of forming a gate electrode and a source / drain electrode.
And a method for manufacturing a semiconductor device comprising: 12. A first step of forming an N-type or P-type amorphous silicon film, a second step of forming a layer containing a catalytic element for promoting crystallization of amorphous silicon, A third step of forming two semiconductor regions serving as source / drain regions by etching the P-type amorphous silicon film, a fourth step of forming an intrinsic amorphous silicon film, and forming an insulating film a fifth step, by thermal annealing, the amorphous silicon film of intrinsic and allowed crystallization, a sixth step of forming a sintered crystallized silicon film, by etching the crystallized silicon film of the insulating film and the intrinsic A seventh step of forming a contact hole with respect to the source / drain region, and an eighth step of forming a gate electrode and a source / drain electrode.
And a method for manufacturing a semiconductor device comprising: 13. A first step of forming an N-type or P-type amorphous silicon film, and etching the N-type or P-type amorphous silicon film to form two semiconductor regions serving as source / drain regions. A second step of forming; a third step of forming an intrinsic amorphous silicon film; a fourth step of forming an insulating film; and etching the insulating film and the intrinsic amorphous silicon film to form the source / source. A fifth step of forming a contact hole with respect to the drain region, a sixth step of forming a layer containing a catalytic element for promoting crystallization of amorphous silicon on the substrate, and a step of thermally annealing the intrinsic amorphous layer. form a silicon film made to crystallization, the seventh step of forming a sintered crystallized silicon film, a gate electrode and source / drain electrodes Eighth to
And a method for manufacturing a semiconductor device comprising: 14. The laser of claim 7, wherein the laser is N
d: a semiconductor device characterized by being a YAG laser
Method of manufacturing. 15. 11. The method according to claim 10, wherein:
After annealing, there is a step of irradiating Nd: YAG laser
Of manufacturing a semiconductor device. 16. 12. The method according to claim 11, wherein
After annealing, there is a step of irradiating Nd: YAG laser
Of manufacturing a semiconductor device. 17. 13. The method according to claim 12, wherein:
After annealing, there is a step of irradiating Nd: YAG laser
Of manufacturing a semiconductor device. 18. 14. The method according to claim 13, wherein
After annealing, there is a step of irradiating Nd: YAG laser
Of manufacturing a semiconductor device.