KR100452443B1 - Method for fabricating of poly silicon Thin film transistor - Google Patents

Abstract

The present invention relates to a method of forming a polycrystalline thin film transistor.

In particular, the present invention relates to a method for removing the catalyst metal remaining in the crystal layer after the polycrystalline silicon forming process using the catalyst metal.

In summary, the active region is defined on the surface of the crystal layer in which the residue of the catalytic metal remains, and an oxide layer pattern is formed in the defined active region, and then the doped and activated ions are removed to remove the catalytic metal.

In this case, since the ions are not doped in the active region, a malfunction of the thin film transistor does not occur and the process is simplified.

Description

Method for fabricating polycrystalline silicon thin film transistor {Method for fabricating of poly silicon thin film transistor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a method for manufacturing a polycrystalline silicon thin film transistor which is a switching element of a liquid crystal display device.

Generally, in order to form a polycrystalline silicon thin film, pure amorphous silicon (intrinsic amorphous silicon) in a predetermined method, that is, plasma silicon vapor deposition (Plasma chemical vapor deposition) or LPCVD (Low pressure CVD) method of amorphous silicon with a thickness of 500 Å on the insulating substrate After the film was deposited, a method of crystallizing it was used. Crystallization methods can be classified into four categories as follows.

First, laser annealing is a method of growing polycrystalline silicon by applying a laser to a substrate on which an amorphous silicon thin film is deposited.

Second, solid phase crystallization (hereinafter referred to as SPC) method is a method of forming polycrystalline silicon by heat-treating amorphous silicon for a long time at a high temperature.

Third, the metal induced crystallization (MIC) method is a method of forming a polycrystalline silicon by depositing a metal on amorphous silicon, a large-area glass substrate can be used.

Fourth, the metal induced lateral crystallization method (MILC) is a method of forming an oxide pattern in an active region and then depositing metal to form polycrystalline silicon. Since it grows, it is a method which can improve the mobility of a carrier.

The first method, laser heat treatment, is a method of forming polycrystalline silicon, which is currently widely studied, which supplies laser energy to a substrate on which amorphous silicon is deposited to make the amorphous silicon in a molten state, and then forms polycrystalline silicon by cooling.

The second method, solid crystallization, forms a buffer layer with a predetermined thickness to prevent diffusion of impurities on a quartz substrate that can withstand high temperatures of 600 ° C. or higher, deposits amorphous silicon on the buffer layer, and then As a method of obtaining polycrystalline silicon by heat treatment at a high temperature for a long time, as described above, since the solid phase crystallization is performed for a long time at a high temperature, a desired polycrystalline silicon phase cannot be obtained, and the grain growth direction is irregular so that the polycrystalline silicon is applied to a thin film transistor. The breakdown voltage of the device is lowered due to irregular growth of the gate insulating layer to be connected to the gate, and the grain size of the polycrystalline silicon is extremely uneven, which lowers the electrical characteristics of the device and requires the use of an expensive quartz substrate. There is a problem.

The third and fourth methods, metal-induced crystallization, can form polycrystalline silicon using a low-cost, large-area glass substrate, but due to the high possibility of metal residues in the network inside the polycrystalline silicon, Although it is difficult to guarantee the reliability, attempts are being made to apply the new MIC method to apply crystallized polycrystalline silicon to thin film transistors and switching elements of liquid crystal displays.

Hereinafter, a conventional polycrystalline silicon forming process through a metal induced crystallization process will be described with reference to the accompanying drawings.

1A to 1C are cross-sectional views sequentially illustrating a manufacturing process of a polycrystalline silicon thin film transistor using a metal induced crystallization method.

First, as shown in FIG. 1A, a buffer layer 12 is formed by depositing one selected from a group of silicon insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) on a substrate 10.

The buffer layer 12 is to prevent the elution of the alkaline substance inside the substrate 10 by the applied heat.

Subsequently, amorphous silicon (a-Si: H) is deposited on the buffer layer 12 to form an amorphous silicon layer 14. Subsequently, the dehydrogenation process is performed on the amorphous silicon layer 14 at a predetermined temperature.

Next, as shown in FIG. 1B, the catalyst metal 16 is adsorbed onto the surface of the amorphous silicon layer 14.

Nickel (Ni) is used as a representative catalyst metal (16), and lead (Pb) and cobalt (Co) are used.

As the method of adsorbing the catalyst metal 16, an ion shower, ion doping, sputtering, CVD, or the like may be used.

When the heat is applied to the amorphous silicon layer to which the catalytic metal 16 is adsorbed by the above-described method, the polycrystalline silicon layer 15 as shown in FIG. 1C is formed.

Next, as shown in Fig. 1D, the island 8 is formed by patterning the polycrystalline silicon layer.

Next, the process illustrated in FIG. 1E is a step of forming a gate insulating film and a gate electrode. The gate insulating film 10 and the gate electrode 12, which are second insulating films, are formed on the island 8.

The island 8 may be divided into two regions, in which the first active region 14 is a pure silicon region, and the second active regions 16 and 17 are impurity regions. The second active regions 16 and 17 are located at both edges of the first active region 14.

Next, n + ions (for example, phosphorus) are doped on the entire surface of the substrate 10 on which the gate electrode 12 is formed.

The reason for doping the n + ions is to remove the catalytic metal remaining in the island-like active layer, particularly the first active region 14.

When the activation process is performed after the ion doping, the residue of the catalytic metal existing in the first active region 8 below the gate electrode 12, in a plan view, diffuses outward from the gate electrode 12. And exit and react with the doped ions to be present at the interface between the second active regions 16 and 17 and the gate insulating layer 10.

Therefore, when the gate electrode is used as an etch stop layer and the exposed gate insulating layer is etched in the following process, most metal residues can be removed.

As a result, the gate insulating film 10 and the gate electrode 12 are formed on the first active region 14.

In this case, the first insulating film and the second insulating film are formed of a material selected from the group consisting of silicon nitride (SiN _x ), silicon oxide (SiO ₂ ), and TEOS (Tetra Ethoxy Silane).

Next, as shown in FIG. 1F, p + impurity ions are doped as dopants to form ohmic contacts in the second active regions 16 and 17.

In this case, the gate electrode 12 serves as an ion stopper to prevent the dopant from penetrating into the first active region 14.

The dopant is doped with Group 3 elements such as B ₂ H ₆ .

FIG. 1G illustrates depositing and patterning a third insulating layer, an interlayer insulator 18, over the entire surface of the gate electrode 12, the second active regions 16, 17, and the second insulating layer 10. Thus, first and second contact holes 16 'and 17' are formed in the second active regions 16 and 17.

The figure shown in FIG. 1H is a combination of several processes.

First, the source electrode 20 and the drain electrode 22 contacting the second active regions 16 and 17, respectively, are formed through the contact holes 16 'and 17' formed in FIG. 1G.

In the above-described process, a p + type polycrystalline silicon thin film transistor T using a conventional metal induced crystallization method may be formed.

When applied to an array substrate for a liquid crystal display device, the protective layer 26 is deposited and patterned on the electrodes 20 and 22 and the entire surface of the substrate 10 to expose a portion of the drain electrode 22. A contact hole 27 is formed.

The transparent conductive electrode is deposited and patterned to form the pixel electrode 28 in contact with the exposed drain electrode 22.

In this manner, an array substrate for a liquid crystal display device including the polycrystalline silicon thin film transistor according to the present invention can be manufactured.

In the polycrystalline silicon thin film transistor forming method as described above, n + ions are doped to remove metal residues remaining in the crystal layer.

After the process of removing the catalyst metal is completed, even when the gate insulating layer is etched, the n + ions may remain in the second active region doped with the p + ions to form an ohmic contact layer.

Therefore, in such a case, when the p + ions are doped, there is a complexity in the process due to the difficult doping conditions in consideration of the remaining n + ions, and if the doping conditions are not properly matched, there is a problem that the characteristics of the device is bad.

The present invention has been made for the purpose of solving the above problems, and after forming a separate oxide film pattern in the first active region and the second active region, the step of doping ions to remove the residue of the catalyst metal Proceed.

In this way, the residue of the catalytic metal remaining in the active region can be effectively removed, and the dopant (p + ions) can be doped in the second active region because the n + ions can be prevented from being doped into the active region. Since the conditions are not demanding, there is no process complexity, and the device characteristics are also improved.

1A to 1H are cross-sectional views illustrating a conventional polycrystalline thin film transistor manufacturing method according to a process sequence.

2A through 2F are cross-sectional views illustrating a method of forming an active layer of a polycrystalline silicon thin film transistor according to a process sequence of the present invention;

3A to 3D are diagrams sequentially illustrating a process of manufacturing a polycrystalline silicon thin film transistor according to the present invention.

<Description of the symbols for the main parts of the drawings>

100: transparent insulating substrate 102: buffer layer

106 polycrystalline silicon layer 108 active region

112: oxide film pattern

According to another aspect of the present invention, there is provided a method of forming an active layer of a polycrystalline silicon thin film transistor, the method including forming a buffer layer as an insulating film on a substrate; Depositing amorphous silicon on the entire surface of the substrate on which the buffer layer is formed; adsorbing a catalyst metal on the amorphous silicon layer; Crystallizing the amorphous silicon layer to which the catalyst metal is adsorbed into a polycrystalline silicon layer; Defining an active region in the polycrystalline silicon layer; Forming an oxide film pattern planarly overlapping the defined active region; Doping n + ions to the polycrystalline silicon layer including the oxide layer pattern and then performing heat treatment to remove the catalytic metal present in the active region under the oxide layer pattern; Etching the exposed polycrystalline layer using the oxide layer pattern as a mask.

The doped n + ions react with silicon in the polycrystalline silicon layer to form silicide on the surface of the polycrystalline silicon layer on which the oxide layer pattern is not formed.

The catalytic metal is one selected from the group of metals consisting of nickel (Ni), cobalt (Co), and lead (Pb).

The buffer layer is formed by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiO ₂ ) and silicon oxide (SiN _X ).

According to an aspect of the present invention, there is provided a method of manufacturing a polycrystalline silicon thin film transistor, the method comprising: forming a buffer layer as a first insulating layer on a substrate; Depositing amorphous silicon on the entire surface of the substrate on which the buffer layer is formed; Adsorbing a catalyst metal on top of the amorphous silicon layer; Crystallizing the amorphous silicon layer to which the catalyst metal is adsorbed into a polycrystalline silicon layer; Defining an active region in the polycrystalline silicon layer; Forming an oxide film pattern planarly overlapping the defined active region; Doping n + ions to the crystalline silicon layer including the oxide film pattern and then performing a heat treatment to remove the catalytic metal present in the lower portion of the oxide film pattern; Etching the exposed polycrystalline silicon layer using the oxide film pattern as a mask; Removing the oxide layer pattern to form an island-shaped active layer; Forming a gate insulating film, which is a second insulating film, on a portion of the active layer; Forming a gate electrode on the active layer over the gate insulating film; Doping an active layer exposed to both sides of the gate electrode to form an ohmic contact layer; Forming a third insulating film on an entire surface of the substrate on which the ohmic contact layer is formed; Patterning the third insulating film to form a first contact hole and a second contact hole exposing the ohmic contact layer; Forming a source electrode contacting the ohmic contact layer exposed through the first contact hole and a drain electrode contacting the ohmic contact layer through the second contact hole.

Hereinafter, with reference to the accompanying drawings and embodiments will be described the present invention in detail.

Example

The present invention is characterized in that to form a separate oxide film pattern in the crystallized crystal layer using a catalyst metal, doping and activating ions, to remove the residue of the catalyst metal remaining in the lower crystal layer of the oxide film pattern.

2A to 2F, a method of removing catalyst metal residues according to the present invention will be described.

First, as shown in FIG. 2A, one selected from a group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) is deposited and patterned on the substrate 100 to form a buffer layer 102. do.

Subsequently, amorphous silicon is deposited on the buffer layer 102 to form an amorphous silicon layer 104.

Subsequently, as shown in FIG. 2B, a small amount of catalytic metal 105 is adsorbed on the amorphous silicon layer 104.

When heat is applied to the amorphous silicon layer 104 to which the catalyst metal 105 is adsorbed, silicide (NiSi ₂ ) is formed by reacting the adsorbed catalyst metal with silicon on the surface of the amorphous silicon layer 104. The silicide is diffused into the lower portion of the amorphous silicon layer 104 and crystallization proceeds.

Thus, as shown in FIG. 2C, a polysilicon layer 106 composed of a plurality of crystal grains 110 is formed.

Next, as shown in 2d, an oxide film is formed on the polycrystalline layer 106 and then patterned to form an oxide film pattern 112 defining the active region 108.

The active region 108 is defined as a first active region 114 serving as a channel and second active regions 116 and 117 serving as an ohmic contact layer.

Subsequently, when the heat treatment process is performed after doping n + ions on the polycrystalline silicon layer 06 including the oxide layer pattern 112, the first active region 114 and the first active region 114 under the oxide layer pattern 112 are formed. 2, the catalytic metal remaining in the active regions 116 and 117 diffuses out of the oxide film pattern and reacts with the doped ions.

If the catalyst metal is nickel (Ni) and the doping material is phosphorus, phosphorus is reacted with NiP.

Therefore, half of the catalyst metal residue reacted with the doped ions is present in the polycrystalline layer 106 in which the oxide layer pattern 112 is not formed.

Next, as shown in FIG. 2E, the polycrystalline layer exposed below is removed using the oxide film pattern 112 as a mask.

Subsequently, as shown in FIG. 2F, the active layer 108 can be formed as a ratio by removing the oxide film pattern 112 using a predetermined etching means.

Hereinafter, the process of FIG. 3A-FIG. 3D demonstrates the process of forming a thin film transistor in order sequentially following the process of FIG. 2A-FIG. 2F.

3A illustrates a cross-section of an active layer manufactured through the process of FIGS. 2A to 2F.

As described above, the active layer 108 is defined as a first active region 114 and a second active region 116 and 117.

Next, the process illustrated in FIG. 3B is a step of forming a gate insulating film and a gate electrode to form a gate insulating film 110 and a gate electrode 112 as a second insulating film on the active layer 108.

The gate insulating layer 110 and the gate electrode 112 have a shape located on the first active region 114.

In this case, the first insulating film and the second insulating film are formed of a material selected from the group consisting of silicon nitride (SiN _x ), silicon oxide (SiO ₂ ), and TEOS (Tetra Ethoxy Silane).

The gate electrode 112 and the gate insulating layer 110 are formed in the same pattern to reduce the number of masks.

After the gate electrode 112 is formed, p + ions are doped to form an ohmic contact layer in the second active region. In this case, the gate electrode 112 serves as an ion stopper to prevent the dopant from penetrating into the first active region 114.

Since the doped dopant is a Group 3 element such as B ₂ H ₆ , a P planar channel is formed in the first active region 114.

3C illustrates depositing and patterning a third insulating layer, an interlayer insulator 118, over the entire surface of the gate electrode 112, the second active regions 116 and 117, and the second insulating layer 110. Thus, first contact holes and second contact holes 116 ′ and 117 ′ are formed in the second active regions 116 and 117.

The drawing shown in FIG. 3D shows a combination of various processes.

First, the source electrode 120 and the drain electrode 122 contacting the second active regions 116 and 117 are formed through the contact holes 116 ′ and 117 ′ formed in FIG. 3C.

Thereafter, the protective layer 126 is deposited and patterned on the electrodes 120 and 122 and the entire surface of the substrate to form a drain contact hole 127 exposing a portion of the drain electrode 122.

A transparent conductive metal material including indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited and patterned to form a transparent pixel electrode 128 in contact with the exposed drain electrode 122. do.

In this manner, an array substrate for a liquid crystal display device including the polycrystalline silicon thin film transistor according to the present invention can be manufactured.

In the method of manufacturing a polycrystalline silicon thin film transistor according to the present invention, after forming an oxide layer pattern on the active region of the polycrystalline silicon layer, a method of removing residues of the catalyst metal by doping ions to the polycrystalline silicon layer having the oxide layer pattern formed thereon is used. Therefore, the residue of the catalyst metal can be effectively removed without doping ions directly into the active layer.

Therefore, the operation failure of the thin film transistor by the doped ions does not occur, and unlike the conventional conditions for doping p + ions in the second active region is not difficult to improve the yield (yield) can be improved. .

Claims (12)

Forming a buffer layer which is an insulating film on the substrate; Depositing amorphous silicon on the entire surface of the substrate on which the buffer layer is formed; Adsorbing a catalyst metal on top of the amorphous silicon layer; Crystallizing the amorphous silicon layer adsorbed by the catalyst metal into a polycrystalline silicon layer Steps; Defining an active region in the polycrystalline silicon layer; Forming an oxide film pattern planarly overlapping the defined active region; Doping n + ions to the polycrystalline silicon layer including the oxide layer pattern and then performing heat treatment to remove the catalytic metal present in the active region under the oxide layer pattern; Etching the exposed polycrystalline layer using the oxide layer pattern as a mask; A method of forming an active layer of a polycrystalline silicon thin film transistor comprising. delete The method of claim 1, The catalyst metal is an active layer forming method of a polycrystalline silicon thin film transistor formed of a metal group consisting of nickel (Ni), cobalt (Co), lead (Pb). The method of claim 1, The buffer layer is a method of forming an active layer of a polycrystalline silicon thin film transistor deposited by one selected from the group of inorganic insulating materials including silicon nitride (SiO ₂ ) and silicon oxide (SiN _X ). Forming a buffer layer, which is a first insulating film, on the substrate; Depositing amorphous silicon on the entire surface of the substrate on which the buffer layer is formed; Adsorbing a catalyst metal on top of the amorphous silicon layer; Crystallizing the amorphous silicon layer adsorbed by the catalyst metal into a polycrystalline silicon layer Steps; Defining an active region in the polycrystalline silicon layer; Forming an oxide film pattern planarly overlapping the defined active region; Doping n + ions to the polycrystalline silicon layer including the oxide film pattern and then performing a heat treatment to remove the catalytic metal present in the lower portion of the oxide film pattern; Etching the exposed polycrystalline silicon layer using the oxide film pattern as a mask; Removing the oxide layer pattern to form an island-shaped active layer; Forming a gate insulating film, which is a second insulating film, on a portion of the active layer; Forming a gate electrode on the active layer over the gate insulating film; Doping impurity ions in the active layer exposed to both sides of the gate electrode to form an ohmic contact layer; Forming a third insulating film on an entire surface of the substrate on which the ohmic contact layer is formed; Patterning the third insulating film to form a first contact hole and a second contact hole exposing the ohmic contact layer; Forming a source electrode contacting the ohmic contact layer exposed through the first contact hole and a drain electrode contacting the ohmic contact layer through the second contact hole Polycrystalline thin film transistor manufacturing method comprising a. delete The method of claim 5, wherein The catalyst metal is a polycrystalline silicon thin film transistor manufacturing method formed of a metal group consisting of nickel (Ni), cobalt (Co), lead (Pb). The method of claim 5, wherein The first and second insulating layers are a material selected from the group consisting of a silicon nitride film (SiN _x ), a silicon oxide film (SiO ₂ ), and TEOS (Tetra Ethoxy Silane). The method of claim 5, wherein And the impurity is a P-type semiconductor. The method of claim 1, When the heat treatment is performed after the doping the n + ions, the catalyst metal under the oxide film pattern is diffused into a polycrystalline layer other than the oxide film pattern to react with the n + ions to form a reactant to form an active layer of a polycrystalline silicon thin film transistor. The method of claim 1, After etching the polycrystalline silicon layer, removing the oxide layer pattern. The method of claim 5 When the heat treatment is carried out after the doping the n + ions, the catalyst metal under the oxide film pattern is diffused into a polycrystalline layer other than the oxide film pattern to react with the n + ions to form a reactant polycrystalline silicon thin film transistor manufacturing method.