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JP3196567B2 - Pressure contact type semiconductor device and method of manufacturing the same - Google Patents

Pressure contact type semiconductor device and method of manufacturing the same

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Publication number
JP3196567B2
JP3196567B2 JP11417395A JP11417395A JP3196567B2 JP 3196567 B2 JP3196567 B2 JP 3196567B2 JP 11417395 A JP11417395 A JP 11417395A JP 11417395 A JP11417395 A JP 11417395A JP 3196567 B2 JP3196567 B2 JP 3196567B2
Authority
JP
Japan
Prior art keywords
projection
passivation film
contact plate
cathode contact
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP11417395A
Other languages
Japanese (ja)
Other versions
JPH08316255A (en
Inventor
勝弘 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP11417395A priority Critical patent/JP3196567B2/en
Publication of JPH08316255A publication Critical patent/JPH08316255A/en
Application granted granted Critical
Publication of JP3196567B2 publication Critical patent/JP3196567B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Thyristors (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、高速サイリスタや大
口径のサイリスタなど複雑な形状のゲート電極構造を有
する増幅ゲート形サイリスタなどの加圧接触型の圧接平
型半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pressure contact type flat semiconductor device such as an amplification gate type thyristor having a gate electrode structure of a complicated shape such as a high speed thyristor or a large diameter thyristor.

【0002】[0002]

【従来の技術】高速サイリスタや大口径のサイリスタで
は、半導体基体(シリコンウエハにpnpn層を形成し
た拡散接合体)の主表面に配置したカソード電極を最大
限有効に利用するため、カソード電極主表面に入り組ん
だ複雑な形状の増幅ゲート電極を有するようにするのが
一般的な設計手段である。
2. Description of the Related Art In a high-speed thyristor or a large-diameter thyristor, a cathode electrode disposed on a main surface of a semiconductor substrate (a diffusion bonded body in which a pnpn layer is formed on a silicon wafer) is used most effectively. It is common design practice to have an intricate and complex shaped amplification gate electrode.

【0003】図5は複雑な形状のゲート電極構造を有す
る増幅ゲート形サイリスタの構造図で、同図(a)は平
面図、同図(b)は同図(a)のA−A線断面図を示
す。半導体基体1の主面にはカソード電極103、ゲー
ト電極101及び増幅ゲート電極102が配置されてい
る。このサイリスタの動作は、ゲート電極101に+電
源、カソード電極103に−電源としてゲート電流を通
電すると、このゲート電流と、増幅ゲート電極102部
で増幅された電流(この個所のpnpnサイリスタがオ
ンしたときの電流)を加えてカソード電極103に流れ
サイリスタはオン状態となる。このような構造を有する
サイリスタを常に正常動作を維持させるためには、主電
流の流れるカソード電極103と、ゲート電極101お
よび増幅ゲート電極102で構成されるその他の電極と
は完全に分離する必要がある。また半導体基体1は支持
板10に合金等で固着されている。次に完全分離した構
造の従来例を図7〜図10に示す。
FIG. 5 is a structural view of an amplifying gate thyristor having a gate electrode structure of a complicated shape. FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along line AA in FIG. The figure is shown. On the main surface of the semiconductor substrate 1, a cathode electrode 103, a gate electrode 101 and an amplification gate electrode 102 are arranged. The operation of the thyristor is as follows. When a gate current is supplied as a + power supply to the gate electrode 101 and a − power supply is supplied to the cathode electrode 103, the gate current and the current amplified by the amplification gate electrode 102 (the pnpn thyristor at this point is turned on) Thyristor is turned on. In order for the thyristor having such a structure to always maintain normal operation, it is necessary to completely separate the cathode electrode 103, through which the main current flows, from the other electrodes including the gate electrode 101 and the amplification gate electrode 102. is there. The semiconductor substrate 1 is fixed to the support plate 10 with an alloy or the like. Next, a conventional example of a completely separated structure is shown in FIGS.

【0004】図6は半導体基体1とカソード接触板3と
をシリコーンゴムなどの接着剤4で固着した場合の断面
図である。図7は半導体基体1のゲート電極101と増
幅ゲート電極102の部分をエッチング技術によって段
差1aをつけ、ゲート電極101部に対応する部分に単
純円状の開口部を有するカソード接触板3を半導体基板
1に接触させ、外周の位置合わせリング5によって固定
した場合の断面図である。
FIG. 6 is a cross-sectional view when the semiconductor substrate 1 and the cathode contact plate 3 are fixed with an adhesive 4 such as silicone rubber. FIG. 7 shows that the gate electrode 101 and the amplification gate electrode 102 of the semiconductor substrate 1 are provided with a step 1a by an etching technique, and the cathode contact plate 3 having a simple circular opening in the portion corresponding to the gate electrode 101 is connected to the semiconductor substrate. 1 is a cross-sectional view in the case of contacting with a reference numeral 1 and being fixed by a positioning ring 5 on the outer periphery.

【0005】図8は図7の問題点を解決するために、段
差1aの直下に高濃度の不純物を拡散し高濃度拡散層6
を形成し、この部分の抵抗を低下させ、過大な電圧を発
生させることなしで、オン動作が容易にできるようにし
た構造の断面図である。図9は図7の問題点をさらに抜
本的に解決するため、増幅ゲート電極102の上に絶縁
膜7(例えばポリイミド樹脂、シリコーン樹脂等)を被
着し、増幅ゲート電極102とカソード接触板3との放
電の危険性を排除した構造とした断面図である。
[0005] FIG. 8 shows a high-concentration diffusion layer 6 formed by diffusing a high-concentration impurity immediately below the step 1a in order to solve the problem of FIG.
FIG. 4 is a cross-sectional view of a structure in which the ON operation can be easily performed without lowering the resistance of this portion and generating an excessive voltage. FIG. 9 shows a method of drastically solving the problem of FIG. 7 by covering the amplifying gate electrode 102 with an insulating film 7 (for example, polyimide resin, silicone resin, etc.), and amplifying the gate electrode 102 and the cathode contact plate 3. FIG. 4 is a cross-sectional view of a structure excluding the danger of discharge.

【0006】[0006]

【発明が解決しようとする課題】図6の構造ではシリコ
ーンゴムなどの接着剤4がカソード接触板3と半導体基
体1上のカソード電極103との隙間に毛管現象によっ
て浸透し、電気的接触不良を起こす危険性が大きい。図
7の構造では、段差1aをつけたことで電気的な抵抗が
大きくなり、増幅ゲート電極102からカソード電極1
03に流れる前記の増幅された電流により過大な電圧が
増幅ゲート電極に発生し、増幅ゲート電極102とカソ
ード接触板3とで放電を起こす危険性が大きい。
In the structure shown in FIG. 6, the adhesive 4 such as silicone rubber penetrates into the gap between the cathode contact plate 3 and the cathode electrode 103 on the semiconductor substrate 1 by capillary action, and the electrical contact failure is reduced. There is a high risk of starting. In the structure of FIG. 7, the electric resistance increases due to the provision of the step 1a.
An excessive voltage is generated at the amplification gate electrode by the above-described amplified current flowing through the gate electrode 03, and there is a high risk of causing a discharge between the amplification gate electrode 102 and the cathode contact plate 3.

【0007】また、図6ないし図9の構造では段差形
成、高濃度不純物拡散、絶縁膜被着など作業工程の大幅
増加となること、また段差形成では、溝の深さのバラツ
キによってゲート部の抵抗(ゲートインピーダンス)値
にバラツキが発生し、安定した点弧特性やターンオン特
性の確保が難しいなど多くの課題がある。この発明は前
記課題を解決するために、カソード接触板をゲート電極
および増幅ゲート電極から確実に分離し、素子特性上信
頼性が高く、組立性の良い圧接平型半導体装置を提供す
ることを目的とする。
In the structures shown in FIGS. 6 to 9, the number of working steps such as step formation, high-concentration impurity diffusion, insulating film deposition, etc. is greatly increased. There are many problems, such as variations in resistance (gate impedance) values, making it difficult to ensure stable ignition characteristics and turn-on characteristics. SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, an object of the present invention is to provide a press-contact flat type semiconductor device in which a cathode contact plate is reliably separated from a gate electrode and an amplification gate electrode, and has high reliability in element characteristics and good assemblability. And

【0008】[0008]

【課題を解決するための手段】前記の目的を達成するた
めに、半導体基体の主面に、放射状に凹凸を有する増幅
ゲート電極と、増幅ゲート電極を取り囲むカソード電極
が形成され、さらに半導体基体の外周部にパッシベーシ
ョン膜を被覆したものにおいて、カソード電極と接触す
るカソード接触板の一部をパッシベーション膜に固着す
る。
In order to achieve the above object, an amplification gate electrode having radial irregularities and a cathode electrode surrounding the amplification gate electrode are formed on a main surface of a semiconductor substrate. In the case where the outer peripheral portion is covered with a passivation film, a part of the cathode contact plate that is in contact with the cathode electrode is fixed to the passivation film.

【0009】またカソード接触板の中央部に増幅ゲート
電極より大きい輪郭を有する開口部が設けられ、さらに
カソード接触板の外周部に突起部が設けられ、この突起
部をパッシベーション膜で固着するとよい。またカソー
ド接触板の突起部がほぼ直角に折り曲げられ、さらにパ
ッシベーション膜の厚さと同程度の高さで外周方向にほ
ぼ直角に再度折り曲げられ、再度折り曲げられた部分を
パッシベーション膜の表面に接触させ、この再度折り曲
げられた部分をパッシベーション膜の表面に接着剤で固
着してもよい。
An opening having a contour larger than that of the amplification gate electrode is provided at the center of the cathode contact plate, and a projection is provided at the outer periphery of the cathode contact plate. The projection may be fixed by a passivation film. In addition, the projection of the cathode contact plate is bent substantially at a right angle, further bent substantially perpendicularly in the outer peripheral direction at the same height as the thickness of the passivation film, and the bent portion is brought into contact with the surface of the passivation film, This refolded portion may be fixed to the surface of the passivation film with an adhesive.

【0010】またカソード接触板と同一平面上に形成さ
れた突起部を半導体基体に接触させ、この突起部をパッ
シベーション膜で固着してもよい。このカソード接触板
は、圧延方法で製作されたモリブデンなどの材料で、こ
のカソード接触板の厚さは0.1〜0.3mmで、この
カソード接触板の開口部および突起部を含む外周端の加
工が打ち抜き加工で行われ、この突起部の曲げ加工が絞
り加工で行われるとよい。
[0010] Further, a projection formed on the same plane as the cathode contact plate may be brought into contact with the semiconductor substrate, and the projection may be fixed by a passivation film. The cathode contact plate is made of a material such as molybdenum manufactured by a rolling method. The thickness of the cathode contact plate is 0.1 to 0.3 mm. The processing is preferably performed by punching, and the bending of the protrusion is preferably performed by drawing.

【0011】[0011]

【作用】増幅ゲート電極よりやや大きな輪郭の開口部
を、カソード接触板に設け、カソード接触板の外周端に
設けた突起部を、パッシベーション膜に固着することに
よって、カソード接触板はカソード電極上に位置決め固
定され、増幅ゲート電極とカソード接触板との距離は確
実に確保される。
The cathode contact plate is formed on the cathode electrode by providing an opening having a profile slightly larger than the amplification gate electrode on the cathode contact plate and fixing the projection provided on the outer peripheral end of the cathode contact plate to the passivation film. It is positioned and fixed, and the distance between the amplification gate electrode and the cathode contact plate is reliably ensured.

【0012】[0012]

【実施例】図1はこの発明の第1実施例の要部構成図
で、同図(a)は平面図、同図(b)は同図(a)のA
−A線断面図を示す。半導体基体1の主面にカソード電
極103とゲート電極101および増幅ゲート電極10
2が形成される。増幅ゲート電極102の平面形状は円
形でなく、例えば4本の腕が伸びた形状となっており、
カソード電極103の内端は増幅ゲート電極102の外
端に並行に対向している。半導体基体1の外周部はパッ
シベーション膜2で被覆されている。尚外周部の形状は
耐圧を確保するためポジティブベベルなど特殊な形状を
しているがここでは単純化されて描かれている。また半
導体基体1の他面には支持板は固着されていない。カソ
ード接触板3の中央部はカソード電極103の内端より
やや大きめに開口され、増幅ゲート電極102やゲート
電極101に接触しない構造となっている。また、カソ
ード接触板3の外周端はパッシベーション膜2の内端よ
りやや小さく、加圧力で確実にカソード電極103に接
触する。カソード接触板3の外周端の一部に突起部31
を設け、この突起部31はほぼ直角に折り曲げられ、さ
らにパッシベーション膜2の厚さで外周方向にほぼ直角
に再度折り曲げられ、この再度折り曲げられた突起部3
2をパッシベーション膜2の表面に接着剤4で固着す
る。同図(a)では再度折り曲げられた突起部32が示
され、全体の突起部31の断面図は同図(b)に示され
ている。パッシベーション膜2はシリコーン樹脂やポリ
イミド樹脂などで形成され、その厚さは数mmである。
またカソード接触板3の材質はモリブデンまたはタング
ステンなどであり、中央部の開口部および突起部は打ち
抜き加工で成形され、突起部の曲げ加工は絞り加工で行
われる。この加工を容易にするために、モリブデン板ま
たはタングステン板の厚さは0.1〜0.3mmであ
る。また加工後は水素還元雰囲気で加工歪みを除去する
熱処理を行うとよい。また突起部の固着に使われる接着
剤4の材質はシリコーンゴムなどである 図2はこの発明の第2実施例の要部断面図を示す。同図
は図1(a)のA−A線切断部に相当した断面図であ
る。図1(b)と異なる点は、パッシベーション膜2の
表面の一部を削って、再度折り曲げた突起部32を接着
剤4で固着した点である。これは突起部31の折り曲げ
部の高さを高く出来ない場合、つまり大きな絞り加工が
出来にくい材質を用いる場合に有効である。
FIG. 1 is a schematic diagram showing a main part of a first embodiment of the present invention. FIG. 1A is a plan view, and FIG.
FIG. The cathode electrode 103, the gate electrode 101, and the amplification gate electrode 10
2 are formed. The planar shape of the amplification gate electrode 102 is not circular, but is, for example, a shape in which four arms are extended.
The inner end of the cathode electrode 103 faces the outer end of the amplification gate electrode 102 in parallel. The outer peripheral portion of the semiconductor substrate 1 is covered with a passivation film 2. The shape of the outer peripheral portion has a special shape such as a positive bevel in order to secure a withstand voltage, but is simplified here. The support plate is not fixed to the other surface of the semiconductor substrate 1. The central portion of the cathode contact plate 3 is opened slightly larger than the inner end of the cathode electrode 103, and has a structure that does not contact the amplification gate electrode 102 or the gate electrode 101. Further, the outer peripheral end of the cathode contact plate 3 is slightly smaller than the inner end of the passivation film 2 and reliably contacts the cathode electrode 103 by the applied pressure. A projection 31 is formed on a part of the outer peripheral end of the cathode contact plate 3.
The projection 31 is bent substantially at a right angle, and further bent substantially at right angles in the outer peripheral direction by the thickness of the passivation film 2.
2 is fixed to the surface of the passivation film 2 with an adhesive 4. FIG. 7A shows the projection 32 bent again, and a cross-sectional view of the entire projection 31 is shown in FIG. The passivation film 2 is formed of a silicone resin, a polyimide resin, or the like, and has a thickness of several mm.
The material of the cathode contact plate 3 is molybdenum, tungsten, or the like. The central opening and the projection are formed by punching, and the projection is bent by drawing. In order to facilitate this processing, the thickness of the molybdenum plate or the tungsten plate is 0.1 to 0.3 mm. After the processing, a heat treatment for removing the processing distortion in a hydrogen reducing atmosphere may be performed. The material of the adhesive 4 used for fixing the projection is silicone rubber or the like. FIG. 2 is a sectional view showing a main part of a second embodiment of the present invention. FIG. 3 is a cross-sectional view corresponding to a section taken along line AA of FIG. 1B is different from FIG. 1B in that a part of the surface of the passivation film 2 is shaved off and the bent protruding portion 32 is fixed with an adhesive 4. This is effective when the height of the bent portion of the projection 31 cannot be increased, that is, when a material that is difficult to perform a large drawing process is used.

【0013】図3はこの発明の第3実施例の要部断面図
を示す。同図も図1(a)のA−A線切断部に相当した
断面図である。突起部31を折り曲げずに、半導体基体
の表面に接触させ、パッシベーション膜2で固着する。
これは、全く絞り加工が出来ない材質を用いる場合に有
効である。この場合は、パッシベーション膜を形成する
シリコーンゴムが毛細管現象でカソード電極103とカ
ソード接触板3の間に浸透しないように、カソード接触
板3の外周部にリング状の溝を設け、浸透してきたシリ
コーンゴムを溝で溜めて、それより内部に浸透すること
を防止する方策等を取る必要がある。
FIG. 3 is a sectional view showing a main part of a third embodiment of the present invention. This figure is also a cross-sectional view corresponding to a section taken along the line AA in FIG. The projection 31 is not bent and is brought into contact with the surface of the semiconductor substrate, and is fixed by the passivation film 2.
This is effective when a material that cannot be drawn at all is used. In this case, a ring-shaped groove is provided on the outer peripheral portion of the cathode contact plate 3 so that the silicone rubber forming the passivation film does not penetrate between the cathode electrode 103 and the cathode contact plate 3 due to a capillary phenomenon. It is necessary to store the rubber in the groove and take measures to prevent the rubber from penetrating therethrough.

【0014】図4は再度折り曲げられた突起部32の形
状を示した図で、同図(a)は第1形状図、同図(b)
は第2形状図、同図(c)は第3形状図を示す。これら
の形状は再度折り曲げられた突起部32の接着部先端の
形状を示し、このような切り欠けが設けられた形状とす
ることで接着部が一層強固に固着される。
FIG. 4 is a view showing the shape of the projection 32 bent again. FIG. 4A is a diagram showing the first shape, and FIG.
Shows a second shape diagram, and FIG. 3C shows a third shape diagram. These shapes show the shape of the tip of the bonding portion of the projection 32 that is bent again, and the bonding portion is more firmly fixed by adopting such a notch.

【0015】[0015]

【発明の効果】この発明によって、ゲート電極および増
幅ゲート電極とカソード接触板とは確実に分離され、こ
のゲート電極および増幅ゲート電極とカソード接触板と
の間での短絡、放電が防止でき、素子特性において信頼
性が高く、組立性がよい圧接平型半導体装置を得ること
ができた。
According to the present invention, the gate electrode and the amplifying gate electrode are reliably separated from the cathode contact plate, and a short circuit and discharge between the gate electrode and the amplifying gate electrode and the cathode contact plate can be prevented. A flat-contact type semiconductor device having high reliability in characteristics and good assemblability was obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の第1実施例の要部構成図で、(a)
は平面図、(b)は(a)のA−A切断部の断面図
FIG. 1 is a configuration diagram of a main part of a first embodiment of the present invention, and FIG.
Is a plan view, and (b) is a cross-sectional view of an AA cut portion of (a).

【図2】この発明の第2実施例の要部断面図FIG. 2 is a sectional view of a main part of a second embodiment of the present invention.

【図3】この発明の第3実施例の要部断面図FIG. 3 is a sectional view of a main part of a third embodiment of the present invention.

【図4】突起部の接着個所の形状を示した図FIG. 4 is a diagram showing a shape of a bonding portion of a protrusion.

【図5】増幅ゲート形サイリスタの構造図で、(a)は
平面図、(b)は(a)のA−A線断面図
5A and 5B are structural views of an amplification gate type thyristor, wherein FIG. 5A is a plan view and FIG. 5B is a cross-sectional view taken along line AA of FIG.

【図6】半導体基体1とカソード接触板3とをシリコー
ンゴムなどの接着剤4で固着した従来例の断面図
FIG. 6 is a sectional view of a conventional example in which a semiconductor substrate 1 and a cathode contact plate 3 are fixed with an adhesive 4 such as silicone rubber.

【図7】半導体基体のゲート電極と増幅ゲート電極の部
分に段差をつけた従来例の断面図
FIG. 7 is a cross-sectional view of a conventional example in which a step is formed in a portion of a gate electrode and an amplification gate electrode of a semiconductor substrate.

【図8】段差の直下に高濃度の不純物を拡散した従来例
の断面図
FIG. 8 is a sectional view of a conventional example in which a high-concentration impurity is diffused immediately below a step;

【図9】増幅ゲート電極上に絶縁膜を被着した従来例の
断面図
FIG. 9 is a cross-sectional view of a conventional example in which an insulating film is deposited on an amplification gate electrode.

【符号の説明】[Explanation of symbols]

1 半導体基体 1a 段差 2 パッシベーション膜 3 カソード接触板 4 接着剤 5 位置合わせリング 6 高濃度拡散層 7 絶縁膜 10 支持板 101 ゲート電極 102 増幅ゲート電極 103 カソード電極 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Step 2 Passivation film 3 Cathode contact plate 4 Adhesive 5 Alignment ring 6 High concentration diffusion layer 7 Insulating film 10 Support plate 101 Gate electrode 102 Amplification gate electrode 103 Cathode electrode

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/52 H01L 29/74 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/52 H01L 29/74

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基体の主面に、放射状に凹凸を有す
る増幅ゲート電極と、増幅ゲート電極を取り囲むカソー
ド電極が形成され、さらに半導体基体の外周部にパッシ
ベーション膜を被覆したものにおいて、カソード電極と
接触するカソード接触板の一部がパッシベーション膜に
固着されていることを特徴とする圧接平型半導体装置。
1. A semiconductor substrate in which an amplification gate electrode having irregularities in a radial direction and a cathode electrode surrounding the amplification gate electrode are formed on a main surface of a semiconductor substrate, and the outer periphery of the semiconductor substrate is covered with a passivation film. A flattened contact type semiconductor device, wherein a part of a cathode contact plate which is in contact with the semiconductor device is fixed to a passivation film.
【請求項2】カソード接触板の中央部に増幅ゲート電極
より大きい輪郭を有する開口部が設けられ、さらに該カ
ソード接触板の外周部に突起部が設けられ、該突起部が
パッシベーション膜で固着されていることを特徴とする
請求項1記載の圧接平型半導体装置。
2. An opening having a contour larger than the amplification gate electrode is provided at the center of the cathode contact plate, and a projection is provided on the outer periphery of the cathode contact plate, and the projection is fixed by a passivation film. The flattened semiconductor device according to claim 1, wherein:
【請求項3】カソード接触板の突起部がほぼ直角に折り
曲げられ、さらにパッシベーション膜の厚さと同程度の
高さで外周方向にほぼ直角に再度折り曲げられ、再度折
り曲げられた部分をパッシベーション膜の表面に接触さ
せ、該再度折り曲げられた部分がパッシベーション膜の
表面に接着剤で固着されていることを特徴とする請求項
2記載の圧接平型半導体装置。
3. The projection of the cathode contact plate is bent substantially at a right angle, further bent substantially at right angles in the outer peripheral direction at the same height as the thickness of the passivation film, and the portion bent again is formed on the surface of the passivation film. 3. The flattened semiconductor device according to claim 2, wherein said bent portion is fixed to the surface of the passivation film with an adhesive.
【請求項4】カソード接触板の突起部がほぼ直角に折り
曲げられ、さらにパッシベーション膜の厚さより小さい
高さで外周方向にほぼ直角に、再度折り曲げられ、再度
折り曲げられた突起部が、パッシベーション膜の表面を
一部除去した部分に接着剤で固着されていることを特徴
とする請求項2記載の圧接平型半導体装置。
4. The projection of the cathode contact plate is bent substantially at a right angle, and further bent substantially perpendicularly to the outer periphery at a height smaller than the thickness of the passivation film, and the projection bent again is formed of the projection of the passivation film. 3. The flattened semiconductor device according to claim 2, wherein the semiconductor device is fixed to a part of the surface with a part removed by an adhesive.
【請求項5】カソード接触板と同一平面上に形成された
突起部を半導体基体に接触させ、該突起部がパッシベー
ション膜で固着されていることを特徴とする請求項2記
載の圧接平型半導体装置の製造方法。
5. The flattened semiconductor according to claim 2, wherein a projection formed on the same plane as the cathode contact plate is brought into contact with the semiconductor substrate, and the projection is fixed with a passivation film. Device manufacturing method.
【請求項6】カソード接触板は、圧延方法で製作された
金属材料で、該カソード接触板の厚さは0.1〜0.3
mmで、該カソード接触板の開口部および突起部を含む
外周端の加工が打ち抜き加工で行われ、さらに該突起部
の曲げ加工が絞り加工で行われることを特徴とする請求
項2記載の圧接平型半導体装置の製造方法。
6. The cathode contact plate is a metal material manufactured by a rolling method, and has a thickness of 0.1 to 0.3.
3. The pressure contact according to claim 2, wherein the outer peripheral edge including the opening and the projection of the cathode contact plate is worked by punching, and the projection is bent by drawing. A method for manufacturing a flat semiconductor device.
JP11417395A 1995-05-12 1995-05-12 Pressure contact type semiconductor device and method of manufacturing the same Expired - Fee Related JP3196567B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11417395A JP3196567B2 (en) 1995-05-12 1995-05-12 Pressure contact type semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11417395A JP3196567B2 (en) 1995-05-12 1995-05-12 Pressure contact type semiconductor device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH08316255A JPH08316255A (en) 1996-11-29
JP3196567B2 true JP3196567B2 (en) 2001-08-06

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP11417395A Expired - Fee Related JP3196567B2 (en) 1995-05-12 1995-05-12 Pressure contact type semiconductor device and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP3196567B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111883587A (en) * 2020-07-14 2020-11-03 株洲中车时代半导体有限公司 Thyristor chip, thyristor and manufacturing method thereof

Also Published As

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