CN111883587A - Thyristor chip, thyristor and manufacturing method thereof - Google Patents
Thyristor chip, thyristor and manufacturing method thereof Download PDFInfo
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- CN111883587A CN111883587A CN202010677130.4A CN202010677130A CN111883587A CN 111883587 A CN111883587 A CN 111883587A CN 202010677130 A CN202010677130 A CN 202010677130A CN 111883587 A CN111883587 A CN 111883587A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3732—Diamonds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7428—Thyristor-type devices, e.g. having four-zone regenerative action having an amplifying gate structure, e.g. cascade (Darlington) configuration
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Abstract
The invention discloses a thyristor chip and a manufacturing method thereof, wherein the chip comprises an N-type base region and a P-type base region which are positioned on an anode P-type layer; the cathode N-type region is positioned in the upper surface of the P-type base region; a cathode metal over the cathode emission N-type region; amplifying gate metal and central gate metal on the surface of the P-type base region; a first dielectric thin film layer of a specified thickness over the enlarged gate metal; and an anode metal under the anode P-type layer. The invention can achieve the purpose of isolating the amplifying gate level from the cathode during packaging without suspending the amplifying gate level in the air by a traditional structure, can improve the di/dt tolerance, is beneficial to improving the performance of the thyristor, prolongs the service life, reduces the process complexity and reduces the process cost.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a thyristor chip, a thyristor and a manufacturing method thereof.
Background
A generally adopted flat plate type packaging structure of the high-power thyristor discrete device with the current level of more than 300A and the voltage level of more than 1200V is shown in figure 1, and a tube cover 1, an upper molybdenum sheet 2, a thyristor chip 3, a lower molybdenum sheet 4 and a tube seat 15 are arranged from top to bottom in sequence, and the components are tightly pressed by applying force of dozens of kilonewtons in the packaging process.
The thyristor chip 3 is a three-terminal four-layer semiconductor device, as shown in fig. 2, three terminals of a conventional thyristor are an anode metal 31, a cathode metal 32, and a gate metal 33 (including an amplifying gate metal 34), and four layers are: an anode P type layer 35 and a low-resistance N type base region 36 of the deep diffusion layer, a P type base region 37 of the deep diffusion layer and a high-concentration cathode N type region 38 are formed by diffusion, ohmic contact type metal electrodes are led out from the anode P type layer 35 and the cathode N type region 38 and are used as anode and cathode terminals respectively, and an ohmic contact type metal electrode is led out from the P type base region 37 and is used as a gate electrode.
There are three electrodes for the thyristor chip: the anode, the cathode and the gate pole, and a positive trigger signal is added between the cathode and the gate pole to control the conduction of the thyristor. The gate electrode and the cathode are positioned on the same surface, the surfaces of the gate electrode and the cathode need to be covered with metal films, the metal films are used for leading out electrodes and realizing ohmic contact, and the gate electrode metal layer and the cathode metal layer need to be separated. As shown in fig. 3, the schematic diagram of the gate cathode surface structure generally shows that the high-power thyristor is divided into a central gate level and an amplifying gate level, the central gate is connected with an external trigger circuit through a gate component, and the amplifying gate can reduce the turn-on time, reduce the turn-on current, improve the turn-on di/dt and the like. As shown in fig. 1, the central gate is isolated from the cathode by the opening of the upper mo strip, and the enlarged gate requires a special structure to achieve isolation from the cathode.
The structure for realizing the isolation of an amplifying gate pole and a cathode and the manufacturing method in the prior art mainly comprise the following three types:
1) the thickness of the cathode metal 32 is 30um, the thickness of the enlarged gate metal 34 is 10um, and the height difference between the enlarged gate metal 34 and the cathode metal 32 is 20 um. During packaging, the upper molybdenum sheet 2 is a flat molybdenum sheet with the thickness of 3mm, and the amplifying gate electrode is suspended due to the height difference between the amplifying gate electrode metal and the cathode metal, so that the amplifying gate electrode is isolated from the cathode, as shown in fig. 4. The manufacturing method for realizing the structure comprises the following steps: the silicon wafer is diffused to realize the doping of the anode P-type layer 35, the P-type base region 37 and the cathode N-type region 38 → the evaporation/sputtering deposits a 20 μm metal layer on the cathode surface of the silicon wafer → the photolithography process leaves a central gate and a metal layer of the cathode → the evaporation/sputtering deposits a 10 μm metal layer on the cathode surface of the silicon wafer → the photolithography process leaves a central gate, a cathode and an enlarged metal layer of the gate, and the structure shown in 4 is realized.
The defects are that the process is complex, and the gate cathode is easy to be short-circuited.
2) The height difference between the silicon chip layer amplification gate and the cathode is 20 mu m, the metal layer is consistent in height, the upper molybdenum sheet is a flat molybdenum sheet with the thickness of 3mm during packaging, and the amplification gate is suspended. Aluminum diffusion is carried out on a silicon wafer to form an anode P-type layer 35 and a P-type base region 37 → a groove with the depth of 20 microns is dug out in a chemical wet grooving process of an amplifying gate region → a metal layer with the depth of 20 microns is deposited on the cathode surface of the silicon wafer by evaporation/sputtering → a photoetching process flows out of a central gate, an amplifying gate and a cathode metal layer, and as shown in figure 5, silicon in the amplifying gate region is subjected to primary photoetching and chemical corrosion, and a primary metal layer is deposited and is subjected to primary photoetching.
The defects are that the process is complex, and the gate cathode is easy to be short-circuited.
3) The silicon chip layer and the metal layer of the amplifying gate electrode and the cathode have the same height of 30 mu m, the upper molybdenum sheet has through hole grooves or blind hole grooves which have the same pattern with the amplifying gate electrode of the tube core during packaging, the thickness of the molybdenum sheet is 3mm, and the blind hole grooves are 1 mm. The amplifying gate pole is suspended. The silicon chip is diffused to realize the doping of the anode P type layer 35, the P type base region 37 and the cathode N type region 38 → a 30 μm metal layer is deposited on the cathode surface of the silicon chip by evaporation/sputtering → a central gate pole, an amplifying gate pole and a cathode metal layer are reserved by the photoetching process → a groove with the depth of 1mm, which is consistent with the pattern of the amplifying gate pole, is formed on the molybdenum piece towards the die surface of the thyristor. As shown in fig. 6. The method is realized by forming a blind hole groove or a through hole groove which is consistent with the pattern of the amplified gate pole on the upper molybdenum sheet.
The disadvantages are high cost, alignment of the upper molybdenum sheet pattern with the die pattern, assembly difficulties, and the tendency for the gate cathode to short circuit.
Achieving effective isolation of the amplifying gate from the cathode without greatly increasing the cost is a technical problem that those skilled in the art want to solve, and therefore a new structure and a manufacturing method for achieving effective isolation of the amplifying gate from the cathode without greatly increasing the cost are needed.
Disclosure of Invention
The invention solves the technical problem of effective isolation of the amplifying gate pole and the cathode while reducing the cost, improves the electrical property of the thyristor and prolongs the service life.
The invention provides a thyristor chip, comprising:
the N-type base region is positioned on the anode P-type layer, and the P-type base region is positioned on the N-type base region;
the cathode N-type region is positioned in a partial region of the P-type base region, and the upper surface of the cathode N-type region is flush with the upper surface of the P-type base region, wherein the cathode N-type region comprises a cathode emission N-type region and a gate electrode N-type region;
the cathode metal is positioned on the cathode emission N-type region and exposes part of the upper surface of the cathode emission N-type region;
the amplifying gate electrode metal is positioned on the surface of the P-type base region and is simultaneously contacted with the P-type base region and the gate electrode N-type region, and the central gate electrode metal is positioned on the upper surface of the P-type base region and is not contacted with the gate electrode N-type region;
a first dielectric thin film layer of a specified thickness over the enlarged gate metal;
and an anode metal under the anode P-type layer.
In an embodiment of the present invention, it is,
the thickness of the amplifying gate metal is the same as that of the cathode metal, and the thickness of the first dielectric thin film layer is far smaller than that of the amplifying gate metal and that of the cathode metal.
In an embodiment of the present invention, it is,
the first dielectric film includes at least one of a DLC film, a silicon nitride film or a silicon oxide film.
In an embodiment of the present invention, it is,
and a second dielectric thin film layer with a designated thickness is further arranged on the upper surface of the P-type base region which is not covered by the cathode metal, the amplifying gate electrode metal and the central gate electrode metal, the thickness of the second dielectric thin film layer is far smaller than the thicknesses of the amplifying gate electrode metal and the cathode metal, and the second dielectric thin film comprises a DLC thin film.
In an embodiment of the present invention, it is,
the designated thickness of the first dielectric DLC film layer is set to be 20-300 nm;
the designated thickness of the second medium thin film layer is set to be 20-500 nm;
the total thickness of the chip is set to be 1.2 mm;
the thicknesses of the amplifying gate metal and the cathode metal are set to be 30 mu m;
the carrier concentration of the N-type base region is set to be 1013cm-3；
The anode P-type layer and the P-type base region are doped with aluminum, and the concentration of current carriers is set to be 1014cm-3～1016cm-3；
The cathode N-type region is doped with phosphorus, and the carrier concentration is set to be 1019cm-3；
The anode metal, the cathode metal and the gate metal are made of aluminum.
The present invention also provides a thyristor,
a thyristor chip comprising any of the above.
The invention also provides a manufacturing method of the thyristor chip, which comprises the following steps:
synchronously forming an anode P-type layer and a P-type base region on the lower surface and the upper surface of the N-type substrate respectively;
forming a cathode N-type region with the upper surface flush with the upper surface of the P-type base region in the partial region of the P-type base region, wherein the cathode N-type region comprises a cathode emission N-type region and a gate electrode N-type region;
forming ohmic contact electrode metal on the cathode emission N-type region, the P-type base region, the gate electrode N-type region and below the anode P-type layer synchronously, wherein cathode metal exposing part of the upper surface of the cathode emission N-type region is formed on the cathode emission N-type region, amplified gate electrode metal simultaneously contacting with the P-type base region and the gate electrode N-type region is formed on the surface of the P-type base region, central gate electrode metal not contacting with the gate electrode N-type region is formed on the upper surface of the P-type base region, and anode metal is formed below the anode P-type layer;
and forming a first medium thin film layer with a designated thickness on the amplifying gate metal through a deposition process.
In an embodiment of the present invention, it is,
the deposition process comprises a chemical vapor deposition process, a physical vapor deposition process, an ion beam deposition process, a filtering type vacuum cathode arc process, a pulse laser deposition process and a magnetron sputtering process, wherein the chemical vapor deposition process comprises a PECVD process;
and a second dielectric thin film layer with a specified thickness is also arranged on the upper surface of the P-type base region which is not covered by the cathode metal, the amplifying gate electrode metal and the central gate electrode metal.
In an embodiment of the present invention, it is,
the thickness of the amplifying gate metal is the same as that of the cathode metal;
the thickness of the first dielectric thin film layer and the thickness of the second dielectric thin film layer are both far smaller than the thickness of the amplification gate metal and the thickness of the cathode metal;
the first dielectric film comprises at least one of a DLC film, a silicon nitride film or a silicon oxide film;
the second dielectric film comprises a DLC film.
In an embodiment of the present invention, it is,
the designated thickness of the first dielectric DLC film layer is set to be 20-300 nm;
the designated thickness of the second medium thin film layer is set to be 20-500 nm;
the PECVD process parameters for depositing the DLC film comprise the following settings:
the vacuum pressure of the deposition chamber is set to 10-6Pa；
The flow range of the alkane gas is set to be 0-500 sccm;
setting the pressure intensity range in the deposition cavity to be 0-66.5 Pa;
the radio frequency source is set to 13.56 MHz;
setting the time range of the deposition process to be 3-10 minutes;
the temperature of the chip is kept constant in the deposition process, and the temperature of the chip in the deposition process is less than or equal to 300 ℃.
The invention provides a manufacturing method of a thyristor, which comprises the manufacturing method of the thyristor chip in any one of the above contents.
One or more embodiments of the present invention may have the following advantages over the prior art:
1. the invention realizes the suspension of the amplifying gate level by applying DLC (diamond-like carbon) film material to the thyristor structure without the height difference of a metal layer, the height difference of a silicon chip layer or a molybdenum sheet slotting structure, thereby achieving the purpose of isolating the amplifying gate level from a cathode during packaging.
2. After the structure of the invention is adopted, the heights of the central gate level, the amplifying gate level and the cathode metal layer are consistent, and the molybdenum sheet is a complete and flat molybdenum sheet, so that the risks of contamination, gas breakdown, gate-cathode short circuit caused by dislocation of a molybdenum sheet graph and a tube core graph and the like between the amplifying gate level and the cathode metal layer and further failure of the thyristor are reduced, the isolating effect of the amplifying gate level and the cathode is improved, the performance of the thyristor is improved, and the service life is prolonged.
3. After the structure is adopted, the process steps of electrode precipitation or metal layer etching are reduced, or the process of silicon wafer etching is reduced, or the process of molybdenum sheet slotting is reduced, the process complexity is reduced, and the process cost is reduced.
4. The invention can improve the heat radiation capability of the thyristor and the di/dt resistance capability of the thyristors of various types, sizes and structures by applying the DLC (diamond-like carbon) film material to the thyristor structure, is favorable for improving the performance of the thyristor and prolongs the service life.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 shows an exploded view of a planar thyristor package;
FIG. 2 is a schematic diagram of a conventional thyristor chip structure;
FIG. 3 is a schematic diagram of a gate cathode structure in a conventional thyristor chip;
FIG. 4 is a schematic structural diagram of an enlarged gate-cathode isolation scheme 1 in a conventional thyristor chip;
FIG. 5 is a schematic diagram of an enlarged gate-cathode isolation scheme 2 for a conventional thyristor chip;
FIG. 6 is a schematic diagram of an enlarged gate-cathode isolation scheme 3 for a conventional thyristor chip;
FIG. 7 is a schematic structural diagram of a thyristor chip according to an embodiment of the invention;
FIG. 8 is a schematic structural diagram of a thyristor chip according to another embodiment of the invention;
FIG. 9 is a schematic flow chart of a method for fabricating a thyristor chip according to an embodiment of the invention;
fig. 10-12 are schematic structural diagrams of the thyristor chip performing step 3 according to an embodiment of the invention;
fig. 13-14 are schematic structural diagrams of a thyristor chip for performing step 4 according to an embodiment of the invention;
fig. 15 is a schematic diagram of a PEVCD process according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the following detailed description of the present invention with reference to the accompanying drawings is provided to fully understand and implement the technical effects of the present invention by solving the technical problems through technical means. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
First embodiment
Fig. 7 is a schematic structural diagram of a thyristor chip according to an embodiment of the invention, and as shown in fig. 7, the embodiment provides a thyristor chip, including: anode metal 31, cathode metal 32, center gate metal 33, amplifying gate metal 34, anode P-type layer 35, N-type base region 36, P-type base region 37, cathode N-type region 38 (including cathode emitter N-type region 381 and gate N-type region 382), first DLC thin film layer 391.
A Diamond-like carbon (DLC) film is a metastable type film of amorphous carbon containing a certain amount of Diamond bonds (sp3), the main component of the film is carbon, and carbon atoms therein are bonded by covalent bonds, and the film has excellent properties such as high infrared transmittance, high hardness, low friction coefficient, high corrosion resistance, high electrical resistivity, high thermal conductivity, high chemical stability, and the like, and has many applications in the field of power semiconductor chip manufacturing.
The embodiment provides a thyristor chip, including:
an N-type base region 36 located above the anode P-type layer 35, and a P-type base region 37 located above the N-type base region 36;
a cathode N-type region 38 located in a partial region of the P-type base region 37 and having an upper surface flush with an upper surface of the P-type base region 37, wherein the cathode N-type region 38 includes a cathode emitter N-type region 381 and a gate N-type region 382;
a cathode metal 32 overlying cathode emission N-type region 381 and exposing a portion of the upper surface of cathode emission N-type region 381;
an enlarged gate metal 34 on the upper surface of the P-type base region 37 and in contact with both the P-type base region 37 and the gate N-type region 382, and a central gate metal 33 on the surface of the P-type base region 37 and not in contact with the gate N-type region 382;
a first dielectric thin film layer 391 of a specified thickness overlying the enlarged gate metal 34;
and an anode metal 31 under the anode P-type layer 35.
Specifically, the 4 layers of materials of the thyristor chip of the present embodiment are all made of semiconductor material silicon, and the total thickness of the thyristor chip is set to be 1.2 mm. An N-type base region 36 is arranged on the anode P-type layer 35, and a P-type base region 37 is arranged on the N-type base region 36; a cathode N-type region 38 which does not completely cover the P-type base region 37 is arranged in the upper surface of the P-type base region 37, wherein the cathode N-type region 38 comprises a cathode emission N-type region 381 and a gate N-type region 382 which is closer to the center of the chip in the direction parallel to the surface of the P-type base region 37;
the anode P-type layer 35 and the P-type base region 37 are doped with aluminum, and the carrier concentration is set to 1014cm-3～1016cm-3(ii) a The carrier concentration of the N-type base region 36 is set to 1013cm-3(ii) a The cathode N-type region 38 is doped with phosphorus and has a carrier concentration of 1019cm-3；
A cathode metal 32 not entirely covering the cathode-emitter-N-type region 381 is disposed on the cathode-emitter-N-type region 381, an enlarged gate metal 34 is disposed on the upper surface of the P-base region 37 and is in contact with the P-base region 37 and the gate-N-type region 382, a central gate metal 33 is disposed on the surface of the P-base region 37 and is not in contact with the gate-N-type region 382, the enlarged gate metal 34 and the cathode metal 32 have the same thickness of 30 μm, an anode metal 31 is disposed under the anode P-type layer 35, and the anode metal, the cathode metal and the gate metal are all made of aluminum. The values of doping elements, concentration, preset thickness and the like of each region can be selected according to actual needs.
A first dielectric thin film layer 391 of a prescribed thickness is provided over the amplifying gate metal 34, the first dielectric thin film 391 including at least one of a DLC thin film, a silicon nitride or a silicon oxide thin film. The designated thickness range of the DLC film layer is set to be 20-300 nm, and the preferred range is set to be 100-200 nm. The first dielectric thin film layer 391 thickness is much less than the thickness of the enlarged gate metal 34 and cathode metal 32. In this embodiment, a DLC (diamond-like carbon) film is deposited on the amplifying gate metal 34, the DLC film is a good insulating dielectric material, and the set thickness is a nano-electrode, which is much smaller than the thicknesses of the metal layer and the molybdenum sheet, and much smaller than the tolerance between the metal layer and the molybdenum sheet, and the thyristor chip does not need to adopt a metal layer height difference, a silicon layer height difference, or a molybdenum sheet grooving structure to perform amplifying gate suspension processing, so that the purpose of isolating the amplifying gate from the cathode can be achieved, and the purpose of contacting the cathode metal layer with the molybdenum sheet can also be achieved. The invention can reduce the complexity and cost of the process and reduce the risk of short circuit of the gate cathode. The DLC film layer 391 is arranged, after the structure of the embodiment is adopted, the heights of the central gate-level metal 33, the amplifying gate-level metal 34 and the cathode metal 32 are all 30 micrometers, the molybdenum sheet is a complete and flat molybdenum sheet, the gate cathode short circuit caused by contamination, gas breakdown, dislocation of a molybdenum sheet pattern and a tube core pattern and the like between the amplifying gate-level metal and the cathode metal layer is reduced, the risk of failure of the thyristor is further caused, the isolating effect of the amplifying gate-level metal and the cathode is improved, the performance of the thyristor is favorably improved, and the service life is prolonged.
In summary, one or more embodiments of the present invention have the following advantages:
1. the invention realizes the suspension of the amplifying gate level by applying DLC (diamond-like carbon) film material to the thyristor structure without the height difference of a metal layer, the height difference of a silicon chip layer or a molybdenum sheet slotting structure, thereby achieving the purpose of isolating the amplifying gate level from a cathode during packaging.
2. After the structure of the invention is adopted, the heights of the central gate level, the amplifying gate level and the cathode metal layer are consistent, and the molybdenum sheet is a complete and flat molybdenum sheet, so that the risks of contamination, gas breakdown, gate-cathode short circuit caused by dislocation of a molybdenum sheet graph and a tube core graph and the like between the amplifying gate level and the cathode metal layer and further failure of the thyristor are reduced, the isolating effect of the amplifying gate level and the cathode is improved, the performance of the thyristor is improved, and the service life is prolonged.
3. After the structure is adopted, the process steps of electrode precipitation or metal layer etching are reduced, or the process of silicon wafer etching is reduced, or the process of molybdenum sheet slotting is reduced, the process complexity is reduced, and the process cost is reduced.
Second embodiment
Fig. 8 is a schematic structural diagram of a thyristor chip according to another embodiment of the invention, and as shown in fig. 8, this embodiment provides a thyristor chip, including: an anode metal 31, a cathode metal 32, a central gate metal 33, an amplifying gate metal 34, an anode P-type layer 35, an N-type base region 36, a P-type base region 37, a cathode N-type region 38 (including a cathode emission N-type region 381 and a gate N-type region 382), a first dielectric thin film layer 391 and a second dielectric thin film layer 392.
The present embodiment provides another thyristor chip, which is improved on the basis of the first embodiment, and a second dielectric thin film layer 392 with a specified thickness is further disposed on the upper surface of the P-type base region 37 not covered by the cathode metal 32, the amplifying gate metal 34, and the central gate metal 33, and the specified thickness of the second dielectric thin film layer 392 is set to be 20 to 500 nm. The second dielectric film comprises a DLC film.
According to the invention, the DLC (diamond-like carbon) film material is applied to the thyristor chip structure, and the DLC film has high thermal conductivity, so that the heat dissipation capability of the thyristor can be improved, the di/dt resistance capability of the thyristors of various types, sizes and structures can be improved, the performance of the thyristor can be improved, and the service life of the thyristor can be prolonged.
Third embodiment
The present embodiment provides a thyristor, which includes the thyristor chip with any one of the structures in the first or second embodiments, and has the advantages of the first or second embodiments.
Fourth embodiment
FIG. 7 is a schematic structural diagram of a thyristor chip according to an embodiment of the invention;
FIG. 9 is a schematic flow chart of a method for fabricating a thyristor chip according to an embodiment of the invention;
fig. 10-12 are schematic structural diagrams of the thyristor chip performing step 3 according to an embodiment of the invention;
fig. 13-14 are schematic structural diagrams of a thyristor chip for performing step 4 according to an embodiment of the invention;
fig. 15 is a schematic diagram of a PEVCD process according to an embodiment of the invention.
As shown in fig. 7, the thyristor chip manufactured by the method for manufacturing a thyristor chip according to this embodiment includes: anode metal 31, cathode metal 32, central gate metal 33, amplifying gate metal 34, anode P-type layer 35, N-type base region 36, P-type base region 37, cathode N-type region 38 (including cathode emitter N-type region 381 and gate N-type region 382), first dielectric thin film layer 391.
The embodiment provides a method for manufacturing a thyristor chip, which comprises the following steps:
step 1, synchronously forming an anode P-type layer 35 and a P-type base region 37 on the lower surface and the upper surface of an N-type substrate respectively,
and 2, forming a cathode N-type region 38 with the upper surface flush with the upper surface of the P-type base region 37 in a partial region of the P-type base region 37, wherein the cathode N-type region 38 comprises a cathode emission N-type region 381 and a gate N-type region 382 closer to the center of the chip in a direction parallel to the surface of the P-type base region 37.
Specifically, after the surface lithography process on the P-type base region 37, ions are implanted at corresponding positions to form a cathode N-type region 38 that does not completely cover the P-type base region 37, wherein the cathode N-type region 38 includes a cathode emitter N-type region 381 and a gate N-type region 382 closer to the center of the chip in a direction parallel to the surface of the P-type base region 37.
And step 3, simultaneously forming ohmic contact electrode metal on the cathode emission N-type region 381, the P-type base region 37 and the gate electrode N-type region 382 and below the anode P-type layer 35, wherein the cathode metal 32 exposing part of the upper surface of the cathode emission N-type region 381 is formed on the cathode emission N-type region 381, the amplified gate electrode metal 34 simultaneously contacting with the P-type base region 37 and the gate electrode N-type region 382 is formed on the upper surface of the P-type base region 37, the central gate electrode metal 33 not contacting with the gate electrode N-type region 382 is formed on the upper surface of the P-type base region 37, and the anode metal is formed below the anode P-type layer.
Specifically, a metal layer is deposited on the upper surface of the P-type base region 37 of the thyristor silicon-based chip by an evaporation/sputtering process, as shown in fig. 10; then, a photoresist layer consistent with a target pattern is obtained on the metal layer through a photoetching process, as shown in FIG. 11; the metal layer at the non-target position is removed by etching to obtain a metal layer with a target pattern, and the photoresist is removed, so as to obtain a cathode metal 32 on the cathode emitter N-type region 381 without completely covering the cathode emitter N-type region 381, an enlarged gate metal 34 on the upper surface of the P-type base region 37 and in contact with the P-type base region 37 and the gate N-type region 382, and a central gate metal 33 on the upper surface of the P-type base region 37 and not in contact with the gate N-type region 382, as shown in fig. 12. The thicknesses of the enlarged gate metal 34 and the cathode metal 32 are the same and are set to 30um, and the other specified thicknesses and doping concentration ranges are set according to the parameters of the first embodiment. An anode metal 31 is deposited under the anode P-type layer 35 at the same time of forming a metal layer on the upper surface of the P-type base region 37.
Step 4, a first dielectric thin film layer 391 of a specified thickness is formed over the enlarged gate metal 34 by a deposition process.
Specifically, photoresist is coated on the surfaces of the enlarged gate metal 34, the central gate metal 33, the cathode metal 32 and the P-type base region 37 which is not covered by the metal, as shown in fig. 13, and a first dielectric thin film layer 391 with a designated thickness is deposited on the photoresist by a PECVD process, as shown in fig. 14. The first dielectric thin film layer 391, which is much thinner than the thicknesses of the amplifying gate metal 34 and the cathode metal 32, comprises at least one of a DLC film, a silicon nitride or a silicon oxide film. As shown in FIG. 15, the PECVD process places the thyristor chip to be deposited with DLC film on the heating plate, and the deposition chamber is evacuated to 10 deg.C-6Pa; setting the flow rate of the alkane gas to be 0-500 sccm, and spraying the alkane gas into the cavity; then the pressure intensity in the cavity is automatically adjusted to be 0-500 mTorr, namely 0-66.5 through the vacuum adjusting valvePa; the alkane gas sprayed into the cavity is decomposed into C under the excitation of a 13.56MHz radio frequency sourcenHm+(ii) a The radio frequency power supply is arranged at two ends of the parallel plate capacitor, the heating plate is used as a cathode and is grounded, the deposition chamber wall is used as an anode, and the areas of the cathode plate and the anode plate are different; under the excitation of a radio frequency source, the movement rates of ions and electrons in the plasma are different, the negative bias voltage of 200-1000V exists between the polar plates due to the different polar plate areas, and CnHm+Bombarding a substrate material at a high speed under the action of negative bias voltage, obtaining a DLC film with the thickness of about 20-300 nm in the deposition process time of 3-10 min, setting the heating plate temperature to be constant in the deposition process, setting the chip temperature to be not more than 300 ℃ in the deposition process, and causing a deposited diamond structure (sp) if the temperature is too high3) Towards the graphitic structure (sp)2) And (4) converting.
The deposition process further comprises a chemical vapor deposition process, a physical vapor deposition process, an ion beam deposition process, a filtering type vacuum cathode arc process, a pulsed laser deposition process and a magnetron sputtering process, wherein the chemical vapor deposition process comprises a PECVD process.
In summary, the present embodiment has the following advantages:
1. in the embodiment, the thyristor structure manufactured by the method for manufacturing the thyristor chip by adopting the DLC (diamond-like carbon) film material does not need the metal layer height difference, the silicon layer height difference or the molybdenum sheet slotting structure to realize the suspension of the amplifying gate level, and the aim of isolating the amplifying gate level from the cathode in packaging can be fulfilled.
2. After the thyristor structure manufactured by the manufacturing method of the thyristor chip made of the DLC (diamond-like carbon) film material, the heights of the central gate level, the amplifying gate level and the cathode metal layer are consistent, and the molybdenum sheet is a complete and flat molybdenum sheet, so that the risk of gate cathode short circuit caused by contamination, gas breakdown, dislocation of a molybdenum sheet graph and a tube core graph and the like between the amplifying gate level and the cathode metal layer and further thyristor failure is reduced, the isolating effect of the amplifying gate level and the cathode is improved, the performance of the thyristor is favorably improved, and the service life is prolonged.
3. After the manufacturing method of the thyristor chip made of the DLC (diamond-like carbon) film material is adopted, the process steps of depositing or etching a metal layer are reduced, or the process of etching a silicon wafer is reduced, or the process of slotting a molybdenum sheet is reduced, the process complexity is reduced, and the process cost is reduced.
Fifth embodiment
As shown in fig. 8, the present embodiment provides a thyristor chip manufactured by the method for manufacturing a thyristor chip, including: an anode metal 31, a cathode metal 32, a central gate metal 33, an amplifying gate metal 34, an anode P-type layer 35, an N-type base region 36, a P-type base region 37, a cathode N-type region 38 (including a cathode emission N-type region 381 and a gate N-type region 382), a first dielectric thin film layer 391 and a second dielectric thin film layer 392.
The embodiment provides another method for manufacturing a thyristor chip, which is improved on the basis of the fourth embodiment, and a second dielectric thin film layer 392 with a specified thickness is further deposited on the upper surface of the P-type base region 37 which is not covered by the cathode metal 32, the amplifying gate metal 34 and the central gate metal 33 through a PEVCD process, wherein the specified thickness of the second dielectric thin film layer 392 is set to be 20-500 nm. The second dielectric film comprises a DLC film.
In the embodiment, the DLC (diamond-like carbon) film material is applied to the thyristor chip structure, and the DLC film has high thermal conductivity, so that the heat dissipation capacity of the thyristor can be improved, the di/dt resistance of thyristors of various types, sizes and structures can be improved, the performance of the thyristor can be improved, and the service life of the thyristor can be prolonged.
Sixth embodiment
This embodiment provides a method for manufacturing a thyristor, including the method for manufacturing a thyristor chip according to any one of the fourth and fifth embodiments, and the advantages are as described in the fourth and fifth embodiments.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as disclosed, and that the scope of the invention is not to be limited to the particular embodiments disclosed herein but is to be accorded the full scope of the claims.
Claims (11)
1. A thyristor chip, comprising:
the N-type base region is positioned on the anode P-type layer, and the P-type base region is positioned on the N-type base region;
the cathode N-type region is positioned in a partial region of the P-type base region, and the upper surface of the cathode N-type region is flush with the upper surface of the P-type base region, wherein the cathode N-type region comprises a cathode emission N-type region and a gate electrode N-type region;
the cathode metal is positioned on the cathode emission N-type region and exposes part of the upper surface of the cathode emission N-type region;
the amplifying gate electrode metal is positioned on the surface of the P-type base region and is simultaneously contacted with the P-type base region and the gate electrode N-type region, and the central gate electrode metal is positioned on the upper surface of the P-type base region and is not contacted with the gate electrode N-type region;
a first dielectric thin film layer of a specified thickness over the enlarged gate metal;
and an anode metal under the anode P-type layer.
2. The thyristor chip of claim 1,
the thickness of the amplifying gate metal is the same as that of the cathode metal, and the thickness of the first dielectric thin film layer is far smaller than that of the amplifying gate metal and that of the cathode metal.
3. The thyristor chip of claim 2,
the first dielectric film includes at least one of a DLC film, a silicon nitride film or a silicon oxide film.
4. The thyristor chip of claim 3,
and a second dielectric thin film layer with a designated thickness is further arranged on the upper surface of the P-type base region which is not covered by the cathode metal, the amplifying gate electrode metal and the central gate electrode metal, the thickness of the second dielectric thin film layer is far smaller than the thicknesses of the amplifying gate electrode metal and the cathode metal, and the second dielectric thin film comprises a DLC thin film.
5. The thyristor chip of claim 4,
the designated thickness of the first dielectric DLC film layer is set to be 20-300 nm;
the designated thickness of the second medium thin film layer is set to be 20-500 nm;
the total thickness of the chip is set to be 1.2 mm;
the thicknesses of the amplifying gate metal and the cathode metal are set to be 30 mu m;
the carrier concentration of the N-type base region is set to be 1013cm-3；
The anode P-type layer and the P-type base region comprise aluminum element doping, and the carrier concentration is set to be 1014cm-3～1016cm-3；
The cathode N-type region comprises phosphorus element doping, and the carrier concentration is set to be 1019cm-3；
The anode metal, the cathode metal and the gate metal comprise aluminum.
6. A thyristor, characterized in that,
a thyristor chip comprising the thyristor of any one of claims 1 to 5.
7. A method for manufacturing a thyristor chip is characterized by comprising the following steps:
synchronously forming an anode P-type layer and a P-type base region on the lower surface and the upper surface of the N-type substrate respectively;
forming a cathode N-type region with the upper surface flush with the upper surface of the P-type base region in the partial region of the P-type base region, wherein the cathode N-type region comprises a cathode emission N-type region and a gate electrode N-type region;
forming ohmic contact electrode metal on the cathode emission N-type region, the P-type base region, the gate electrode N-type region and below the anode P-type layer synchronously, wherein cathode metal exposing part of the upper surface of the cathode emission N-type region is formed on the cathode emission N-type region, amplified gate electrode metal simultaneously contacting with the P-type base region and the gate electrode N-type region is formed on the surface of the P-type base region, central gate electrode metal not contacting with the gate electrode N-type region is formed on the upper surface of the P-type base region, and anode metal is formed below the anode P-type layer;
and forming a first medium thin film layer with a designated thickness on the amplifying gate metal through a deposition process.
8. The method of claim 7,
the deposition process comprises a chemical vapor deposition process, a physical vapor deposition process, an ion beam deposition process, a filtering type vacuum cathode arc process, a pulse laser deposition process and a magnetron sputtering process, wherein the chemical vapor deposition process comprises a PECVD process;
and a second dielectric thin film layer with a specified thickness is also arranged on the upper surface of the P-type base region which is not covered by the cathode metal, the amplifying gate electrode metal and the central gate electrode metal.
9. The method of claim 8,
the thickness of the amplifying gate metal is the same as that of the cathode metal;
the thickness of the first dielectric thin film layer and the thickness of the second dielectric thin film layer are both far smaller than the thickness of the amplification gate metal and the thickness of the cathode metal;
the first dielectric film comprises at least one of a DLC film, a silicon nitride film or a silicon oxide film;
the second dielectric film comprises a DLC film.
10. The method of claim 9,
the designated thickness of the first dielectric DLC film layer is set to be 20-300 nm;
the designated thickness of the second medium thin film layer is set to be 20-500 nm;
the PECVD process parameters for depositing the DLC film comprise the following settings:
the vacuum pressure of the deposition chamber is set to 10-6Pa；
The flow range of the alkane gas is set to be 0-500 sccm;
setting the pressure intensity range in the deposition cavity to be 0-66.5 Pa;
the radio frequency source is set to 13.56 MHz;
setting the time range of the deposition process to be 3-10 minutes;
the temperature of the chip is kept constant in the deposition process, and the temperature of the chip in the deposition process is less than or equal to 300 ℃.
11. A method for fabricating a thyristor, which is characterized in that,
a method of making a thyristor chip comprising any one of claims 7 to 10.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08316255A (en) * | 1995-05-12 | 1996-11-29 | Fuji Electric Co Ltd | Pressure contact flat-type semiconductor device and its manufacture |
| JP2000332231A (en) * | 1999-05-19 | 2000-11-30 | Mitsubishi Electric Corp | Semiconductor device |
| CN104409491A (en) * | 2013-08-26 | 2015-03-11 | 湖北台基半导体股份有限公司 | High-voltage quick-turn-on thyristor and manufacturing method thereof |
| CN111244172A (en) * | 2020-01-18 | 2020-06-05 | 常州瑞华新能源科技有限公司 | Improved chip for welding module |
| CN212659547U (en) * | 2020-07-14 | 2021-03-05 | 株洲中车时代半导体有限公司 | Thyristor chip and thyristor |
-
2020
- 2020-07-14 CN CN202010677130.4A patent/CN111883587A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08316255A (en) * | 1995-05-12 | 1996-11-29 | Fuji Electric Co Ltd | Pressure contact flat-type semiconductor device and its manufacture |
| JP2000332231A (en) * | 1999-05-19 | 2000-11-30 | Mitsubishi Electric Corp | Semiconductor device |
| CN104409491A (en) * | 2013-08-26 | 2015-03-11 | 湖北台基半导体股份有限公司 | High-voltage quick-turn-on thyristor and manufacturing method thereof |
| CN111244172A (en) * | 2020-01-18 | 2020-06-05 | 常州瑞华新能源科技有限公司 | Improved chip for welding module |
| CN212659547U (en) * | 2020-07-14 | 2021-03-05 | 株洲中车时代半导体有限公司 | Thyristor chip and thyristor |
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