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JP3184207B2 - Ceramic multilayer substrate and method of manufacturing the same - Google Patents

Ceramic multilayer substrate and method of manufacturing the same

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Publication number
JP3184207B2
JP3184207B2 JP24625890A JP24625890A JP3184207B2 JP 3184207 B2 JP3184207 B2 JP 3184207B2 JP 24625890 A JP24625890 A JP 24625890A JP 24625890 A JP24625890 A JP 24625890A JP 3184207 B2 JP3184207 B2 JP 3184207B2
Authority
JP
Japan
Prior art keywords
pin
ceramic
multilayer substrate
firing
ceramic multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP24625890A
Other languages
Japanese (ja)
Other versions
JPH04125994A (en
Inventor
寛 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Chemi Con Corp
Original Assignee
Nippon Chemi Con Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Chemi Con Corp filed Critical Nippon Chemi Con Corp
Priority to JP24625890A priority Critical patent/JP3184207B2/en
Publication of JPH04125994A publication Critical patent/JPH04125994A/en
Application granted granted Critical
Publication of JP3184207B2 publication Critical patent/JP3184207B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、セラミック多層基板に端子ピンを立設する
製造方法の改良、およびこの方法によって製造されるセ
ラミック多層基板に関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a manufacturing method for erecting terminal pins on a ceramic multilayer substrate, and a ceramic multilayer substrate manufactured by this method.

[従来の技術] 近年の電子回路の小型化・高密度化に対応して、セラ
ミック基板の多層化が進められているが、この目的によ
り適切に適合するものとして、近年では特に低温焼成基
板が注目されている。
[Prior Art] In recent years, ceramic substrates have been multi-layered in response to miniaturization and densification of electronic circuits. Attention has been paid.

従来の基板材料としては、熱放散、熱膨脹係数、寸法
安定性等の観点から優れた特性を有するアルミナ多層基
板が重要な位置を占めていた。しかしながら、アルミナ
の焼成条件としては一般に1500℃以上の高温を必要とす
るため、導体材料としては耐熱性金属であるMoやW等に
使用範囲が限定されていた。また、高温焼成に耐える必
要があるため、抵抗体材料等についても一定の制約が余
儀なくされていた。
As a conventional substrate material, an alumina multilayer substrate having excellent characteristics from the viewpoint of heat dissipation, thermal expansion coefficient, dimensional stability, and the like occupies an important position. However, since the firing conditions of alumina generally require a high temperature of 1500 ° C. or more, the range of use has been limited to heat-resistant metals such as Mo and W as conductive materials. In addition, since it is necessary to withstand high-temperature firing, certain restrictions have been imposed on the resistor material and the like.

このようなアルミナ多層基板の問題点を克服し、導体
材料、抵抗体材料等の電子部品の使用範囲拡大を図るべ
く、焼成温度が一般に900℃程度と低くても十分な品質
の基板を作製し得る材料の開発が行われ、この結果近年
では、700℃以下〜1000℃程度でも焼成できるガラス粉
末等のような幾種かの材料を用いることにより、例えば
多層配線基板として基板と導体ペーストとを同時に焼成
できる低温焼成基板が実用化されている。一般に低温焼
成基板は、導体のスクリーン印刷が可能であり、高伝導
度を有し、高周波特性に優れる等の利点を有する。
In order to overcome such problems of the alumina multilayer substrate and expand the range of use of electronic components such as conductor materials and resistor materials, a substrate of sufficient quality was manufactured even at a low firing temperature of about 900 ° C. In recent years, by using several materials such as glass powder that can be fired even at 700 ° C. or less to about 1000 ° C., for example, a substrate and a conductive paste can be used as a multilayer wiring board. Low-temperature fired substrates that can be fired simultaneously have been put to practical use. In general, low-temperature fired substrates have advantages such as the ability to screen print conductors, high conductivity, and excellent high frequency characteristics.

このような低温焼成基板を使用することにより、導体
材料や抵抗体材料の使用範囲が拡大され、より高性能の
基板を提供することができるため、これと共に基板の用
途も更に拡大し、より高密度化が求められる混成集積回
路(ハイブリッドIC)等にも低温焼成基板が広く使用さ
れるに至っている。
By using such a low-temperature fired substrate, the range of use of the conductive material and the resistor material can be expanded, and a higher-performance substrate can be provided. Low-temperature fired substrates have been widely used in hybrid integrated circuits (hybrid ICs) and the like that require higher density.

一般にセラミック基板上には、外部との電気的な接続
を得るための端子ピンが所定の位置に立設されるが、従
来よりセラミック基板として多用されているものは、前
記したように酸化アルミニウムからなるアルミナ基板で
あり、アルミナ基板の焼成は1500〜1600℃の高温で行わ
れるため、焼成前のグリーンシートの段階で、ピンを所
定の位置に予め取り付けておくことはできなかった。
In general, terminal pins for obtaining electrical connection with the outside are provided upright at predetermined positions on a ceramic substrate, but those that have been frequently used as ceramic substrates in the past are made of aluminum oxide as described above. Since the alumina substrate is fired at a high temperature of 1500 to 1600 ° C., it was not possible to attach pins to predetermined positions in advance at the stage of the green sheet before firing.

従来の製造方法においては、第2図に示すように、焼
結時にアルミナ基板30の表面に形成したW、Mo等の高融
点材の導体パターン32にNiメッキ34を施し、ここにAg/C
u合金等のろう付け剤36を塗布した端子ピン38を配置し
て、ろう付けにより立設していた。このため、端子ピン
38の折り曲げや引張り等の機械的強度が十分ではなかっ
た。また、ピンの配置作業の際には、基板が焼成により
収縮し所定の接続位置が変動するため、端子ピン毎に位
置決めを行わなければならない等、工程が煩雑でもあっ
た。
In the conventional manufacturing method, as shown in FIG. 2, a Ni plating 34 is applied to a conductor pattern 32 of a high melting point material such as W or Mo formed on the surface of an alumina substrate 30 during sintering, and the Ag / C
The terminal pins 38 coated with a brazing agent 36 such as a u-alloy are arranged and are erected by brazing. For this reason, terminal pins
The mechanical strength such as bending and pulling of 38 was not enough. In addition, when arranging the pins, since the substrate shrinks due to baking and the predetermined connection position changes, the process is complicated, such as the need to position each terminal pin.

このような問題点の解決を図るべく、本出願人は先に
特願平2−194056号として、ガラスセラミック材からな
る低温焼成用セラミックから構成した多層または単層の
グリーンシートの所定位置に棒状のピンを立設し、その
後低温で焼成を行うことを特徴とする低温焼成回路基板
の製造方法を提案した。しかしながら、セラミック多層
基板にピンを立設する場合、ピン材の金属とセラミック
との間の熱膨脹係数が異なるため、ピンとセラミックと
の間に隙間が生じてしまい、接合強度が低下する傾向が
あることが分った。
In order to solve such a problem, the present applicant has previously filed Japanese Patent Application No. 2-194056 as a rod-shaped sheet at a predetermined position of a multi-layer or single-layer green sheet made of glass ceramic material for low-temperature firing. A method for manufacturing a low-temperature fired circuit board, characterized in that the pins are erected and then fired at a low temperature. However, when pins are erected on a ceramic multilayer substrate, the thermal expansion coefficient between the metal of the pin material and the ceramic differs, so that a gap is generated between the pins and the ceramic, and the bonding strength tends to decrease. I understand.

[発明が解決しようとする課題] 本発明は、グリーンシートに端子ピンを予め立設して
同時焼成することにより製造するセラミック多層基板を
改良し、ピン材の金属とセラミックとの間の熱膨脹係数
の相異によるピンとセラミックとの間の隙間の発生に起
因する接合強度の低下を回避し、接合強度を向上させ得
るセラミック多層基板およびその製造方法を提供するこ
とを目的とする。
[Problems to be Solved by the Invention] The present invention is to improve a ceramic multilayer substrate manufactured by erecting and simultaneously firing terminal pins on a green sheet, and to obtain a coefficient of thermal expansion between metal and ceramic of the pin material. It is an object of the present invention to provide a ceramic multilayer substrate capable of improving the bonding strength by avoiding a decrease in the bonding strength caused by the generation of a gap between the pin and the ceramic due to the difference between the two, and a method of manufacturing the same.

[課題を解決するための手段] 本発明によれば、ガラスセラミック材からなる低温焼
成用セラミックから構成したグリーンシートの所定位置
に棒状のAu−Pt−Ag合金およびNi−Cr−Al合金から選択
した材料からなるピンを立設し、その後低温で焼成を行
なうことからなり、一部に凸部を有するピンをプレスの
際に打ち込み、該ピンの下に金ビア導体を予め配置し、
700−1000℃で同時焼成することを特徴とするセラミッ
ク多層基板の製造方法が提供される。
[Means for Solving the Problems] According to the present invention, a rod-shaped Au-Pt-Ag alloy or a Ni-Cr-Al alloy is selected at a predetermined position of a green sheet made of a low-temperature firing ceramic made of a glass ceramic material. Erecting a pin made of the material, then firing at a low temperature, driving in a pin having a convex part at the time of pressing, placing a gold via conductor under the pin in advance,
A method for manufacturing a ceramic multilayer substrate characterized by co-firing at 700-1000 ° C. is provided.

金ビア導体は、金を含有するビア導体であり、次の条
件: 700〜1000℃にて大気中で変質もせず硬度も低下しな
い、 基板の導体である金属体と強固に接合する、 を充足するものを使用すれば好適である。
Gold via conductors are gold-containing via conductors and satisfy the following conditions: At 700 to 1000 ° C, they do not deteriorate in the air and do not decrease in hardness. They are firmly bonded to the metal body that is the conductor of the substrate. It is preferable to use one that does.

更に本発明によれば、前記した方法により製造された
セラミック多層基板が提供される。
Further, according to the present invention, there is provided a ceramic multilayer substrate manufactured by the above-described method.

本発明に使用し得るガラスセラミック材からなる低温
焼成用セラミックとして、例えば鉛ホウケイ酸ガラス−
アルミナ等を例示することができ、このようなセラミッ
クを用いて、好ましくは700〜1000℃の温度で焼成を行
う。
As a low-temperature firing ceramic comprising a glass ceramic material that can be used in the present invention, for example, lead borosilicate glass
Alumina and the like can be exemplified, and sintering is preferably performed at a temperature of 700 to 1000 ° C. using such a ceramic.

グリーンシートに立設するピンの材質は、通常使用さ
れるものでよく、例えばAu−Pt−Ag合金等を使用するこ
とができる。
The material of the pins erected on the green sheet may be a commonly used material, for example, an Au-Pt-Ag alloy or the like can be used.

ピンの凸部は、適切にはピンの径の200〜300%程度の
径を有するものとする。
The protrusion of the pin has a diameter of about 200 to 300% of the diameter of the pin.

このような凸部を有するピンの下にピンと接合性の強
い金ビア導体を形成するが、この金ビア導体の径は、好
ましくはピンの凸部の径と同程度とする。また、金ビア
導体の縦方向の厚さは、好ましくは0.2〜0.6mm程度とす
る。
A gold via conductor having a strong bonding property with the pin is formed below the pin having such a convex portion, and the diameter of the gold via conductor is preferably substantially equal to the diameter of the convex portion of the pin. The vertical thickness of the gold via conductor is preferably about 0.2 to 0.6 mm.

[作用] 前記したように、本出願人は、先にセラミック材料と
して、通常1000℃以下で低温焼成可能なガラスセラミッ
ク材を用い、焼成によるピンの変質がなく、グリーンシ
ートの段階で端子ピンを立設して焼成を行うことができ
る低温焼成回路基板の製造方法を提案した。しかしなが
ら、セラミック多層基板にピンを立設する場合、ピン材
の金属とセラミックとの間の熱膨脹係数が異なるため、
ピンとセラミックとの間の隙間が生じてしまい、接合強
度が低下する傾向があることが分った。
[Operation] As described above, the present applicant previously used a glass ceramic material that can be fired at a low temperature of usually 1000 ° C. or less as a ceramic material, and there was no deterioration of the pins due to firing, and the terminal pins were formed at the green sheet stage. A method for manufacturing a low-temperature fired circuit board capable of standing and firing is proposed. However, when pins are erected on the ceramic multilayer substrate, the thermal expansion coefficient between the metal of the pin material and the ceramic is different,
It has been found that a gap is formed between the pin and the ceramic, and the bonding strength tends to decrease.

本発明はこのような問題点の解決を図るものであり、
セラミック多層基板を製造するに際し、一部に凸部を有
するピンをプレスの際に打ち込み、ピンの下に金ビア導
体を予め配置し、同時焼成するものである。
The present invention is intended to solve such a problem,
In manufacturing a ceramic multilayer substrate, a pin having a projection is partially driven in at the time of pressing, a gold via conductor is previously arranged below the pin, and co-firing is performed.

すなわち本発明は、ピンと接合性の強い金ビア導体の
材料的性質を利用すると共に、ピン自体を所定の形状と
することにより、構造面からの接合強度の向上をも企図
するものである。
That is, the present invention intends to improve the bonding strength from the structural aspect by utilizing the material properties of the gold via conductor having a strong bonding property with the pin and by forming the pin itself into a predetermined shape.

[実施例] 以下に実施例により本発明を更に詳細に説明するが、
本発明は以下の実施例にのみ限定されるものではない。
EXAMPLES Hereinafter, the present invention will be described in more detail with reference to Examples.
The present invention is not limited only to the following examples.

第1図は、本発明のセラミック多層基板にピンを立設
する概略を示す図である。第1図に示すように、ガラス
セラミック材からなる低温焼成用セラミックから構成し
たグリーンシート10の所定位置に棒状のピン12を立設
し、このピンは一部に凸部14を有するものとした。この
ピンをプレスの際に打ち込むが、ピンの下には金ビア導
体16を予め配置した。これをプレス後に同時焼成するこ
とにより、セラミック多層基板を製造した。
FIG. 1 is a view schematically showing how a pin is erected on a ceramic multilayer substrate according to the present invention. As shown in FIG. 1, a bar-shaped pin 12 is erected at a predetermined position on a green sheet 10 made of a ceramic for low-temperature firing made of a glass ceramic material, and this pin has a projection 14 in a part. . This pin was driven in at the time of pressing, and a gold via conductor 16 was previously arranged under the pin. This was simultaneously fired after pressing to produce a ceramic multilayer substrate.

ガラスセラミック材として鉛ホウケイ酸ガラス−アル
ミナを使用し、ピンの材質はAu−Pt−Ag合金またはNi−
Cr−Al合金とし、焼成は900℃で常法により行った。
Lead borosilicate glass-alumina is used as the glass ceramic material, and the pin material is Au-Pt-Ag alloy or Ni-
A Cr-Al alloy was used, and firing was performed at 900 ° C by a conventional method.

ピンは直径0.4mm、長さ3.0mmのものを使用した。ピン
の凸部の大きさは直径0.8mm、長さ0.2mmとした。金ビア
導体部分の大きさは、直径0.8mm、長さ0.2mmとした。
The pin used had a diameter of 0.4 mm and a length of 3.0 mm. The size of the protrusion of the pin was 0.8 mm in diameter and 0.2 mm in length. The size of the gold via conductor was 0.8 mm in diameter and 0.2 mm in length.

得られたセラミック多層基板は、ピンとセラミックと
の間の隙間の発生に起因する接合強度の低下が回避さ
れ、接合強度が向上したものであった。
In the obtained ceramic multilayer substrate, a decrease in bonding strength due to the generation of a gap between the pin and the ceramic was avoided, and the bonding strength was improved.

[発明の効果] 以上説明したように本発明によれば、グリーンシート
に端子ピンを予め立設して同時焼成することにより製造
するセラミック多層基板を改良し、ピン材の金属とセラ
ミックとの間の熱膨脹係数の相異によるピンとセラミッ
クとの間の隙間の発生に起因する接合強度の低下を回避
し、接合強度を向上させ得るセラミック多層基板および
その製造方法が提供される。
[Effects of the Invention] As described above, according to the present invention, a ceramic multilayer substrate manufactured by previously erecting terminal pins on a green sheet and firing them simultaneously is improved, so that the pin material and the ceramic can be interposed. The present invention provides a ceramic multilayer substrate capable of avoiding a decrease in bonding strength due to the generation of a gap between a pin and a ceramic due to a difference in thermal expansion coefficient between the pins and improving the bonding strength, and a method for manufacturing the same.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明のセラミック多層基板にピンを立設する
概略を示す図、第2図は従来の方法による端子ピンの立
設を示す図である。 10……グリーンシート、12……端子ピン 14……凸部、16……金ビア導体 30……アルミナ基板、32……導体パターン 34……Niメッキ、36……ろう付け剤 38……端子ピン
FIG. 1 is a view schematically showing how pins are erected on a ceramic multilayer substrate of the present invention, and FIG. 2 is a view showing how terminal pins are erected by a conventional method. 10 ... Green sheet, 12 ... Terminal pins 14 ... Protrusion, 16 ... Gold via conductor 30 ... Alumina substrate, 32 ... Conductor pattern 34 ... Ni plating, 36 ... Brazing agent 38 ... Terminal pin

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】ガラスセラミック材からなる低温焼成用セ
ラミックから構成したグリーンシートの所定位置に棒状
のAu−Pt−Ag合金およびNi−Cr−Al合金から選択した材
料からなるピンを立設し、その後低温で焼成を行なうこ
とからなり、一部に凸部を有するピンをプレスの際に打
ち込み、該ピンの下に金ビア導体を予め配置し、700−1
000℃で同時焼成することを特徴とするセラミック多層
基板の製造方法。
1. A pin made of a material selected from a rod-shaped Au-Pt-Ag alloy and a Ni-Cr-Al alloy is erected at a predetermined position on a green sheet made of a low-temperature firing ceramic made of a glass ceramic material. After that, firing is performed at a low temperature, a pin having a convex portion is driven in at the time of pressing, and a gold via conductor is previously arranged under the pin, and 700-1
A method for producing a ceramic multilayer substrate, comprising co-firing at 000 ° C.
【請求項2】上記金ビア導体として、次の条件: 1.700〜1000℃にて大気中で変質もせず硬度も低下しな
い、 2.基板の導体である金属体と強固に接合する、 を充足するものを使用する請求項1記載の方法。
2. The gold via conductor satisfies the following conditions: 1. 700 to 1000 ° C., does not deteriorate in the air and does not decrease in hardness, 2. satisfactorily bonds to a metal body which is a conductor of a substrate. A method according to claim 1, wherein said method is used.
【請求項3】請求項1または2記載の方法により製造さ
れたセラミック多層基板。
3. A ceramic multilayer substrate manufactured by the method according to claim 1.
JP24625890A 1990-09-18 1990-09-18 Ceramic multilayer substrate and method of manufacturing the same Expired - Fee Related JP3184207B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24625890A JP3184207B2 (en) 1990-09-18 1990-09-18 Ceramic multilayer substrate and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24625890A JP3184207B2 (en) 1990-09-18 1990-09-18 Ceramic multilayer substrate and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH04125994A JPH04125994A (en) 1992-04-27
JP3184207B2 true JP3184207B2 (en) 2001-07-09

Family

ID=17145848

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24625890A Expired - Fee Related JP3184207B2 (en) 1990-09-18 1990-09-18 Ceramic multilayer substrate and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP3184207B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220042712A (en) * 2020-09-28 2022-04-05 주식회사 디아이티 Multilayer ceramic substrate having connecting means with frame and method of manufacturing the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10284836A (en) * 1997-04-08 1998-10-23 Hitachi Ltd Collectively laminated ceramic wiring board and its manufacture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220042712A (en) * 2020-09-28 2022-04-05 주식회사 디아이티 Multilayer ceramic substrate having connecting means with frame and method of manufacturing the same
KR102466911B1 (en) 2020-09-28 2022-11-14 주식회사 디아이티 Multilayer ceramic substrate having connecting means with frame and method of manufacturing the same

Also Published As

Publication number Publication date
JPH04125994A (en) 1992-04-27

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