JP3179040B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous semiconductor memory, and more particularly to a synchronous dynamic random access memory (hereinafter referred to as DRAM) having a characteristic in output control.

[0002]

2. Description of the Related Art A conventional synchronous semiconductor memory is disclosed in
No. 1-39295 and JP-A-62-275384. The synchronous semiconductor memory has a memory cell array. A decoder is connected to the input of this memory cell. A latch circuit and an output buffer are connected to the output of the memory cell array.

When data is read from a memory cell array, an externally input address is decoded by a decoder,
Select a memory cell in the memory cell array. The data stored in the selected memory cell is temporarily latched by the latch circuit. Thereafter, the data latched in synchronization with the synchronization clock is read out from the output buffer to the outside. In the above-mentioned synchronous static random access memory (hereinafter referred to as SRAM), only one pulse of a synchronous clock is input to the output buffer during one memory access period, so that read data is accurately output from the output buffer in synchronization with this pulse. can do.

On the other hand, in a DRAM, a plurality of consecutive pulses of a synchronous clock are input to an output buffer during one memory access period. When a conventional synchronization method is applied to a DRAM, it is necessary to determine in advance which pulse of the synchronization clock should output read data from the output buffer to the outside.

[0005]

However, in a DRAM, since an address is input and data is read or written during one memory access period, a delay may occur in the timing of inputting read data to a latch circuit. There is. Therefore, the operation timing of the output buffer cannot be accurately controlled in the DRAM to which the conventional synchronization method is applied. An object of the present invention is to provide a synchronous DRAM that selects an optimum pulse from a plurality of pulses of a synchronous clock input to an output buffer during one memory access period and determines the operation timing of the output buffer. It is in.

[0006]

As means for solving the above-mentioned problems, means taken in a semiconductor memory according to the present invention includes a memory cell array composed of a plurality of memory cells and a memory cell array which responds to an address control signal. A circuit for selecting a desired memory cell among a plurality of memory cells constituting a memory cell array based on input address information;
A transfer circuit for transferring data stored in the selected memory cell, and data transferred from the transfer circuit,
A data output circuit that outputs data in response to a control signal, and a clock signal and selection information are input thereto, based on transitions of potential levels at different timings in the clock signal according to the address control signal,
Generate a plurality of timing signals that change the potential level,
And a control signal output circuit for selectively outputting any one of the plurality of timing signals as a control signal based on the selection information.

[0007]

The control signal generation circuit outputs one of a plurality of control signals having different timings to the data output circuit depending on the state of the input signal, so that the control signal having the optimum timing can be selected.

[0008]

FIG. 1 shows a synchronous DR according to an embodiment of the present invention.
It is a schematic block diagram of AM. This synchronous DRA
M includes an address input circuit 101 that receives addresses A0 to An input from outside and outputs an X address and a Y address. Address input circuit 101
Is a latch circuit 103 for inputting addresses A0 to An in synchronization with a synchronous clock CLK;
And an address buffer 105 for generating an X address and a Y address based on the output of the address 03. An X address decoder 107 and a Y address decoder 109 are connected to the output of the address buffer 105. The outputs of the X address decoder 107 and the Y address decoder 109 are
Memory cells (not shown) to which the plurality of word lines 111 and bit lines 113 are connected are connected to a memory cell array 115 in which a matrix is arranged. A memory cell is connected to each intersection of the word line 111 and the bit line 113. X address decoder 107
Selects one word line among the plurality of word lines 111. The Y address decoder 109 has a plurality of bit lines 113
One of the bit lines is selected.

The bit line 111 is connected to a data bus 119 via an input / output circuit 117 for reading / writing. The data bus 119 is connected to the data latch circuit 601. Data latch circuit 601 latches read data read onto data bus 119. Thereafter, the data latch circuit 601 outputs the latched read data S1.
To the output circuit 123. Output circuit 123 is activated by output control signal φa synchronized with clock signal CLK, and outputs read data S1 to the outside in the form of read data D0. In this embodiment, the output circuit 123 is constituted by an output buffer. The DRAM of this embodiment
Is provided with a memory control signal generation circuit 125 and an output clock delay control circuit 607. The memory control signal generation circuit 125 includes a clock signal CL input from the outside.
K, a row address strobe signal / RAS, and a column address strobe signal / CAS are input, and various memory control signals S3 and drive signals S4 for controlling the memory internal circuit are output. Memory control signal generation circuit 1
Reference numeral 25 denotes a latch circuit 131 for latching a row address strobe signal / RAS and a column address strobe signal / CAS in response to a clock signal CLK, and receives an output of the latch circuit 131 to generate a memory control signal S3 and a drive signal S4. And a signal generation circuit 133 that generates the signal. Drive signal S4 is sent to output clock delay control circuit 607.

The output clock delay control circuit 607 has external input terminals 603 and 605. External input terminal 6
03 and 605 are terminals for inputting external input signals SEL0 and SEL1 for specifying a delayed clock, respectively.
The output clock delay control circuit 607 outputs the clock signal CL
K, the row address strobe signal / RAS, the drive signal S4 from the memory control signal generation circuit 125 and the external input signals SEL0 and SEL1.
3 to generate an output control signal φa.

FIG. 2 is a circuit diagram showing a configuration example of the output clock delay control circuit 607 shown in FIG. The output clock delay control circuit 607 includes a shift register unit 609 and a logic circuit unit 611. The shift register unit 609 includes an inverter 613 for inverting the drive signal S4 falling in synchronization with the falling of the row address strobe signal / RAS, and a row address strobe signal / RA
A reset pulse generation circuit 615 that outputs a reset signal S8 having a one-shot pulse in synchronization with the falling and rising edges of S, and five flip-flops (hereinafter referred to as FFs) that shift the output of the inverter 613 in synchronization with the clock signal CLK. ) 617, 619, 621, 623
And 625. The output of the inverter 613 is connected to the input of the first FF 617 and the first FF 61
7 is connected to the input of the second FF 619 and the second FF 61
9 is input to the input of the third FF 621,
1 is input to the input of the fourth FF 623 and the fourth FF 62
The output of the third FF 625 is connected to the input of the fifth FF 625.
The output of the reset pulse generation circuit 615 is the first through fifth outputs.
Are connected to the reset inputs of the FFs 617 to 625. Further, the clock signal CLK is supplied to the first to fifth FFs.
617 to 625 are input to the timing input. Third, fourth and fifth FFs 62 of the shift register unit 609
The outputs of 1, 623 and 625 are supplied to the logic circuit unit 611.

The logic circuit section 611 includes a shift register section 6
This is a circuit for selecting the fall timing of the output control signal φa based on a combination of the output signal 09 and the external input signals SEL0 and SEL1. The logic circuit portion 611 receives the external input signal S
First and second input terminals 603 and 605 for receiving EL0 and SEL1, respectively, and inverters 627 and 62
9, first, second, and third NAND gates 631, 633, 635 for signal selection, and these NAND gates 6
And a fourth NAND gate 637 for generating an output control signal φa from the outputs of 31, 633 and 635. The first external terminal 603 is connected to first inputs of the first and second NAND gates 631 and 633 and is also connected to a first input of the third NAND gate 635 via the inverter 629. The second external terminal 605 is connected to the first N
The second input of the AND gate 631 is connected to the second input of the second and third NAND gates 633 and 635 via the inverter 627. Third FF6
21 is connected to the third input of the third NAND gate 635, and the output of the fourth FF 623 is connected to the second input of the second NAND gate 6.
33, the output of the fifth FF 625 is the first N
Each is connected to a third input of an AND gate 631.
First, second and third NAND gates 631, 633,
The output of 635 is connected to the first, second and third inputs of a fourth NAND gate 637.

FIG. 3 is an operation timing chart of the synchronous DRAM of FIG. 1. The operation of the synchronous DRAM of FIG. 1 will be described with reference to FIG. Near time t22,
Address input circuit 101 receives X address 801 in addresses A0 to An, and receives Y address 803 near time t23. Then, the clock signal C
Independently of LK, the address buffer 10
5 are transferred to the X address decoder 107 and the Y decoder 109, respectively. The output of the X address decoder 107 and the Y address decoder 109 causes the memory cell array 1
15 of the memory cells are selected. The storage data 805 of the selected memory cell is transferred to the data latch circuit 601 via the data bus 119 at time t25. On the other hand, the row address strobe signal / input to the shift register unit 609 of the output clock control circuit 607 is
RAS falls at time t21, and in response to this fall, reset pulse generating circuit 615 outputs reset signal S8 having a one-shot pulse. The reset signal S8 resets the first to fifth FFs 617 to 625 slightly later than the time t21 (FIG. 3 shows a case where the outputs of all the FFs are at the "L" level. Not shown above). Thereafter, drive signal S4 falls, and in response to this fall, output signal S4A of inverter 613 rises to "H" level. At time t22 when output signal S4A goes to "H" level and first clock signal CLK rises, output signal A of first FF 617 goes from "L" level to "H" level in response to this rising. Thereafter, at times t23, t24, t26 and t27, the output signals B to E of the second to fifth FFs 619 to 625 are output.
Respectively, from "L" level to "H" level. Thereafter, row address strobe signal / RAS is applied at time t28.
, And in response, the reset pulse generating circuit 615 generates a reset signal S having a one-shot pulse.
8 and the drive signal S4 also rises. Therefore, the output signal A of the inverter 613 changes from “H” level to “L” level. First to fifth FFs 617 to 625
Output signals A to E change from "H" level to "L" level in response to the pulse of the reset signal S8.

Next, the operation of the logic circuit section 611 of the output clock delay control circuit 607 will be described. In this operation, the external input signal SEL0 is at “H” level,
1 is at the “L” level (see FIG. 3A), when both the external input signals SEL0 and SEL1 are at the “L” level (see FIG. 3B), and when the external input signals SEL0 and SEL1 are
The description will be divided into three cases, each of which is at the “H” level (see FIG. 3C).

In the case of FIG. 3A, when the external input signal SEL0 is at "H" level and SEL1 is at "L" level, the outputs of the first NAND gate 631 and the third NAND gate 635 are output to the shift register section. It is at “L” level regardless of the output of 609. on the other hand,
The output of the second NAND gate 633 is the fourth FF 62
3 is output as it is. Therefore, the fourth N
Output control signal φa which is an output signal of AND gate 637
Becomes the output signal D of the fourth FF 623, and the time t26
And falls at time t28. This is described in Table 1 below, which shows the input and output signal levels of the first to fourth NAND gates 631 to 637.

【table 1】

Output circuit 123 outputs read data D0 (805) in response to output control signal φa with a delay of a predetermined delay time Ta from time t26.

In the case of FIG. 3B, when the external input signal SEL0 is at the "L" level and SEL1 is also at the "L" level, the outputs of the first NAND gate 631 and the second NAND gate 633 are output to the shift register unit. It is at “L” level regardless of the output of 609. on the other hand,
The output of the third NAND gate 635 is the third FF 62
1 is output as it is. Therefore, the fourth N
Output control signal φa which is an output signal of AND gate 637
Becomes the output signal C of the third FF 621, and the output control signal φa rises at time t24 and falls at time t28. This is illustrated by Table 2 below.

[Table 2]

Output circuit 123 attempts to output read data D0 (805) in response to output control signal φa, but at time t24, output circuit 123 outputs read data D0.
(805) has not been latched yet. Therefore, the read data D is delayed by a time Tb longer than the predetermined delay time Ta.
Outputs 0.

In the case of FIG. 3C, when the external input signal SEL0 is at the “H” level and SEL1 is also at the “H” level, the outputs of the second NAND gate 633 and the third NAND gate 635 are output to the shift register unit. It is at “L” level regardless of the output of 609. on the other hand,
The output of the first NAND gate 631 is connected to the fifth FF 62
5 is output as it is. Therefore, the fourth N
Output control signal φa which is an output signal of AND gate 637
Becomes the output signal E of the fifth FF 625, and the output control signal φa rises at time t27 and falls at time t28. This is illustrated by Table 3 below.

[Table 3]

Output circuit 123 responds to output control signal φa and delays read data D0 by a predetermined delay time Ta.
(805) is output.

In the case of FIG. 3B, when the output control signal φa rises, the read data D0 has not yet been sent to the data latch circuit 601. Therefore, the data output of the output circuit 123 starts at the rising time t24 of the clock signal CLK. Until the time Tb is required. On the other hand, in the case of FIGS. 3A and 3C, the read data D0 is already latched in the data latch circuit 601 when the output control signal φa rises, so that the rising time t26 of the clock signal CLK rises.
Alternatively, the output circuit 123 can output the read data D0 with a delay of a predetermined delay time Ta from t27.

Comparing the above three cases, in the case of FIG. 3B, the row address strobe signal / RAS
Although the time from the fall time t21 to the start of access is fast, the start of access from the rise of the clock signal CLK is slow. In the case of FIG. 3C, the time from the rise time t21 of the row address strobe signal / RAS to the start of access is delayed. Therefore, the case of FIG. 3A can be said to be the case where the optimum output control signal φa is generated. Therefore, if the external input signal SEL0 is set to “H” level and SEL1 is set to “L” level, the read data D0 is output from the output circuit 123 by the output control signal φa output from the output clock delay control circuit 607, and A synchronous operation is obtained. It should be noted that the DRA having the same configuration as this embodiment is used.
If the transfer speed of the read data from the memory cell array 115 to the data latch circuit 601 is high due to manufacturing variation even in M, the case of FIG. 3B may be the optimum synchronous operation.

[0023]

As described above in detail, in the DRAM of the present invention, the output control signal can be arbitrarily set by a predetermined input signal or the like. Also, it is possible to output read data from the memory in synchronization with the optimum clock pulse.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a synchronous DRAM showing an embodiment of the present invention;

FIG. 2 is a circuit diagram showing a configuration example of an output clock delay control circuit shown in FIG. 1;

FIG. 3 is an operation timing chart of the synchronous DRAM of FIG. 1;

[Explanation of symbols]

 101: Address input circuit 107: X address decoder 109: Y address decoder 111: Word line 113: Bit line 115: Memory cell array 117: Input / output circuit 123: Output circuit 125: Memory control signal generation circuit 601: Data latch circuit 603, 605: External input terminal

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/4063

Claims (8)

(57) [Claims] 1. A memory cell array comprising a plurality of memory cells, and a desired memory cell among a plurality of memory cells constituting the memory cell array, based on input address information in response to an address control signal. A circuit for selecting, a transfer circuit for transferring data stored in the selected memory cell, a data output circuit for receiving the data transferred from the transfer circuit and outputting the data in response to a control signal; A clock signal and selection information are input,
According to the address control signal, a plurality of timing signals whose potential levels transition are generated based on potential level transitions at different timings in the clock signal, and any one of the plurality of timing signals is generated based on the selection information. And a control signal output circuit for selectively outputting one of the control signals as the control signal. 2. The semiconductor memory includes an internal control signal generation circuit that receives at least the clock signal and the address control signal and generates a plurality of internal control signals. 2. The plurality of timing signals are generated based on a signal corresponding to the address control signal among the internal control signals generated and input by a control signal generation circuit.
The semiconductor memory according to any one of the preceding claims. 3. The control signal output circuit sequentially shifts one of the internal control signals input from the internal control signal generation circuit to the control signal output circuit at each transition of the potential level of the clock signal. A shift register that outputs a plurality of timing signals, and based on the selection information,
3. The semiconductor memory according to claim 2, further comprising: a selection circuit that selectively outputs any one of the plurality of timing signals as the control signal. 4. The shift register according to claim 3, wherein a potential level of each of the plurality of timing signals can be reset to a predetermined potential level in accordance with a transition of a potential level of the address control signal. The semiconductor memory according to any one of the preceding claims. 5. The address control signal according to claim 1, wherein the address control signal corresponds to a row address strobe signal.
5. The semiconductor memory according to any one of items 1 to 4, 6. The semiconductor memory according to claim 5, wherein the circuit for selecting the specific memory cell also responds to a column address strobe signal. 7. The semiconductor memory according to claim 1, wherein the selection information is a plurality of bits of data composed of a plurality of signals. 8. The semiconductor device according to claim 1, wherein the selection information is inputted from outside the semiconductor memory.
8. The semiconductor memory according to any one of items 1 to 7,