JP2732710B2 - Synchronous semiconductor memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a synchronous semiconductor memory, and more particularly to a synchronous dynamic random access memory (hereinafter referred to as DRAM).
) Output control method.

(Background Art) Conventional synchronous semiconductor memories are disclosed in JP-A-61-39295 and JP-A-62-275384.

The synchronous semiconductor memory has a memory cell array. A decoder is connected to the input of this memory cell. A latch circuit and an output buffer are connected to the output of the memory cell array.

When reading data from a memory cell array, an externally input address is decoded by a decoder, and a memory cell in the memory cell array is selected. The data stored in the selected memory cell is temporarily latched by the latch circuit. Thereafter, the data latched in synchronization with the synchronization clock is read out from the output buffer to the outside. In the above-described synchronous static random access memory (hereinafter referred to as SRAM), one synchronous clock is used during one memory access period.
Since only the pulse is input to the output buffer, the read data can be accurately output from the output buffer in synchronization with the pulse.

On the other hand, in the DRAM, a plurality of consecutive pulses of the synchronous clock are input to the output buffer during one memory access period. When a conventional synchronization method is applied to a DRAM, it is necessary to determine in advance which pulse of a synchronization clock should output read data from an output buffer to the outside.

However, in the DRAM, an address is input and data is read or written during one memory access period, so that there is a possibility that the timing of inputting read data to the latch circuit may be delayed. Therefore, the operation timing of the output buffer cannot be accurately controlled in the DRAM to which the conventional synchronization method is applied.

An object of the present invention is to provide a synchronous DRAM that performs appropriate synchronous control.

(Disclosure of the Invention) In a synchronous semiconductor memory according to the present invention, a memory cell array in which a plurality of memory cells are arranged in a matrix is connected to the memory cell array, and a specific memory cell is selected from the plurality of memory cells. A circuit connected to the circuit and the memory cell array, for transferring data stored in the memory cell; and a data connected to the transfer means for receiving data from the transfer means, latching the data, and outputting a data transfer completion signal. A latch circuit, an output circuit connected to the data latch circuit for receiving data latched from the data latch circuit, and outputting the received data according to a control signal; a clock signal and a data transfer completion signal connected to the data latch circuit And the clock pulse of the clock signal after receiving the data transfer completion signal A clock counting circuit for counting the number and a clock number output circuit connected to the clock counting circuit and outputting the number of pulses calculated by the clock counting circuit are provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a synchronous DRAM according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of a clock counting circuit and a delay clock number output circuit of FIG. FIG. 3 is a timing chart of FIG. 1, FIG. 4 is a block diagram of a synchronous DRAM showing a second embodiment of the present invention, and FIG. 5 is a timing chart of FIG.

BEST MODE FOR CARRYING OUT THE INVENTION FIG. 1 is a schematic block diagram of a synchronous DRAM according to a first embodiment of the present invention.

This synchronous DRAM has addresses A0 to
An address input circuit 101 that receives An and outputs an X address and a Y address is provided. Address input circuit 101
A latch circuit 103 for inputting addresses A0 to An in synchronization with a synchronous clock CLK, and an address buffer for generating an X address and a Y address based on the output of the latch circuit 103.
It consists of 105. An X address decoder 107 and a Y address decoder 109 are connected to the output of the address buffer 105.

The outputs of the X address decoder 107 and the Y address decoder 109 are connected to a memory cell array 115 in which memory cells (not shown) to which a plurality of word lines 111 and bit lines 113 are respectively connected are arranged in a matrix. A memory cell is connected to each intersection of the word line 111 and the bit line 113. The X address decoder 107 selects one word line among the plurality of word lines 111. Y address decoder 109 selects one bit line among a plurality of bit lines 113.

Bit line 111 is an input / output circuit 1 for reading / writing.
It is connected to the data bus 119 via 17. Data bus 119
Are connected to the data latch circuit 121. Data latch circuit 121 latches the read data read onto data bus 119. Thereafter, the data latch circuit 121 supplies the latched read data S1 to the output circuit 123 and outputs a latch completion signal S2. The output circuit 123 outputs the clock signal C
It is activated by an output control signal φ synchronized with LK, and outputs read data S1 to the outside in the form of read data D0. In this embodiment, the output circuit 123 is constituted by an output buffer.

Further, the DRAM of this embodiment has a memory control signal generation circuit.
125, a clock counting circuit 127, and a delayed clock number output circuit 129 are provided. Memory control signal generation circuit 125
Receives a clock signal CLK, a row address strobe signal ▲ ▼, and a column address strobe signal ▲ ▼ inputted from outside, and various memory control signals S3 and a drive signal S4 for controlling a memory internal circuit.
Is output. The memory control signal generation circuit 125 responds to the clock signal CLK to respond to the row address strobe signal ▲.
The latch circuit 131 latches the ▼ and column address strobe signals ▲ ▼, and the signal generation circuit 133 which receives the output of the latch circuit 131 and generates the memory control signal S3 and the drive signal S4. The drive signal S4 is sent to the delay clock number output circuit 129.

The clock counting circuit 127 responds to the fall of the row address strobe signal ▲ ▼ in response to the clock signal CLK.
Is counted. Then, the data latch circuit 12
When receiving the latch completion signal S2 from 1, the clock counting circuit 127 stops the counting operation. The output of the clock counting circuit 127 is connected to the delay clock number output circuit 129. The delay clock number output circuit 129 is a memory control signal generation circuit 1
Clock counting circuit in response to drive signal S4 from 25
This circuit outputs the output of 127 to the number-of-delayed-clock output terminals 135, 137, 139. Here, the output terminal 135 outputs the first digit of the counted clock number (binary number), the output terminal 137 outputs the second digit, and the output terminal 139 outputs the third digit.

FIG. 2 is a circuit diagram showing a configuration of the clock counting circuit 127 and the delayed clock number output circuit 129 shown in FIG.

The clock counting circuit 127 controls the input of the clock signal CLK by the latch completion signal S2 to output the driving clock signal S5, and the reset pulse which outputs the reset signal S6 in response to the row address strobe signal ▲ ▼. And a generation circuit 203. The output of the reset pulse generating circuit 203 is connected to an address counter 205. The address counter 205 is reset by the reset signal S6 and counts up by the driving clock signal S5. Address counter output P0, P of address counter 205
1, P2 are connected to the inputs of the delay clock number output circuit 129. Here, the address counter output P0 outputs the first digit of the address count number (binary number), the output P1 outputs the second digit,
P2 represents the third digit.

The delay clock number output circuit 129 includes three-state inverters 207, 209, and 21 that are opened and closed by the drive signal S4.
These tri-state inverters 207 and 20
Delay clock number output terminals 135, 137, and 139 are connected to outputs of 9, 211, respectively.

FIG. 3 is a timing chart of FIG. 1, and the operation of FIGS. 1 and 2 will be described with reference to FIG.

When the row address strobe signal ▲ ▼ falls and access (data reading) starts at time t1, a one-shot pulse of the reset signal S6 is generated from the reset pulse generation circuit 203 in the clock counting circuit 127. The address counter 205 is reset by the reset signal S6, and the outputs P0, P1, and P2 become "L" level. Since the read data is not transferred from the data bus 119 to the data latch circuit 121 until time t7, the latch completion signal S2 output from the data latch circuit 121 remains at "L" level until time t7. Therefore, the NOR gate 20 in the clock counting circuit 127
1 inputs the clock signal CLK until time t7 and supplies the drive clock signal S5 to the address counter 205. Thus, at time t2, t3, t4, and t5, the address counter 205 counts up in synchronization with the rise of the drive clock signal S5 (see outputs P0, P1, and P2).

During this time, the externally supplied addresses A0 to An are taken into the address input circuit 101. An X address and a Y address are output from the address input circuit 101 and supplied to the X address decoder 107 and the Y address decoder 109, respectively. X address decoder 107 and Y address decoder 1
In step 09, the X address and the Y address are each decoded to select a memory cell in the memory cell array 115. The storage data of the selected memory cell is transferred to the data bus at time t6.
The data is transferred to the data latch circuit 121 via 119.

At time t7, which is a certain time after time t6, the data latch circuit
The latch completion signal S2 output from 121 becomes “H” level, and the output of the clock signal CLK from the NOR gate 201 in the clock counting circuit 127 is stopped. Therefore, outputs P0, P1, P
The level of signal 2 is fixed. Then, at time t8, the drive signal S4 output from the memory control signal generation circuit 125 becomes “H” level, and the delay clock number output circuit
The tri-state inverters 207, 209 and 211 in the 129 are turned on, and the signal levels of the fixed address counter outputs P0, P1 and P2 change to the tri-state inverters 207, 209 and 21.
It appears at the delayed clock number output terminals 135, 137, 139 via 1.

In the first embodiment, when the output circuit 123 is activated with one of a plurality of continuous pulses of the clock signal CLK input during one memory access, an output can be obtained by an optimal clock synchronization operation. Can be easily determined by measuring the delay clock number output terminals 135, 137, 139 and the like with a tester or the like.

Generally, in a DRAM, the data transfer time from the start of access to the data latch circuit 121 varies due to manufacturing variations. This data transfer time can be determined from the number of delayed clocks output from the number-of-delayed-clock output terminals 135, 137, 139. Then, an output control signal φ synchronized with the clock signal CLK is generated based on the determination result. If the providing circuit 123 is activated by the output control signal φ to output the read data D0, the read data D0 can be accurately output in synchronization with the clock signal CLK.

FIG. 4 is a schematic block diagram showing the configuration of a synchronous DRAM according to a second embodiment of the present invention. Elements common to those in FIG. 1 are denoted by the same reference numerals.

The DRAM of the second embodiment is the same as the DRAM of the first embodiment except that a delay circuit 401 is connected between the output of the data latch circuit 121 and the input of the clock counting circuit 127. . The delay circuit 401 receives the latch completion signal S2 output from the data latch circuit 121, and receives a predetermined delay time
A latch completion delay signal S7 delayed by Td is generated. Delay circuit 401 provides latch completion delay signal S7 to clock counting circuit 127.

The delay circuit 401 according to the second embodiment includes a plurality of inverters.

FIG. 5 is a timing chart of FIG. 4, and the operation of the DRAM of the second embodiment will be described with reference to FIG.

Time t11 at which access starts when ▲ ▼ falls
Since the read data is not transferred to the data latch circuit 121 from to the time t15, the latch completion signal S2 output from the data latch circuit 121 is at the “L” level. for that reason,
The clock counting circuit 127 performs a count operation at times t12, t13, t14, and t16 in synchronization with the rise of the drive clock signal S5. During this time, the memory cell is selected, and the data stored in the selected memory cell is transferred to the data latch circuit 121 via the data path 119 at time t15.

When the read data is transferred to the data latch circuit 121, the latch completion signal S2 output from the data latch circuit 121 goes to “H” level. The latch completion signal S2 is delayed by the delay circuit 401 by a fixed delay time Td, and is output from the delay circuit 401 as a latch completion delay signal S7 which goes to the “H” level at time t17. The clock counting circuit 127 stops the circuit counting operation in response to the latch completion delay signal S7. Thereafter, at time t18, drive signal S4 output from memory control signal generation circuit 125 attains an "H" level. The signal levels of the address counter outputs P0, P1 and P2 of the stopped clock counting circuit 127 appear on the delayed clock number output terminals 135, 137 and 139 in response to the drive signal S4.

In the second embodiment, since the delay circuit 401 is provided at the output of the data latch circuit 129, a margin can be obtained in consideration of manufacturing variations, worst-case conditions during use operation, and the like. Therefore, the optimum number of delay clocks can be selected in consideration of the margin compared with the first embodiment, so that more accurate read data can be output in synchronization with the clock signal CLK.

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications.

As shown in FIG. 3, the clock signal CL at time t8 immediately after the read data is transferred to the data latch circuit 121.
At the rise of K, the clock counting circuit 127 outputs its output to the outside. However, it is also possible that the clock counting circuit 127 outputs an output to the outside at the falling of the clock signal CLK at the time t8. Further, as shown in FIG. 5, the clock counting circuit 127 outputs its output to the outside at the rising edge of the clock signal CLK at time t18 immediately after the generation of the latch completion delay signal S7. However, it is also possible that the clock counting circuit 127 outputs an output to the outside at the falling of the clock signal CLK at the time t8.

(Industrial Applicability) As described above, the DRAM of the present invention can be applied to a synchronous DRAM capable of outputting read data from a memory in synchronization with an optimum clock pulse.

Claims (7)

(57) [Claims] A memory cell array in which a plurality of memory cells are arranged in a matrix; a memory cell array connected to the memory cell array;
A circuit for selecting a specific memory cell from the plurality of memory cells; a unit connected to the memory cell array, for transferring data stored in the memory cell; a unit connected to the transfer unit; And a data latch circuit for latching data and outputting a data transfer completion signal; and an output connected to the data latch circuit for receiving data latched from the data latch circuit and outputting the received data according to a control signal. A clock counting circuit that is connected to the data latch circuit, receives a clock signal and a data transfer completion signal, and counts the number of clock pulses of the clock signal until the data transfer completion signal is received; And outputs the number of pulses calculated by the clock counting circuit. Synchronous semiconductor memory having a click number of output circuits. 2. A delay circuit connected between the data latch circuit and a clock counting circuit, the delay circuit delaying a data transfer completion signal received from the data latch circuit and applying the delayed signal to the clock counting circuit. 2. The synchronous semiconductor memory according to claim 1. 3. The memory cell selecting means receives an address signal, and receives an X signal based on the address signal.
An address input circuit for outputting an address signal and a Y address signal, an X address decoder connected to the address input circuit, receiving the X address signal, and selecting a row of the memory cell array based on the X address signal; 2. The synchronous semiconductor memory according to claim 1, further comprising: a Y address decoder connected to an address input circuit, receiving the Y address signal, and selecting a column of the memory cell array based on the Y address signal. 4. An address input circuit comprising: a latch circuit for receiving the address signal in response to a clock signal; a latch circuit connected to the latch circuit; and an X address signal and a Y address based on the address signal output from the latch circuit. 4. The synchronous semiconductor memory according to claim 3, further comprising an address buffer for outputting a signal. 5. The synchronous semiconductor memory according to claim 1, further comprising a control signal generating circuit connected to said clock number output circuit and generating a drive signal for driving said clock number output circuit. 6. A gate circuit that receives the clock signal and the data transfer completion signal and controls the output of a clock signal based on the data transfer completion signal, a clock signal generation circuit, and a reset signal generation circuit that generates a reset signal. Connected to the reset signal generation circuit and the gate circuit,
2. The synchronous semiconductor memory according to claim 1, further comprising: an address counter reset by the reset signal and counting the number of pulses of a clock signal output from the gate circuit. 7. The synchronous semiconductor memory according to claim 1, wherein said clock number output circuit has a tri-state inverter to which an output of said clock counting circuit is input and which is opened and closed by said drive signal.