JP3145969B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a memory cell region in which a plurality of semiconductor memory elements (hereinafter referred to as "memory cells") are regularly arranged, and more particularly to a memory which is arbitrarily addressed in the memory cell region. The present invention relates to a semiconductor device provided with a mark pattern serving as a mark for easily detecting a cell on a chip.

[0002]

2. Description of the Related Art When a defect occurs in a memory cell region of a semiconductor device, an analysis is performed by first identifying a defective address by an electrical characteristic test and then observing the memory cell of the defective address with a metallographic microscope or an electron microscope. Conventionally, a method of performing a failure analysis has been widely and generally performed. However, the number of memory cells mounted in the memory cell area has increased dramatically with the increase in the degree of integration and capacity of the semiconductor device, and the wiring structure on the memory cell area has changed arbitrarily. It is becoming very difficult to find a memory cell at an address with a metallographic microscope or an electron microscope.

[0003] Specifically, it is as follows. Conventionally, in a semiconductor device having a large-scale memory cell region, it has been general that at least two metal wires exist in the memory cell region and above the memory cell. The lower metal wiring of the two layers is provided for the purpose of lowering the resistance of the word line of the memory cell formed of polysilicon or polysilicon and tungsten silicide (WSi), and the word line of the memory cell is formed in the memory cell region. Running directly above the memory cell and connected to the word line of the memory cell at predetermined intervals via a contact called word suspension, the wiring can be observed with a metallographic microscope or an electron microscope as an X address line above the memory cell. there were. However, the word suspension has been abolished due to the reduction of the margin in the manufacturing process and circuit measures, and at the same time, the lower metal wiring of the memory cell area has also been abolished. When searching for a memory cell at a specified address with a metallographic microscope or an electron microscope, it is very difficult to count the address position.

An example of a method for solving this problem is disclosed in Japanese Unexamined Patent Publication No.
This is disclosed in Japanese Patent Application Laid-Open No. 8-141557 (hereinafter referred to as Known Example 1) and Japanese Patent Application Laid-Open No. 59-124752 (hereinafter referred to as Known Example 2).

FIG. 4 is a schematic diagram showing the method disclosed in the first prior art. An address (address) having a concave portion for every 10 addresses of the X address signal line 101 in the power supply line 102
The X address signal lines 101 are easily counted by providing a mark 103 for determining the address, and a mark 103 'for determining the address formed of the convex portion at each 100 address. The same is done for the Y address signal line so that the address of any memory cell on the semiconductor memory device can be easily searched. In addition, a pattern serving as a mark can also be formed by unevenness or change in shape of a base.

FIG. 5 is a schematic layout diagram of a memory array section for explaining the method disclosed in the second prior art. In the manufacturing process of the semiconductor memory device, a mark 1 is formed on a part of the memory array portion 106 in addition to the pattern constituting the element.
05 is attached. In this semiconductor memory device, for example, a mark is provided at every address 5 or every 10 addresses, so that a defective address can be easily found. In addition, the use of a plurality of marks having different shapes or the use of numerals as marks makes it easier to find a defective address.

[0007]

First, in each of the methods disclosed in the above-mentioned known examples 1 and 2, a mark is provided outside the memory cell region, and the defective address is located near the center of the memory cell region. , There is a problem that the effect of the mark is reduced by half.

More specifically, the first problem is that, when a defective address is searched for using a metal microscope or an electron microscope, the X address side and the Y address side have a magnification at which recent miniaturized memory cells can be identified. It is difficult to count the locations of defective addresses while keeping both landmarks in the field of view at the same time.
The address on either one of the X and Y sides can be easily found, but the address on the other side must be searched without a mark, especially in a recent large-scale memory cell area. It has become difficult.

In addition, as in the method of the prior art 1, in order to provide a mark on the power supply line, a power supply line which can be provided with a mark on the outer peripheral portion of the memory cell region or an alternative power supply line is always used. However, the method of the second conventional example has a problem that a region for providing a mark is required.

It is an object of the present invention to provide a semiconductor device which can easily find a memory cell at an arbitrary designated address, regardless of where the address is located in a memory cell area.

Another object of the present invention is to provide a semiconductor device which does not cause a layout restriction even if a mark pattern serving as a mark for determining the address of a memory cell is arranged and formed. .

[0012]

According to the present invention, there is provided a semiconductor device comprising:
In a memory cell region in which a plurality of memory cells are regularly arranged, above the memory cells, addresses arranged and formed in a mesh pattern in the memory cell region with regularity related to the arrangement rule of the memory cells are provided. It has a sign pattern that serves as a mark for determination , and this sign pattern is
Through holes provided under the top layer wiring in the memory cell area
Is composed of rules .

In the memory cell region of the semiconductor device having the marker patterns arranged and formed as described above, the number of marker patterns provided above the memory cells and easily observed can be counted. The memory cell at the specified address can be easily found.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a schematic plan view of a part of a memory cell region according to a first embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view taken along the line AA ′ of FIG. It is sectional drawing shown in FIG.

The memory cell region 1 of the semiconductor device according to the present embodiment is provided for each of a predetermined number of word lines (X address lines) 4 and a predetermined number of digit lines (two, four, or eight are generally used). And a lower metal wiring 9 serving as a through-hole seat. Further, the upper metal wiring 5 and the lower metal wiring 9
Has a through-hole 6 provided as a marker pattern for determining the address of the memory cell region 1 with regularity related to the arrangement pitch of the memory cells. The lower metal wiring 9 left as a through-hole seat serves as a stopper for preventing the through-hole 6 from penetrating to the memory cell portion 7.

With this configuration, in the semiconductor device of the present embodiment, the number of upper metal wires 5 in the memory cell region 1 and
By counting the number of through holes 6 provided in the upper metal wiring 5 with regularity related to the arrangement pitch of the memory cells, it is possible to easily find a memory cell at an arbitrary designated address.

Next, a specific example of a method of arranging the through holes 6 and a method of finding a memory cell at a designated address in a memory cell region having the through holes 6 will be described with reference to FIG.

It is assumed that there is an upper metal interconnection 5 in the memory cell region 1 for every four digit lines of the memory cell.
1 from address 0 of Y address (left side of memory cell area 1)
The word line 4 of the memory cell is located below the upper layer metal wire 5 corresponding to the address (4-1) = 3 of the Y address.
Are provided at positions corresponding to the fifth, 25th, 45th,... X addresses from the 0th address (upper side of the memory cell area 1), and the second from the 0th address of the Y address, that is, ( 4 × 2-1) = 10 under the word line 4 of the memory cell under the upper metal wiring 5 corresponding to address 7.
The through-hole 6 is provided at a position corresponding to the 30th, 50th,..., And below the upper metal wiring 5 corresponding to the fifth to fifth addresses of the Y address, that is, (4 × 5-1) = 19 addresses of the Y address. , A through hole 6 is provided at a position corresponding to the fifth, 25th, 45th, etc. word lines 4 of the memory cell, similarly to the first upper layer metal wiring 5 from the address 0 of the Y address. That is, the same shape is repeated every four upper metal wirings 5. By arranging the through holes 6 with such a regularity, it is possible to easily find the position of the specified address regardless of the position of the specified address in the memory cell area. ing.

A method for finding a memory cell at a specified address in the memory cell area in which the through holes 6 are provided is as follows.

For example, considering the case where the address 105 of the X address and the address 121 of the Y address are designated addresses, the Y address is (121 + 1) / 4 = 30 or more 2 from the 30th of the upper metal wiring 5. It is in the middle of the 31st. Assuming that the X address is the through hole 6 provided below the upper metal wiring 5, the 30th upper metal wiring 5 is the 10th, 30th, 5th, 5th, 5th, and 5th word lines 4 of the memory cell.
There is a through hole 6 in the 0th line. The sixth hole when the through hole 6 is counted corresponds to the address 110 of the X address and is closest to the designated address.
The ninth is the fifth, twenty-fifth word line 4 of the memory cell,
There is a through hole 6 in the forty-fifth line, and the sixth hole corresponds to exactly 105 of the X address.

Therefore, the memory cell of the designated address can be easily found from the extension of the position of the through hole. Even if the address specified in this way is a position slightly deviated from the marker pattern serving as a mark below the closest upper metal wiring 5, the target is to set the marker pattern several lines before or several lines ahead of the upper metal wiring 5. Then, you can easily find it by searching for the location of the specified address.

The method of manufacturing the through-hole 6 provided below the upper metal wiring 5 in the memory cell region of the present embodiment is roughly as follows.

Referring to FIG. 2, first, a word line 4 of a memory cell is patterned, and thereafter, a memory cell portion (detailed structure is not shown) 7 is formed, and an interlayer insulating film 8 is grown. Lower metal wiring layer 9 in cell region
Is left in a cushion shape as a through hole seat and a stopper at a portion where the through hole 6 is opened.
After growing 0, a through hole 6 is opened and the upper metal wiring 5 in the memory cell region is patterned. As described above, the marker pattern for determining the address of the memory cell is formed under the upper metal wiring 5 of the memory cell region in the normal manufacturing process with the regularity related to the arrangement pitch of the memory cells. And there is no layout restriction.

In the present embodiment, the through-hole 6 is provided as a mark pattern for identifying the address of the memory cell provided below the upper metal wiring 5 in the memory cell region.
Is limited to a number that does not hinder the operation of the upper metal wiring 5 provided with the through-holes 6. Further, by devising the shape and arrangement of the through-holes 6, it is possible to find a memory cell at a specified address. It becomes even easier.

Next, a second embodiment of the present invention will be described. The second embodiment is different from the first embodiment in that a marker pattern serving as a mark for determining an address is formed in the uppermost wiring layer in the memory cell region.

FIG. 3 is a cross-sectional view showing a schematic structure of a portion of the sign pattern of the present embodiment.

In the present embodiment, the Y address line 39 is formed of a lower layer wiring located above the memory cell section 7, and a marker pattern 35 serving as a mark for determining an address is formed of an upper metal wiring layer located above the memory cell section 7. It is formed with.
This is because the Y address line is transferred to the lower metal wiring using a through hole at the end of the memory cell area (not shown),
This can be realized by opening the upper metal wiring layer in the memory cell region. As a result, the marker pattern can be arbitrarily arranged and formed so that the address can be most easily identified, and the memory cell at the specified address can be found even more easily.

The other method of arranging the sign patterns and the method of searching for the memory cell at the designated address by using the arranged sign patterns are the same as those in the first embodiment, so that the explanation will be omitted.

[0030]

According to the present invention, a semiconductor device having a memory cell region in which a plurality of memory cells are regularly arranged is provided with a regularity related to an arrangement rule of memory cells in a layer above a memory cell in the memory cell region. Since a mark pattern is provided as a mark for determining the address of the memory cells arranged and formed in a mesh pattern in the memory cell area, even if an arbitrarily designated address is located anywhere in the memory cell area, The effect is obtained that the memory cell at the designated address can be easily found.

Thus, when a failure occurs in the memory cell area of the semiconductor device, it is possible to quickly find the memory cell at the failure address and perform the failure analysis.

Further, the above-mentioned mark pattern serving as a mark is:
As in the through hole described in the embodiment, in a normal manufacturing process, it can be provided in a mesh form with regularity by utilizing a vacant wiring layer or the like above the memory cell. There are no restrictions on the layout.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a part of a memory cell region according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view schematically showing a schematic structure of a cross section taken along line AA ′ of FIG.

FIG. 3 is a cross-sectional view illustrating a schematic structure of a marker pattern portion according to a second embodiment of the present invention.

FIG. 4 is a schematic view showing a method disclosed in a known example 1.

FIG. 5 is a schematic layout diagram of a memory array unit for explaining a method disclosed in a known example 2;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 memory cell region 4 word line 5 upper metal wiring 6 through hole 7 memory cell part 8 interlayer insulating film 9 lower metal wiring layer 35 marker pattern (upper metal wiring) 39 Y address line (lower metal wiring) 10 interlayer insulating film 101 address Signal line 102 Power supply line 103, 103 'Mark for determining address (address) 105 Mark 106 Memory array section

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/3205 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (3)

(57) [Claims] In a semiconductor device having a semiconductor memory element region in which a plurality of semiconductor memory elements are regularly arranged, said semiconductor memory element has a regularity related to an arrangement rule of said semiconductor memory element in a layer above said semiconductor memory element. It has a marker pattern which is arranged and formed in a mesh in the area and serves as a mark for discriminating the address.
Is provided below the uppermost layer wiring in the semiconductor memory element region.
Formed in the lower metal wiring layer at the bottom
Wherein a Oh Rukoto with through holes having a hole seat. 2. A lower metal arrangement according to claim 1, wherein
The semiconductor device according to claim 1, wherein the semiconductor device is shared by a line . 3. A semiconductor device having semiconductor memory element regions in which a plurality of semiconductor memory elements are regularly arranged in a matrix, wherein one of the matrix-like arrangements is provided.
Is the X-axis direction, and the array direction perpendicular to this is the Y-axis direction.
Then, the arrangement pitch of the marker pattern is X axis, Y
With respect to at least one of the axes,
3. The semiconductor device according to claim 1, wherein: (arrangement pitch of the conductor storage elements ) × (a multiple of 5) . 4.