JP2889462B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standard cell type semiconductor integrated circuit in which a plurality of types of standard cells are arranged, and more particularly, to a standard cell type semiconductor integrated circuit incorporating a so-called matrix probing type test circuit. It relates to an integrated circuit.

[0002]

2. Description of the Related Art Conventionally, semiconductor integrated circuits have been used in a wide range of fields.
One is a so-called standard cell system. In this standard cell system, a library of a plurality of types of standard cells, each of which has been confirmed to have a predetermined circuit function, is prepared, and by combining them, a circuit that performs a desired operation as a whole is constructed. It is a method to do. When this standard cell method is used, in terms of wafer manufacturing, it is necessary to make each product from the beginning of the previous process, so it takes more time than the gate array, but the design time is shortened like the gate array In addition, the generation of a wasteful chip area as in the gate array is prevented.

[0003] With the recent increase in the degree of integration of semiconductor integrated circuits, how to test manufactured semiconductor chips has become an increasingly important problem. Various proposals have been made.
One such test circuit is a matrix probing type test circuit. FIG. 5 is a schematic diagram of a test circuit of a matrix probing method, and FIG. 6 is an enlarged view of a portion indicated by a circle A shown in FIG.

[0004] A large number of probe lines 10 are formed so as to extend in the vertical direction in FIG. 5, and a large number of sense lines 20 are formed so as to extend in the horizontal direction. At each intersection of each probe line 10 and each sense line 20, a sense transistor 30 is formed as shown in FIG. One end 31 of the sense transistor 30 is connected to a predetermined node of the internal circuit, and the other end is connected to the sense line 20. The gate of the sense transistor 30 is connected to the probe line 10. The probe line 10 is usually formed of a polysilicon layer so as to also serve as the gate itself of the sense transistor 30. When a certain probe line 10 is started by the probe line driver 40, the probe line 10
Is turned on, and the signal of the node connected to the sense transistor 30 is read out via the sense transistor 30, the sense line 20, and the sense line driver / receiver 50. Is good or bad.

[0005]

The above-described matrix-probing type test circuit has a large number of probe lines 10,
It is necessary to form the sense lines 20 vertically and horizontally, which is suitable for a gate array in which the cell arrangement is regularly determined in advance. However, in the case of the standard cell system, the cell size also differs depending on the type of the cell. In addition, since the position of a node in the cell requiring a sense also differs depending on the type of the cell, the probe line cannot be formed linearly as shown in FIG. 5, and in particular, the probe line is formed of a polysilicon layer. When forming, a problem is how to adapt the matrix probing type test circuit to a standard cell type semiconductor integrated circuit.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor integrated circuit in which a test circuit of a matrix probing method adapted to a standard cell method is incorporated.

[0007]

According to the present invention, there is provided a semiconductor integrated circuit according to the present invention, wherein a plurality of probe lines extend in a predetermined first direction and a predetermined second direction intersects the first direction. A plurality of sense lines extend in the direction, and a matrix probing type test circuit for sensing a signal of each node near each intersection by each sense transistor arranged at each intersection of each probe line and each sense line is incorporated. Further, in the standard cell type semiconductor integrated circuit, each of the probe lines is formed of a polysilicon layer also serving as a gate of a sense transistor, and the standard cell has a constant dimension in the first direction regardless of the type. And the dimension in the second direction is variable length for each type, and furthermore, a plurality of stander lines of the probe wires are arranged in the first direction. The probe line passing through the inside of the standard cell is connected to the second end of the end of the standard cell in the first direction such that the portion connecting the cells is arranged on each straight line extending in the first direction. The position in the direction of is determined.

[0008]

According to the semiconductor integrated circuit of the present invention, each of the standard cells has a second probe line at the end in the first direction.
Is determined according to a predetermined rule as described above, so that the matrix-probing type test circuit is suitable for a standard cell type semiconductor integrated circuit.

[0009]

Embodiments of the present invention will be described below. FIG. 1 is a diagram showing the structure of a cell according to one embodiment of the present invention. The size of the cell in this embodiment in the vertical direction in FIG. 1 is constant irrespective of the type of cell, and the method in the horizontal direction in FIG. 1 is variable in length according to the circuit size inside the cell.

In the cell, probe lines made of a polysilicon layer extend in the vertical direction in FIG. 1. In the cell, the distance between the probe lines is varied according to the position of the node to be sensed. However, the positions in the left and right directions at the upper and lower edges are constant regardless of the cell. Here, the distance between the adjacent probe lines in the left-right direction at the upper and lower ends is, as shown, a distance A, a distance B (A ≧ B).
When an even number of probe lines are present in the cell as shown in the figure, the interval between the end portion in the left-right direction of the cell and the adjacent probe line is equal to or less than the wider interval A. When an odd number of probe lines exist, one of them is equal to or less than the interval A, and the other is equal to or less than the interval B. This is a limitation due to the necessity of arranging a probe line adjacent to this cell. In this cell, a power supply line, a ground line, and a sense line are also supposed to be wired with a single metal layer at the positions shown in the figure.

FIG. 2 is a schematic diagram showing a cell disposable area in a chip. The probe lines finally connected to each other are arranged in the wiring channel region so as to be straight in the wiring channel region in the vertical direction in the drawing, and so that their intervals are alternately A and B. The position of the probe line in is predefined. Each cell is arranged in the cell arrangable area. At this time, the cells are arranged so that the probe line in the cell is connected to the probe line in the wiring channel area.

FIG. 3 is a schematic diagram showing a state where each cell is arranged in the cell arrangement possible area. As shown in the drawing, the probe line in the cell is connected to the probe line in the wiring channel region in the portion where the cell is arranged. However, in this state, there is a probe line which is not divided and the probe line remains separated. Then, the separated probe wire is connected next.

FIG. 4 is a schematic diagram showing a state of connecting the divided probe wires. In the illustrated example, a cell (feedthrough cell) for connecting the probe line is prepared in the library, and the cell is not arranged. Therefore, the feedthrough cell is arranged in a place where the probe line is not connected depending on the cell. As a result, all the probe wires are connected to one wire.

After that, as in the ordinary placement and routing processing,
The power supply line and the ground line are connected, and this processing includes the sense line and the connection. In addition, signal lines are also wired, thereby realizing a standard cell type semiconductor integrated circuit in which a test circuit of a matrix probing method is incorporated.

[0015]

As described above, according to the present invention,
By adopting a design method that can be easily mounted on a currently available placement and routing tool, a standard cell type semiconductor integrated circuit incorporating a matrix probing type test circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing the structure of a cell according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a cell disposable area in a chip.

FIG. 3 is a schematic diagram showing a state where each cell is arranged in a cell arrangement possible area.

FIG. 4 is a schematic diagram showing a state in which a divided probe wire is connected.

FIG. 5 is a schematic diagram of a test circuit of a matrix probing method.

FIG. 6 is an enlarged view of a portion indicated by a circle A shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Probe line 20 Sense line 30 Sense transistor 40 Probe line driver 50 Sense line driver / receiver

──────────────────────────────────────────────────の Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) H01L 21/82 H01L 21/66 H01L 21/822 H01L 27/04

Claims (1)

(57) [Claims] A plurality of probe lines extending in a predetermined first direction and a plurality of sense lines extending in a predetermined second direction intersecting the first direction; A standard cell system in which a plurality of types of standard cells are arranged, in which a matrix probing system test circuit for sensing a signal of each node near each intersection by each sense transistor arranged at each intersection with a sense line is incorporated. Wherein each of the probe lines is formed of a polysilicon layer also serving as a gate of the sense transistor, wherein the standard cell has a constant dimension in the first direction regardless of the type, and The dimension in the second direction is variable for each type, and a plurality of standard cells of each probe line are arranged in the first direction. The second portion of the end of the standard cell in the first direction of each probe wire passing through the inside of the standard cell, such that portions connecting the cattle are arranged on each straight line extending in the first direction. Characterized in that the position in the direction is determined.