JP3061884B2 - Analog-to-digital conversion system and spectral histogram generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION This invention relates to pulse height spectrum analyzers and, more particularly, to an analog to digital conversion system for such analyzers.

[0002]

2. Description of the Related Art A pulse-height spectrum analyzer for displaying a probability distribution of the amplitude of an electric signal.
spectroscopic analysers)
There is. An analog-to-digital converter (analog-to-digital converter) used in this analyzer
inverters: hereinafter, referred to simply as ADCs, include differential non-linearity (differential non-linearity).
-Lineality: hereinafter, simply referred to as DNL) and a short conversion time. Commercially available ADCs cannot be directly applied to spectral measurements. The reason is that in the case of these spectrum measurements, the applied DNL is (± 1) LS
B (the least significant bit (± 1 least signif
icantbit (LSB)).
i) in some cases. When applied to spectral measurements, the large DNL described above is unacceptable for spectral measurements because the DNL is required to be (± 1/100) LSB. Such a DNL
Many technological developments have been made to achieve the demands on the technology. These developed techniques have become significantly more complex due to greater utilization of the full dynamic range of the ADC and higher resolution.

Reference: "Nucl. Instru. And
Meth. (Nuclear Instrument and Method) "No. 24 (1963), p241
(Cottini, C., et al.)
Standard sliding scale (s
A riding scale method is disclosed. According to the system of this document, an auxiliary incremental analog signal is applied to the ADC input.
channel (also referred to as a bin) obtained by adding an analog signal (binning average).
(ffect). That is, in this case, A
After the D conversion, the digital amount of the auxiliary incremental analog signal is subtracted from the ADC output to obtain a true digital amount of the ADC input.

FIG. 1 shows a block diagram for executing the method disclosed in this document. This conventional method will be described below. In order to perform the ADC conversion, a plurality of conversion points (conversion points (ADC co.
version point)) to provide each ADC
A different channel is assigned to each input value.
Then, the digital output of the ADC after subtraction obtained through each channel is averaged to obtain the above-mentioned true digital value. This process is a process for statistically equalizing the channel width (statistical equalization).
n).

[0005]

The main problem with this prior art method is that the dynamic range of the ADC is reduced by an amount equal to the auxiliary level range. In this regard, see the literature: “Nuc
l. Instru. and Meth. (Nuclear Instrument and Method) "No. A2
35 (1985), p536 (Correia, C.I.
B. A. (Correia C.B.A.)).

When the increment signal is positive, the increment signal is added to the input voltage of the ADC. And M
Is the number of channels swept by the averaging digital-to-analog converter (DAC), ie, used for averaging, the magnitude of the input voltage value is M channels above the full dynamic range of the ADC. It is limited to a size that can fit within the range deducted by the minute. This restriction creates a dilemma. This is because averaging (avera) is required to keep the input range wide.
ging) The sweep range of the DAC must be narrow, but the sweep range must be sufficiently large to make the averaging effect effective.

In a recent approach to solving this problem, in order to avoid the dynamic range from being narrowed (waste), the voltage value of the ADC input is set to the lower half and the higher half of the ADC dynamic range. The averaging process (average) on the upper side (downward) or on the lower side (downward), depending on which one is supported.
ng). For a description of such an approach, see the literature: "Nucl. Instru. And
Meth. (Nuclear Instrument and Method) "No. A259 (1987), p52
1 (Xianjie, X.)
Is disclosed. In this method, a circuit for determining whether to perform averaging on the upper side or averaging on the lower side is provided in the ADC, and a comparator and a circuit are provided somewhere in the middle of the full dynamic range of the ADC. Trip
Point (comparator trip point)
t), that is, a threshold value (level) for determination is established. If the amplitude of the input signal exceeds this threshold value, lower averaging is performed.
Otherwise, the averaging process on the upper side is performed.

[0008] However, the threshold value is the upper or lower (2 ^M -1) (where M is the number of slidings bits).
cale bits). This approach is also problematic, since it must not be present in one) channel.
The channel width of the channel where the threshold value exists is not averaged. In order to equalize the channel width of this specific channel, a triangular voltage (tr)
It is necessary to modulate the threshold value by angular voltage. Successive approximation ADC
(Successiveapproimation ADC), usually, the DNL is in the area of 1/2, 1/4 and 3/4 of the full scale.
Is in the worst case. Therefore, the modulation region of the threshold value cannot be set in the above-mentioned area, and the modulation region overlaps with the upper and lower (2 ^M −1) channels. Should not be done. For this reason, if the full dynamic range is an N-bit ADC, the maximum of the number M of sliding scale bits is limited to (N−2). Here, N is the resolution of the ADC.

Further complicating the problem is a new type of fast subranging ADCs.
Then, internal transition between ranges (internal tra
The problem is that the DNL is not good. According to the internal architecture of this type of ADC, first the flash conversions are performed on the seven MSBs (most significant bit).
ion), and then processes five LSBs (least significant bits) (2 ⁵ (2 5) = 32). This creates an internal split point that indicates the bad DNL associated with that bit. ADC products use various technologies,
The DNL area varies from device to device.

An object of the present invention is to provide an ADC system which is simplified as compared with the conventional one. In order to solve the above-mentioned problems, the DNL is small, and high stability and high accuracy are achieved without complicating the circuit. Is to provide an ADC system using a technology that can be realized.

[0011]

In order to achieve this object, according to the invention of the present application, a sampling means for sampling an analog voltage signal; a comparator; a sampled analog voltage signal from the sampling means. Adding means having a first input terminal to which is input and an output terminal connected to the first input terminal of the comparator; a digital number generating means for generating a variable digital count number; A bipolar input terminal connected between the second input terminal of the adding means and the variable digital count number to an analog quantity.
A digital-to-analog converter (DAC); an analog input terminal connected to the output terminal of the adder and the second input terminal of the comparator, An analog-to-digital converter (ADC) having a reference voltage output terminal for outputting the full-scale reference voltage so as to determine whether the output exceeds the full-scale reference voltage;
Control means comprising the digital number generation means and the analog-to-digital converter, wherein the output of the addition means is provided by the addition means in response to the output of the comparator. If the output exceeds the full-scale reference voltage, an output representing the difference between the analog amount and the sampled analog voltage signal is generated. Said control means for producing an output representative of the quantity and said sampled analog voltage signal;
And an input terminal connected to the digital output terminal of the analog-to-digital converter and another input terminal connected to the digital number generating means. Removing the contribution of the variable digital count to the output of the converter, i.e., if the output of the adder is less than the full-scale reference voltage, the digital output of the analog-to-digital converter. The variable digital count is subtracted from the variable digital count, and the variable digital count is added to the digital output of the analog-to-digital converter when the output of the adding means is larger than the full-scale reference voltage. And an addition processing means that operates as described above.

In accordance with a preferred embodiment of the present invention, the control means includes means for providing the output of the comparator to the most significant bit (MSB) input terminal of the bipolar digital-to-analog converter. Preferably, the arrangement is operable to invert the polarity of the analog quantity from the bipolar digital-to-analog converter when the output exceeds the full-scale reference voltage.

According to another preferred embodiment of the present invention, the sampling means is preferably a track and hold circuit.

According to still another preferred embodiment of the present invention, the digital number generating means may be a circuit for generating sequential numerical values.

According to yet another preferred embodiment of the present invention, there is provided a computer which accumulates the number of times each value of an input signal falls within a specific range and generates a histogram of the input signal based on the accumulation. Is good.

According to the invention of the method for generating a histogram of a spectrum of the present application, a detector detects nuclear particles and generates a voltage specific to the nuclear particles as an analog input signal. Generating a variable digital count number; converting the variable digital count number into an analog quantity; adding the specific voltage and the analog quantity to obtain an added value; By comparing with the full-scale reference voltage of the digital converter, (1) when this added value is smaller than the above-mentioned full-scale reference voltage, a) the added value is converted from analog to digital to digitally converted addition. Value, and b) this digital conversion Subtracting said variable digital count number from said sum to produce a digital output representative of said particular voltage; and (2) if said sum is greater than said full scale reference voltage, a) subtracting the aforementioned analog quantity from the aforementioned specific voltage to obtain a subtracted value; b) performing an analog-to-digital conversion on the subtracted value to obtain a digitally converted subtracted value; Reconstructing the digital output of the analog input signal by adding a digital count to the subtracted value; further distributing all digital outputs to a corresponding one of the continuous channels; and By accumulating the number of times the aforementioned digital output enters each of these channels with an interval of A configuration including a step of creating data on ram.

In accordance with a preferred embodiment of the method, each detected specific voltage may be tracked and held in reserve.

[0018]

As is apparent from the above configuration, the sliding scale averaging technique of the present invention can be applied to an analog-to-digital converter (ADC). Prior to conversion of the analog signal, a variable number is added to this analog signal (su
mming) to obtain an addition signal. As a result, the input voltage signal having the same value, which is obtained repeatedly, is converted by different channels (bins) of the ADC converter to minimize errors caused by unequal channel widths (bin widths). In the present invention, the addition (sum
ed) Includes comparison techniques to ensure that the signal does not exceed the full dynamic range of the ADC.

For this reason, in the case of an N-bit analog-to-digital converter (ADC), the number of bits M with respect to the sliding scale was conventionally (N-2), but according to the present invention, the number of bits M is N. And can be increased.

Thus, the full dynamic range of the ADC can be maintained and 100% averaging is obtained. Therefore, in the present invention, the modulation circuit required in the conventional method is no longer required. Due to this change in the design, the number of components is reduced, the complexity of the circuit configuration is eliminated, and the stability of the circuit can be improved.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the present invention, a prior art will be described with reference to FIG. The present invention is an improvement over the prior art. The conventional ADC circuit 8 performs analog-to-digital conversion (convers) on a number of continuous channels.
ions). Certain of these channels are associated with the value of the analog input voltage. These channels have the same channel width. Thus, if the values of the respective input voltage signals are distributed over the full dynamic range of the converter, these signals should be uniformly distributed on each channel. However, in practice, some channels (bins) have a wider channel width than other channels, and therefore are not uniformly distributed in each channel. To avoid this problem, the prior art shown in FIG. 1 basically converts the same input voltage into different periods by shifting the level of the input voltage to the converter to various values. The conversion is performed on separate channels of the shifter, that is, on the channels corresponding to the shift levels. By performing the level shift and conversion in this manner, errors in this channel are averaged, so that the influence of the errors can be minimized.

To understand how this is achieved, a further explanation is given with reference to FIG. In FIG.
The number generator is a means for performing the level shift described above. The generator 1 may be a conventional random number generator or a sequential numerical generator. The output of the generator 1 is a digital signal (digital value) and is also an input of the DAC 3. After being converted into an analog signal (analog value), the generated analog value is transferred via a line 4 to an integrated operational amplification adder (uni).
ty operational amplifier
and the analog value and the input voltage VIN (input to the input terminal 6) in the adder 5.
And (addition). By this addition, an added value, that is, an analog level shift signal is obtained on line 7. As a result, the output obtained on line 7 becomes the input of ADC 8. Thus, for the same input voltage, the sums (analog level shift signals) generated on line 7 during two successive periods will take different values, and these sums will be converted by the different channels of ADC 8. You. The important thing here is to reconstruct the original input voltage (restore:
restoring). This restoration processing is performed by the digital subtractor 11. This subtractor has a first level shift input "a" and a second input "b" to which a number generator is connected via connection 10. The subtractor 11 subtracts the number generated from the number generator 1 to reconstruct the original voltage. As a result, any conversion errors due to unequal channel widths are averaged because the conversion for the same value of the input voltage signal is performed in different channels of ADC 8.

A computer 13 is connected to an output terminal of the subtractor 11 to obtain a spectrum distribution of the input voltage. In this computer, an amplitude probability distribution is obtained according to a well-known technique, and a count number (count) for a specific input voltage is obtained.
s) is the ADC channel number (ADC channel).
It is possible to obtain a histogram as a function of number.

FIG. 4 shows a typical amplitude probability distribution obtained from a direct-feed ADC 8 not utilizing the averaging technique described above. In the case of the ADC 8 connected as shown in FIG. 1 and incorporating the averaging technique described above, the distribution shown in FIG. 4 has features that are sharper and more distinct. However, as already explained, the dynamic range of the ADC depends on the adder 5.
Is reduced by the amount that the level (auxiliary amount) supplied to is supplementarily level-shifted.

Next, the configuration of an analog-to-digital conversion system improved by the present invention will be described with reference to FIG. The system shown in FIG. 2 similarly implements the channel (bin) averaging technique, but avoids the problems described in connection with the conventional device shown in FIG. This will be described in more detail. First, a track-and-hold circuit (track-and-hold circuit) 1 serving as a sampling means.
6 samples an input voltage input to the terminal 15, that is, an analog voltage signal. For example, when applied to the spectrum measurement of the Nuclear particle (nuclear Particls), such as the system such as ⁶⁰ Co, ¹¹³ Sn, ²³² TH is the analog voltage signal, the voltage peculiar to these Nuclear Particle Signal.

The sampled analog voltage signal output from the track-and-hold circuit 16 is supplied to a first input terminal 17 of an integrated gain operation amplification adder 14 serving as an adding means.
Is input to The second input to the adder 14 is provided to a second input terminal 18. This second input is the analog quantity of the digital count at the time of sampling.

Counter 20 as digital number generating means
Is basically a sequential number generator, the output of which is a variable digital count. Bipolar digital-to-analog converter (DAC) 22 includes a counter 20
And the second input terminal 18 of the adder 14. The output of the counter 20 is input to the input terminal LSB's of the least significant bit (LSB) of the bipolar digital-to-analog converter (DAC) 22 and
It is output as an analog quantity from C22.

The system of the present invention further includes an analog-to-digital converter (ADC) 28. This A
The DC 28 is a reference voltage output connected to an analog input terminal 27 connected to the output terminal 24 of the adder 14 and a second input terminal of a comparator (also referred to as a threshold comparator or a level comparator) 26. And a terminal 29.
The reference voltage output terminal outputs a full-scale reference voltage (output) to the comparator 26. The comparator 26 is supplied with the full-scale reference voltage so that the adder 1
It is possible to determine whether or not the output supplied from 4 exceeds this full-scale reference voltage.

Prior to the AD conversion, first, an addition value (also referred to as an addition signal) output from the adder 14 is output from the ADC 2.
8 is compared with the voltage value corresponding to the full range to determine whether or not the added signal is out of the full range. To make this determination, ADC 28 generates a full-range output signal at its reference voltage output terminal 29 (REF OUT). This full-range output signal is used as the "B" input of the threshold comparator
It is supplied to the input terminal. The output of the adder 14 is supplied directly to the first input terminal as the "A" input of the comparator 26. The full-range output signal of the ADC 28 is a reference signal for comparison in the comparator 26, that is, the above-described full-scale reference voltage (output) “B”.

The above-described adder 14, counter 20, and bipolar DAC 22 cooperate to form control means. The control means causes the adder 14 to generate an output responsive to the comparison output of the comparator 26. That is, when the output of the adder 14 exceeds the full-scale reference voltage, the adder 14 produces an output representing the difference between the analog amount from the bipolar DAC 22 and the sampled analog voltage signal. When the output of the adder 14 does not exceed the full-scale reference voltage, the bipolar DA
An adder 14 produces an output representing the sum of the analog quantity from C22 and the sampled analog voltage signal. This point will be further described.

As a result of the comparison processing by the threshold comparator 26, this full-scale reference voltage (output) "B"
If the sum is larger than the addition signal “A” obtained by the addition by the adder 14, a binary “0” is generated as a comparison output from the output terminal of the comparator 26. In the binary signal of “0”, the most significant bit (M
SB) is not set, and the DAC 22 operates as described in connection with the conventional circuit shown in FIG. As a result, in this case, the ADC 28 performs the averaging process on the upper side.

However, as a result of the comparison processing in the comparator 26, when the addition value "A" in the adder 14 is larger than the full scale (full range) reference output "B",
A binary "1" is generated as a comparison output from the comparator 26,
This binary signal is sent to the MSB input terminal of the DAC 22. For this reason, the polarity of the analog amount output from the DAC 22 is inverted and added to the adder 14. As described above, the adder 14 subtracts the inputs 17 and 18, and the analog output from the adder 14 is converted to the ADC 28.
Not to exceed the full range of As a result, in this case, the ADC 28 performs the averaging process on the lower side.

The system according to the present invention further includes a digital adder 30 as addition processing means. ADC28
Is supplied from its digital output terminal (DOUT) to one input terminal "A" of a digital adder (adder) 30. The parallel output terminal of the counter 20 is connected to the other input terminal “B” of the digital adder 30.

The digital adder 30 is addition processing means for performing two's complement addition processing. This addition is actually
The variable digital count is subtracted from the output of ADC 28 so that output 32 of adder 30 is the digital conversion of the analog input voltage signal at terminal 15. However, the sum of the two quantities of adder 14 is ADC2
Over the full-scale (full-range) reference voltage of 8
When the MSB terminal of the AC 22 is set, the comparison output of the threshold comparator 26 is supplied from the output terminal 25 to the “carry-in” of the digital adder 30.
n) "is supplied to the" input terminal, whereby normal addition is performed. In other words, the adder 30 removes the influence (contribution component) of the variable digital count of the counter 20 from the output of the ADC 28. When the output of the adder 14 is smaller than the full-scale reference voltage, the adder 30 adds the analog input signal and the analog amount, The converted sum is obtained as a digital output, and the variable digital count is subtracted from the digital output (digital converted sum) of the ADC 28. On the other hand, the adder 30 sets the output of the adder 14 to a full-scale reference. If the voltage is larger than the voltage, the adder 14 subtracts the analog amount from the analog input signal, And in ADC 28, to obtain a digital converted subtraction value as a digital output and digital conversion, adds the number of variable digital count to the digital output of the ADC 28 (digital converted subtraction value).

As a result of the addition / subtraction processing in the digital adder 30, an appropriate digital output (DOUT) is again obtained from the adder 30. This digital output represents a digital quantity corresponding to the input voltage at the input terminal 15. As described above, the digital output corresponding to the analog input voltage is reconstructed and output from the adder 30.

In the preferred embodiment of the present invention, the ADC 28
Is a 14-bit converter, like the bipolar DAC 22. To ensure that the analog input is properly converted, the other input terminal "B" of the adder 30 includes a terminal for receiving the 13-bit output of the counter 20, and the most significant bit (MSB) Is received as the MSB terminal 36. The MSB terminal 36 is connected to the output terminal 25 of the comparator 26 and the control carry input terminal 34.

The result of adding the input voltage and the DAC voltage is AD
If it exceeds the dynamic range of C28, the normal (r
The threshold trigger input to the ADC is constantly changing as the subtraction of the (eg in the adder 14) averaging process is performed. Therefore, in the present invention, conventionally required,
There is no need to provide a modulation circuit for averaging the threshold points (levels).

Further, since the digital output terminal of the digital adder 30 is connected to the computer 13, it is possible to generate a histogram clearly showing the amplitude probability distribution as shown in FIG. That is, the computer 13 distributes the digital output to any one of the continuous channels and accumulates the number of times that the value of the input signal is within a specific range. Generate a histogram. The distribution of FIG. 3 merely illustrates the potential of the invention that can be realized in a spectroscopy system. FIG.
Shows the advantage of the averaging technique over a histogram obtained without using the averaging technique illustrated in FIG.

[0039]

Thus, according to the present invention, a new sliding scale averaging technique has been developed which utilizes a large number of bits for the sliding scale. as a result,
100% averaging is obtained, so that the differential nonlinearity can be improved by a factor of 4 while still maintaining the full dynamic range of the ADC. Since the conventional modulation circuit is no longer required, the number of circuit components is reduced, the circuit configuration is simplified, and the problem of potential drift is reduced. Also, the number of constituent circuits is reduced,
The stability of the circuit also increases.

The present invention is not limited to the embodiments described above, but it will be apparent to those skilled in the art that many changes or modifications may be made.

[Brief description of the drawings]

FIG. 1 is a conventional block diagram.

FIG. 2 is a block diagram of the present invention.

FIG. 3 is a diagram in which a histogram obtained by channel averaging is plotted.

FIG. 4 is a diagram plotting a histogram obtained without performing channel averaging.

[Explanation of symbols]

 13: Computer 14: Integrated gain operation amplification adder 15: Terminal 16: Track and hold circuit 17: First input terminal 18: Second input terminal 20: Counter 22: DAC 23: MSB input terminal 24: Output terminal 26 : Threshold comparator 28: ADC 29: output terminal 30: digital adder 34: control carry input terminal 36: MSB terminal

Continued on the front page (72) Inventor Martin Kesselman Com Mac Glenmere Lane, New York, USA 39 (72) Inventor Anthony Earl Serona, USA No Sport, New York. Rainway 5 (56) References JP-A-63-33012 (JP, A) JP-A-62-230120 (JP, A) JP-A-62-112221 (JP, U) (58) Fields investigated (Int. Cl. ^7, DB name) H03M 1/20 G01R 19/17 G01R 19/25 G01R 29/02 H03M 1/40

Claims (7)

(57) [Claims] A sampling means for sampling an analog voltage signal; a comparator; a first input terminal to which a sampled analog voltage signal from the sampling means is input; and a first input terminal of the comparator. Adding means having an output terminal, a digital number generating means for generating a variable digital count number, the digital number generating means being connected between the digital number generating means and a second input terminal of the adding means; A bipolar digital-to-analog converter (DAC) for converting the count number into an analog quantity, an analog input terminal connected to the output terminal of the adding means, and a second input terminal of the comparator;
An analog-to-digital converter (ADC) having a reference voltage output terminal for outputting the full-scale reference voltage so that the comparator can determine whether the output of the adding means exceeds the full-scale reference voltage. Control means comprising the adding means, the digital number generating means, and the analog-to-digital converter, wherein the output of the adding means is provided by the adding means in response to an output of the comparator. When the voltage exceeds the reference voltage, an output representing the difference between the analog amount and the sample / analog voltage signal is generated, and when the output of the adding means does not exceed the full scale reference voltage, the analog amount and the analog amount are output. The control means, and the analog-to-digital converter, for producing an output representative of a sum with a sampled analog voltage signal. A digital input terminal connected to the digital output terminal of the digital converter and the other input terminal connected to the digital number generation means, and the output of the analog-to-digital converter is Adder processing means for removing the effect of the variable digital count number on the variable digital count number from the digital output of the analog to digital converter when the output of the adder means is smaller than the full scale reference voltage. And adding the variable digital count number to the digital output of the analog-to-digital converter when the output of the adding means is greater than the full-scale reference voltage. Analog-to-digital conversion system. 2. The analog-to-digital conversion system according to claim 1, wherein said control means receives an output of said comparator at a most significant bit (MSB) input terminal of said bipolar digital-to-analog converter. An analog-to-digital converter operable to invert the polarity of the analog quantity from the bipolar digital-to-analog converter when the output of the adder exceeds the full-scale reference voltage. system. 3. The analog-to-digital conversion system according to claim 1, wherein said sampling means is a track-and-hold circuit. 4. The analog-to-digital conversion system according to claim 1, wherein said digital number generating means is a circuit for generating a numerical value in sequence. Digital conversion system. 5. The analog-to-digital conversion system according to claim 1, further comprising the step of storing the number of times that the value of the input signal falls within a specific range. An analog-to-digital conversion system, comprising: a computer that generates a histogram of the input signal based on the data. 6. Detecting nuclear particles with a detector and generating a voltage specific to the nuclear particles as an analog input signal; generating a variable digital count number; Converting the digital count number into an analog quantity; adding the characteristic voltage and the analog quantity to obtain an added value; comparing the added value with a full-scale reference voltage of the analog-to-digital converter; (1) if the sum is less than the full scale reference voltage: a) analog-to-digital conversion of the sum to obtain a digitally converted sum; and b) By subtracting the variable digital count, Generating a digital output representative of a voltage; and (2) if the sum is greater than the full scale reference voltage: a) subtracting the analog quantity from the characteristic voltage to obtain a subtracted value; b) Performing an analog-to-digital conversion on the subtracted value to obtain a digitally converted subtracted value; c) reconstructing a digital output of the analog input signal by adding a digital count number to the digitally converted subtracted value. Further distributing all digital outputs to corresponding ones of consecutive channels; and generating data relating to the histogram by accumulating the number of times the digital outputs enter each of the channels having a predetermined interval. Generating a spectrum histogram. 7. The method of claim 6, wherein each detected unique voltage is preliminarily tracked and
A method for generating a histogram of a spectrum, characterized by holding.