JP3058900B2 - Scan speed modulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a scanning speed modulation circuit for performing a contour compensation by modulating an electron beam horizontal scanning speed of a picture tube in a color television receiver or the like. In particular, the power loss in the output amplifying unit is reduced, and the image quality is improved.

(Prior Art) As a means for correcting the contour of a television image, a device using a scanning speed modulation circuit for changing the horizontal scanning speed in accordance with a video signal and correcting the horizontal scanning speed is known. This principle will be described with reference to the waveforms of FIG. FIG. 3 (a) is a video signal waveform, and the brightness of the signal on the screen of the cathode ray tube is increased because the beam spot has a certain spread.
As shown in the figure, the luminance changes with the edge portion removed. To correct this, the contour correction signal currents A and B obtained by differentiating the video signal are superimposed on the horizontal scanning current that changes linearly with time as shown in FIG. 3c. Good. That is, since the screen luminance is inversely proportional to the scanning speed, the screen becomes darker at a portion where the scanning speed is fast and becomes brighter at a portion where the scanning speed is slow. As a result, a screen image in which an edge portion is enhanced as shown in FIG. 3D is obtained. As means for performing such scanning speed modulation, an auxiliary deflection coil is generally mounted on the outer periphery of the neck portion of the color picture tube, and a correction current is supplied to the auxiliary deflection coil to change the scanning speed of the edge portion to change the image quality. Improve.

FIG. 4 shows an example of such a contour correction device using scanning speed modulation. In FIG. 4, the antenna section
1, a tuner section 2, a VIF amplification detection section 3, a video signal amplification section 4, a horizontal deflection section 5, a vertical deflection section 6, a video signal output amplification section 7, a horizontal deflection coil 8, a vertical deflection coil 9, and a cathode ray tube 10. The configuration is exactly the same as that of a general receiver, and a description thereof will be omitted.

Further, in FIG. 4, reference numeral 16 denotes a scanning speed modulation circuit unit, which applies the output signal of the video signal amplification unit 4 to the amplification unit 11, differentiates the output by the differentiation circuit unit 12, and amplifies the output by the amplification unit 13. Further, the power is amplified by the output amplifying unit 14, and the auxiliary deflection coil 15 for scanning speed modulation is driven.

In such a scanning speed modulation circuit, while the edge portion becomes sharp, the S / N of the entire screen deteriorates,
It has been clarified that the power consumption at the output of the speed modulation circuit is very large depending on the type of image. So far, Japanese Patent Publication No. 56-13064 (contour correction device) A solution as described in Japanese Patent Publication No. 56-13066 (scanning speed modulation circuit) has been proposed.

FIG. 5 shows a configuration example of a scanning speed modulation circuit based on the method proposed in Japanese Patent Publication No. 56-13066. Fifth
In the figure, the differentiating circuit unit 12 and the amplifying stage in FIG.
Circuits corresponding to 13 and 14 are shown. Reference numeral 25 is a video signal input terminal, 26 is a coupling capacitor, 27 and 28 are resistors and coils for forming a differential signal, 29 is a coupling capacitor,
30 and 31 are bias resistors of the transistor 32, 32 is an amplifying transistor, 33 is an emitter resistor of the transistor 32, 34
Denotes a high-frequency compensation capacitor inserted in parallel with the emitter resistor 32, and 35 denotes a collector resistance of the transistor 32. Reference numerals 37 and 38 denote complementary grounded collector transistors. An emitter current limiting resistor 39 is connected between the emitters of both transistors. 40 and 41 are damping resistors, 42 and 43 are coupling capacitors, 45, 46, 47, 48 and 49 are bias resistors of output stage transistors 50 and 51, and 52, 53, 55 and 56 are emitters of output stage transistors 50 and 51. The resistors 54 and 57 are smoothing capacitors. Reference numeral 58 denotes an auxiliary deflection coil for performing velocity modulation, and reference numeral 59 denotes a coupling capacitor of the auxiliary deflection coil 58.
Reference numerals 36 and 44 denote power supply terminals connected to the DC power supplies + B1 and + B2, respectively.

 The operation of the circuit shown in FIG. 5 will be briefly described.

First, the video signal applied to the input terminal 25 is
The signal is differentiated by a differentiating circuit comprising a coil 28 and a scanning speed modulation signal. This differential signal for scanning speed modulation is voltage-amplified by the amplifying transistor 32, and this signal is further current-amplified by the next-stage transistors 37 and 38. The differential signal for contour correction is further amplified by the output stage transistors 50 and 51, and a correction current for scanning speed modulation is supplied to the auxiliary deflection coil for speed modulation 58 connected to the collector.

By the way, in the scanning speed modulation circuit configured as described above, if the video signal supplied to the input terminal 25 is a signal having a poor S / N or a signal having many high frequency components, the speed of the auxiliary deflection coil 58 is reduced. The modulation correction current increases,
The power supply current also increases. For this reason, in the circuit of FIG. 5, a parallel circuit of a resistor 53 and a smoothing capacitor 54, a resistor 56 and a smoothing capacitor 57 are provided on each emitter side of the output stage transistors 50 and 51.
The increase of the power supply current is suppressed by inserting the parallel circuit of each. That is, the output stage transistor normally operates in class B or class AB. However, when the signal has a poor S / N or a signal with many high frequency components, the output stage transistors 50 and 51 are used.
And the DC voltage generated in the parallel circuit of the resistor 53 and the smoothing capacitor 54 increases (the same applies to the parallel circuit of the other resistor 56 and the smoothing capacitor 57). Becomes a reverse bias, and a class C operation state is established. In other words, in the case of a signal having a poor S / N or a signal having many high-frequency components, a base clip is applied at the output amplification stage. In other words, the normal signal operates in class B and the S /
When the signal has a bad N or a signal with many high-frequency components, it can be operated in class C, suppressing the increase in power supply current and
The base clip has an effect that a correction current generated by differentiating a noise signal can be removed, or overcorrection of a fine image having many high-frequency components can be suppressed.

As described above, in the conventional scanning speed modulation circuit, a resistor and a smoothing capacitor are inserted into the emitter of the output stage transistor as a means for suppressing an increase in the power supply current when a signal having a poor S / N or a signal having many high frequency components is used. When the emitter current increases, for example, by controlling the base-emitter voltage in the reverse bias direction, the increase in the emitter current can be suppressed to a predetermined amount, and the speed modulation effect can be limited to an appropriate amount. However, an unnecessary high voltage is supplied to both ends of the collector and the emitter of the output stage transistor, and there is a disadvantage that the power loss of the output stage transistor is large.

(Problems to be Solved by the Invention) As described above, the conventional scanning speed modulation circuit has a problem that a high voltage is applied between the collector and the emitter of the output stage transistor, and the power loss of the output stage transistor is large.

Therefore, the present invention has been made in view of the above-described problem, and when a signal having a poor S / N or a signal having many high-frequency components is present, similar to the conventional example,
Controlling the base-emitter voltage of the output stage transistor in the reverse bias direction, performing base clipping to suppress an increase in power supply current, removing correction current due to noise signals, or overcorrecting fine images with many high-frequency components It is another object of the present invention to provide a scanning speed modulation circuit capable of suppressing the power loss of the output stage transistor by simultaneously reducing the collector-emitter voltage of the output stage transistor.

[Structure of the Invention] (Means for Solving the Problems) The scanning speed modulation circuit of the present invention comprises a push-pull output stage transistor connected to an auxiliary deflection coil for speed modulation.
About one emitter circuit, the emitter circuit on the power supply side
In this configuration, a voltage reduction circuit is inserted, and a constant voltage circuit is inserted into the other emitter circuit. The voltage reduction circuit is
A resistor and a smoothing capacitor are connected between the DC power supply and the push-pull output stage.

Further, the base bias source of the push-pull output stage transistor is obtained from a DC power source and from a voltage point reduced by a source voltage circuit.

(Operation) According to the above configuration, by inserting the voltage reduction circuit of the above configuration into the power supply line, when the power supply current increases as in the case of a signal with poor S / N or a signal with many high frequency components, By reducing the voltage supplied to the output stage transistor and reducing the voltage between the collector and the emitter of the output stage transistor, power loss can be reduced.

In addition, by obtaining the base bias source of the output stage transistor from the DC power supply and from the voltage point reduced by the voltage reduction circuit, the setting of the base bias using the voltage reduction effect of the voltage reduction circuit is achieved. Done, S / N
In the case of a poor signal or a signal having many high-frequency components, the voltage between the base and the emitter of the output stage transistor is reversed in the same manner as described in the conventional example, and the base clip can be applied by the output stage transistor.

(Example) An example will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a scanning speed modulation circuit according to one embodiment of the present invention. In this figure, the same reference numerals as in the conventional example shown in FIG. 5 indicate the same functions.

In FIG. 1, a video signal input terminal 25 is connected to a resistor 27 and a differentiating circuit of a coil 28 via a coupling capacitor 26, and an output terminal thereof is connected to a base of a voltage amplifying transistor 32 via an engaging capacitor 29. ing. Transistor
The base of 32 is supplied with a base bias voltage obtained by voltage dividing resistors 30 and 31 connected to a power supply terminal 36, and the emitter of the transistor 32 is referenced via a parallel circuit of an emitter resistor 33 and a high-frequency compensation capacitor 34. The collector of the transistor 32 is connected to the power supply terminal 36 via the collector resistor 35. The collector output of the voltage amplifying transistor 32 is supplied to the bases of the complementary grounded collector transistors 37 and 38. An emitter current limiting resistor 39 is connected between the emitters of the transistors 37 and 38, and the emitter of the transistor 37 is connected to the base of the output stage transistor 50 via a damping resistor 40 and a coupling capacitor 42. The emitter of the transistor 38 is connected to the base of the output transistor 51 via the damping resistor 41 and the coupling capacitor 43. The output stage transistor 50 is constituted by a PNP transistor, the output stage transistor 51 is constituted by an NPN transistor, and both transistors constitute a push-pull output circuit. The above configuration is the same as the conventional example shown in FIG.

FIG. 1 differs from the conventional example shown in FIG. 5 in the emitter circuit portions of the output stage transistors 50 and 51 and the base bias circuit portion.

In FIG. 1, the collectors of the output stage transistors 50 and 51 are commonly connected, the emitter of the output stage transistor 51 is connected via a resistor 55 to the emitter of a constant voltage source transistor 60, and the collector of the transistor 60 has a reference potential. The smoothing capacitor 61 is connected to the point, and the emitter is connected to the point. A constant voltage obtained by voltage dividing resistors 62 and 63 provided between the power supply terminal 44 and the reference potential point is supplied to the base of the constant voltage source transistor 60, and a constant voltage is obtained to the emitter of the transistor 60.

On the other hand, the emitter of the output stage transistor 50 is connected via a resistor 52 to a voltage reduction circuit composed of a resistor 64 and a smoothing capacitor 65. The voltage reduction circuit is provided between the power supply terminal 44 of the DC voltage + B2 and the resistor 52, and is configured by, for example, connecting the resistor 64 and the smoothing capacitor 65 in series between the power supply terminal 44 and the reference potential point. That is, the emitter of the output stage transistor 50 is connected via the resistor 52 to the connection point between the voltage reducing resistor 64 and the smoothing capacitor 65. In addition, resistors 45, 46, 47, 48, 49, 66 are connected to respective bases of both output stage transistors 50, 51.
As a result, a bias voltage is supplied from both the power supply terminal 44 and the voltage reduction circuits (64, 65). That is, the voltage dividing resistors 45, 46, 47, and 48 are connected in series between the connection point of the resistor 64 and the smoothing capacitor 65 constituting the voltage reduction circuit and the reference potential point, and the resistor 45 is connected.
And 46 are connected to the base of the output transistor 50, the resistors 46 and 47 are connected to the common collector of the output transistors 50 and 51 via the resistor 49, and the 48 Connected to the base of output stage transistor 51.
In addition, the power supply terminal 44 is connected to the base of the output stage transistor 50 via the voltage dividing resistor 66.

The operation of the output amplification stage of the scanning speed modulation circuit configured as described above will be briefly described below.

First, the voltage reduction circuit including the resistor 64 and the smoothing capacitor 65 operates to change the voltage across the smoothing capacitor 65 in accordance with the current consumption of the output stage transistors 50 and 51. FIG. 2A shows a change in voltage across the smoothing capacitor 65. In FIG. 2, the vertical axis represents the voltage value, and the horizontal axis represents the current consumption value. As shown in FIG. 2 (1), the voltage across the smoothing capacitor 65, that is, the emitter voltage and the collector voltage supplied to the output stage transistors 50 and 51 decrease as the current consumption increases.
The power consumption of the output stage transistors 50 and 51, which is the product of the voltage supplied to the power supply and the current consumption, is smaller than that without the voltage reduction circuit (64, 65).

Here, when the voltage reduction circuit in FIG. 1 is compared with the circuit of the conventional example (FIG. 5), the DC voltage +
The parallel circuit of the resistor 53 and the capacitor 54 and the resistor 52 are connected in series between the terminal 44 of B2 and the output transistor 50. However, in FIG. 1 of the present invention, the terminal 44 of the DC voltage + B2 is connected.
A voltage dividing circuit (bleeder circuit) is provided between the resistor 64 and the capacitor 65 at a time between the reference potential point and the output stage transistor 50 via the resistor 52 at the connection point between the resistor 64 and the capacitor 65.
Connected to the emitter. Accordingly, the voltage between both ends of the smoothing capacitor 65 for voltage reduction, that is, the voltage supplied to the output stage transistors 50 and 51 can be changed relatively easily by selecting the resistance value of the resistor 64, and is supplied to the output stage transistors 50 and 51. Voltage can be set lower. Since the base bias voltages of the output stage transistors 50 and 51 are supplied from the voltage reduction circuit via the voltage dividing resistor 45, the power supply voltage is relatively lowered as compared with FIG. The voltage between the emitter and collector of the output stage transistors 50 and 51 can be reduced accordingly. In contrast, in the conventional example (FIG. 5), the resistance 53
As described above, the parallel circuit of the smoothing capacitor 54 and the resistor 52 operate to reverse-bias the emitter voltage with respect to the base voltage of the transistor 50, that is, merely obtain a clipping function. The same applies to the voltage supplied to the collector of the transistor 51.

On the other hand, according to the present invention (FIG. 1), according to the maximum allowable power of the output stage transistors 50 and 51, the resistance 64
Can be set, so that the heat radiation design of the output stage transistors 50 and 51 is easy.

On the other hand, the changes in the base-emitter voltages of the output stage transistors 50 and 51 are shown in FIGS. 2 (2), (3), (4),
It becomes like (5). FIG. 2 (2) shows the emitter voltage of the output stage transistor 50, which is lower by the voltage drop of the resistor 52 than the voltage across the smoothing capacitor 65 shown in FIG. 2 (1). FIG. 2 (3) shows the emitter voltage of the output stage transistor 51, which is kept constant by the constant voltage source transistor 60 as described above.

FIG. 2 (4) shows the base voltage of the output stage transistor 50. The base voltage is the resistance 45, 46, 4
It is obtained by the voltage divider circuit of 7,48,49,66. If the resistor 66 is not provided, the voltage across the smoothing capacitor 65 is roughly divided by the resistance ratio, that is, the voltage in FIG. 2A is multiplied by a certain constant (1 or less). Terminal 44
Therefore, the base voltage of the output stage transistor 50 has a slower source voltage with respect to the consumption current than the voltage across the smoothing capacitor 65 shown in FIG. 2A.

Accordingly, when the base voltage of the output stage transistor 50 is compared with the emitter voltage of the output stage transistor 50 shown in FIG. 2B, the amount of decrease in the base voltage is slower with respect to the increase in current consumption. When the current consumption reaches a predetermined value, the inversion of the base potential and the emitter potential (shaded portion in the figure) occurs. In other words, when the current consumption exceeds a certain value,
The base region of 50 will be above the emitter potential. This is a condition for obtaining the base clip effect described in the conventional example, that is, the class C operating state.

FIG. 2 (5) shows the base voltage of the output stage transistor 51. This base voltage is substantially equal to the base voltage of the output stage transistor 50 shown in FIG.
, And has characteristics similar to the characteristics shown in FIG. 2 (4). Also in this case, when the base voltage of the output stage transistor 51 is compared with the emitter voltage of the output stage transistor 51 shown in FIG. 2 (3), the inversion of the base potential and the emitter potential at the time when the current consumption reaches a predetermined value (the hatched portion in the drawing) Part). In other words, when the current consumption exceeds a certain value,
The base potential of 51 will be lower than the emitter potential.

In a scanning speed modulation circuit having the above characteristics, S /
In the case of a signal having a bad N or a signal having many high-frequency components, the current between the emitter and the collector and the current between the collector and the emitter of the output stage transistors 50 and 51, that is, the current consumption increases, but the voltage reduction circuit (64, The power consumption can be suppressed by suppressing the current consumption of the output stage transistors 50 and 51 by the voltage reduction effect according to 65). At the same time, by setting the base potential and the emitter potential using the voltage reduction effect as described above, when a signal having a poor S / N or a signal having many high-frequency components is used, the description of the conventional example is omitted. Similarly, the voltages between the bases and the emitters of the output stage transistors 50 and 51 are reversed, and a class C operation state is set. In other words, this means
A base clip will be applied at the output increase stage. For normal signals, class B operation is performed, and when the signal has a poor S / N or a signal with many high-frequency components (in this case, the correction current increases and the consumption current increases. Can cause class C operation, thereby suppressing an increase in power supply current, removing correction current due to a noise signal, or suppressing overcorrection of a fine image having many high-frequency components.

[Effects of the Invention] As described above, according to the present invention, when a signal with poor S / N or a signal with many high-frequency components is present, the base-emitter voltage of the output-stage transistor is increased in the reverse bias direction as in the conventional example. By controlling and performing base clipping, it is possible to suppress an increase in power supply current, to remove correction current due to noise signals, or to suppress overcorrection for fine images with many high-frequency components. The voltage between the emitters can also be reduced, and the power loss of the output stage transistor can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a scanning speed modulation circuit according to one embodiment of the present invention, FIG. 2 is an explanatory diagram showing a voltage change of each part with respect to a consumption current in an output amplifier of the circuit of FIG. 1, and FIG. Waveform diagram for explaining the principle of contour compensation by velocity modulation,
FIG. 4 is a block diagram showing a conventional television receiver provided with a scanning speed modulation circuit, and FIG. 5 is a circuit diagram showing a conventional scanning speed modulation circuit. 25: Video signal input terminal, 27: Differential resistor, 28: Differential coil, 32: Amplifying transistor, 37, 38: Transistor, 44: Power supply terminal, 45, 46, 47, 48, 49,66… Division resistor for base bias, 50,51… Output stage transistor, 52,55… Emitter resistance, 58… Auxiliary deflection coil for speed modulation, 59… Coupling capacitor for auxiliary deflection coil, 60 …………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………….

Claims (1)

(57) [Claims] 1. A differentiating circuit for differentiating an input video signal to obtain a scanning speed modulation signal; an amplifying means for amplifying a scanning speed modulation signal from the differentiating circuit; A voltage reduction circuit for reducing the voltage with a resistor and a smoothing capacitor, and the collectors of the PNP transistor and the NPN transistor are connected in common, and the emitter of the PNP transistor is connected to the second.
And the emitter of the NPN transistor is connected to a reference potential point via a third resistor and a constant voltage circuit, and the PNP type A push-pull output circuit for inputting a scanning speed modulation signal from the amplifying means to a transistor and the base of the NPN transistor and extracting an output to a speed modulation auxiliary deflection coil connected to a common collector; the PNP transistor and the NPN A bias circuit for supplying a bias voltage from the DC power supply and from a connection point between the first resistor and the second resistor via a resistor, respectively, at a base of the transistor. Scanning speed modulation circuit.