JP2848390B2 - Output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video output circuit for a television or a display, and more particularly to a peak clamp circuit having a stable clamp level.

[0002]

2. Description of the Related Art Emitter peaking is frequently used in conventional wideband amplifier circuits. For example, FIG.
In the amplifier circuit described in Japanese Patent Application Laid-Open No. 0-26899, the current Iin of the input signal source 10 is amplified and output from the terminals 59 and 501. However, the emitters of the transistors 3 and 38 or the transistors 4 and 48 of the differential amplifier circuit are used. A capacitor 35 or 45 is added between them for emitter peaking.

In the case of emitter peaking, the degree of amplification in the high frequency band is increased relative to that in the low frequency band by utilizing the fact that the impedance between the emitter and the AC ground decreases as the signal frequency increases. However, in the circuit of FIG.
For the purpose of doubling the amplifiable frequency, the connection of two sets of differential amplifier circuits including the transistors 3, 38, 4 and 48 is devised. In other words, the outputs of the differential amplifier circuit are connected in parallel in phase to double the output,
The inputs are connected in series and the input impedance is also doubled.

FIG. 9 shows a clamp circuit suitable for a large-output wideband video circuit disclosed in Japanese Patent Application Laid-Open No. 61-220566. In FIG. 9, the signal of the video signal source 1 is amplified by the transistor 3 and applied to the CRT 9. FIG. 9 shows a synchronous clamp circuit in which the timing for clamping the cathode terminal 91 of the CRT 9 to a voltage substantially equal to the voltage of the clamp variable voltage source 73 is controlled by the clamp pulse signal source 75. The resistor 81 is a protection resistor that suppresses an abnormal increase in luminance of the CRT 9 when the power is turned on. Since the discharge current 76 flowing through the clamp capacitor 8 during the clamp does not flow through the resistor 53 but becomes a closed circuit current via the emitter and the collector of the clamp transistor 7,
In addition to stabilizing the clamp level, power consumption can be reduced by increasing the resistance value of the resistor 53.

FIG. 10 shows an example in which the synchronous clamp circuit of FIG. 9 is improved to a peak clamp circuit that automatically clamps at the time of a signal peak. In FIG. 10, the variable resistor 79 and the capacitor 78 connected between the voltage sources 52 and 82 to reduce power consumption realize the variable voltage source 73 for clamping shown in FIG. Therefore, the clamp diode 77 and the clamp transistor 7 conduct only at the peak of the signal, and the clamp operation is performed. FIG. 10 shows a configuration close to a practical circuit, including a protection diode 72 for the clamp transistor 7 and a capacitor 83 for compensating for an increase in the impedance of the capacitor 8 at high frequencies.

Next, a blanking circuit which can be operated at a high speed is shown by the configuration of transistors 5 and 6 in FIG. FIG.
, The transistor 5 is used as a cascode-connected grounded base circuit for amplifying a video signal. The transistor 6 having the transistor 5 and the emitter connected to each other performs a blanking operation by shutting off the transistor 5 when a blanking pulse input to its base is at the HI level. At this time, since the transistors 5 and 6 can be a non-saturated differential pair, switching at the time of blanking can be performed at an extremely high speed. Further, since the transconductance of the differential pair is high, the amplitude of the blanking pulse can be suppressed to a small value (at least about 0.2 Vpp at room temperature), thereby improving the speed.

[0007]

In the conventional emitter peaking typified by the circuit shown in FIG. 2, as the signal amplitude increases and the bias current of the transistor decreases, the expansion range of the frequency band narrows. There's a problem. This will be described with reference to FIG. 3 showing the configuration of the differential amplifier circuit in FIG. For example, when a rising pulse is applied to the base of the transistor 3 from the signal source 14, a signal current 302 proportional to the pulse amplitude flows through the peaking capacitor 35. This signal current 30
2 shunts to currents 303 and 304 (but current 3
04 is often negligible in view of the impedance ratio). At this time, if the current 303 becomes larger than the bias current flowing through the transistor 38 before the rise of the pulse, the transistor 38 is cut off, and the linearity of the circuit is impaired.

The above phenomenon is caused by inputting a falling pulse to a general emitter-grounded common circuit which is subjected to emitter peaking, which is represented by only the configuration of the transistor 3 and the resistors 32 and 33 and the capacitor 31 in the conventional example of FIG. In this case, the transistor 3 is similarly turned off.

A first object of the present invention is to alleviate the restriction on the broadening of the output power of the emitter peaking.

Next, in the case of the conventional clamp circuit shown in FIG. 10, there is a problem in the stability of the clamp level. In the same figure, when the video signal level is particularly small during the non-clamp period, the diodes 72 and 77 do not conduct, so that
The impedance of the base line of the transistor 7 increases. When a hand or a metal such as a chassis is brought close to the base line of the transistor 7 for adjustment, or when dust is accumulated on a printed circuit board, the stray capacitance 703 and the resistor 704 shown in FIG. This is equivalent to the connection of the external noise source 706, and the transistor 7 conducts under the influence of induction or leakage current. In that case, the capacitor 8
Discharge causes the CRT 9 to illuminate, as if the clamp level fluctuated.

When the protection resistor 81 is connected as shown in FIG. 10 for the purpose of reducing the impedance of the base line of the transistor 7, the current 701 flowing at the time of clamping increases, and the video signal and the clamping period (peak period) increase. The clamp level fluctuates due to the change of the clamp circuit (corresponding to the blanking period).

A second object of the present invention is to eliminate the instability of the clamp level due to the high impedance of the base line of the clamp transistor.

Next, in the case of a blanking circuit as shown in FIG. 4, a high-frequency power transistor is often used as the transistor 5, and its emitter input capacitance is extremely large (for example, about 0.22 μF). Therefore, when the video signal and the brightness adjustment level decrease and the current flowing through the transistor 5 during non-blanking decreases, 5
May take longer to recover from the cut-off state to the active state. (For example, about 100 nsec or more). This recovery time is a delay time when blanking is turned off, and often hinders realization of a short blanking period (for example, about 4 μsec) in a signal of a high-definition display or the like.

A third object of the present invention is to reduce the delay time when the blanking is turned off.

[0015]

In order to achieve the first object, a phase-inverted signal voltage source is connected to an input terminal of a base (gate) ground circuit via a desired impedance circuit. The output terminal of the base (gate) ground circuit is connected to the output terminal of the amplifier.

In order to achieve the second object, the clamp capacitor and the emitter of the clamp transistor are connected via a diode, and the base of the clamp transistor is connected to a clamp voltage source.

In order to achieve the third object, another current path is provided at the emitter of the transistor which is cut off during blanking. Alternatively, the third object can be achieved by connecting, via a resistor, the emitter of a common-base transistor whose current is limited during blanking and the emitter of a transistor to which a blanking pulse is input to the base. You.

In the means for achieving the first object, the impedance connected to the phase-inverted signal voltage source has a function of converting the phase-inverted signal voltage into a peaked signal current. Further, the base (gate) ground circuit connected to the impedance has an action of adding the signal current obtained from the phase-inverted signal voltage in the same phase as the conventional signal current obtained from the non-inverted signal voltage. Therefore, when only the conventional peaking is used, the signal current that tends to be distorted can be linearized by using the signal current obtained from the phase-inverted signal voltage together, and the above-described large output and wide band can be realized.

In the means for achieving the second object, the diode connected between the clamp capacitor and the emitter of the clamp transistor has a function of a clamp switch that conducts only at the peak of a signal. Accordingly, since the base line of the clamp transistor is always connected to the clamp voltage source to reduce the impedance, the instability of the clamp level is eliminated.

In the means for achieving the third object, another current path provided at the emitter of the transistor which is cut off at the time of blanking restricts the minimum value of the current flowing through this transistor at the time of blanking OFF. Has an action. Further, the resistance connected between the emitter of the transistor whose current is limited at the time of blanking and the emitter of the transistor to which the blanking pulse is input to the base is determined by the current value of the transistor whose current is limited at the time of blanking. Has an action to set. Therefore, it is possible to suppress an increase in the recovery time of the transistor which is cut off at the time of blanking or is subjected to the current limitation to the state at the time of blanking OFF, and the delay time at the time of blanking OFF can be reduced. it can.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. In FIG. 1, the signal voltage of the signal source 1 is
The signal is amplified by a differential amplifier circuit including a differential output amplifier circuit 2 and transistors 3 and 4 and a grounded base circuit of a transistor 5 and applied to a CRT 9 via a clamp capacitor 8. 1 show an example of the peaking impedance circuit of the present invention, and the coils 54 and 55 and the resistor 56 constitute a conventionally used series peaking circuit. In addition, transistor 6
A blanking pulse is input to the base from the signal source 61 to control the current of the transistor 5;
Therefore, the minimum current of the transistor 5 is limited by the newly provided current path. Furthermore, the diode 7
Since the base of the transistor 7 connected to the capacitor 8 via 1 is always connected to the variable voltage source 73 for clamping, a stable clamp level is secured for the signal appearing at the cathode terminal 91 of the CRT.

Here, an embodiment of peaking according to the present invention will be described first. Transistors 3 and 4 of FIG.
It is not necessary to add a peaking capacitor in parallel to the resistor 34 connecting the emitters. Therefore, the peaking intensity set by the peaking impedance circuits 30 and 40 can be enhanced within a range up to a level at which only the transistors 3 and 4 are not cut off. This is because most of the signal current peaked by the impedance 30 flows through the transistor 3 and hardly flows through the transistor 4, and similarly, the impedance 40 acts only on the transistor 4 and affects the transistor 3. Because it is small. In the present invention, since the signal currents flowing through the impedances 30 and 40 are added at the output of the amplifier circuit,
The product of the frequency band and the maximum output amplitude at the upper limit can be enhanced to about twice the level of the conventional circuit. At this time, even if slight distortion occurs in both signal currents, they are added complementarily at alternate timings. Even harmonics are suppressed. Although the impedances 30 and 40 in FIG. 1 are of a bilinear type with a resistor and a capacitor configuration, they may have a general passive element configuration including a coil (accordingly, a direct current may flow). The effect of the present invention is lost regardless of the configuration including active elements such as transistors and the like, and the configuration of two or more terminals in which the inflow and outflow currents do not match (however, the two currents need to be dependent). Absent. Further, in FIG. 1, the differential output of the amplifier circuit 2 is amplified by a differential amplifier circuit composed of transistors 3 and 4 (if the polarity is the same, a "PNP transistor" or another active element may be used). But
It is also possible to adopt an amplification type using two independent amplifier circuits without using the resistor 34. In that case, transistor 3
And 4 may have different polarities. From this,
The resistor 34 of FIG. 1 has the above impedance and a value of 3 unless it allows the signal current emphasized for peaking to pass through.
Similarly to 0 and 40 (however, dependency on inflow / outflow current is not required), a general impedance circuit may be used.

Next, FIG. 5 shows a configuration example of a peaking circuit which forms a video output circuit in combination with the circuit of the present invention. In FIG. 5, the signal voltage of the signal source 1 is inverted (amplified) by the transistor 3 without using the differential output amplifier circuit.
By directly inputting the signal to the circuit 20, the circuit scale can be reduced. The inverting (amplifying) circuit 20 in FIG. 5 uses a common emitter circuit including a PNP transistor 22.
It may be a common emitter circuit of an NPN transistor. As a peaking method, the emitter resistance 2
Many conventional systems in which a capacitor is connected in parallel to the capacitor 4 or a coil is inserted in series in the collector resistor 23 can be applied.
The base (input) resistors 11 and 21 are used for stabilizing the circuit, and can be used for all active elements (not shown).

Next, another configuration example of the peaking circuit which forms a video output circuit in combination with the circuit of the present invention is shown in FIG. FIG. 6 shows an example in which power consumption is reduced when any one of the differential outputs of the amplifier circuit 2 is used only for peaking. Buffer circuit 401 in FIG.
Are AC-coupled by a coupling capacitor 403, and the power consumed by the transistor 4 and the resistor 43 can be reduced by lowering the voltage of the bias voltage source 402 while securing the signal dynamic range. Also,
It is needless to mention that the buffer circuit 401 itself becomes unnecessary when the amplifier circuit 2 has a sufficient current supply capability, but even in that case, any one of the two differential outputs is used as described above. By using one of the outputs only for peaking, the power consumption inside the amplifier circuit 2 can be reduced. Further, in FIG. 6, only the transistor 3 is used for DC amplification, but the power consumption can also be reduced by using the buffer 401 for DC amplification and using the transistor 3 only for peaking.

Next, FIG. 7 shows an example of the configuration of a peaking circuit when a video output circuit for three channels is formed in combination with the circuit of the present invention. FIG. 7 shows a video output circuit for three channels (R: red, G: green, B: blue) having the same configuration, with only the R channel shown in detail. FIG.
, A 1-channel video output circuit is connected to two sets of differential amplifier circuits (for example, a transistor 3
And a circuit composed of two sets of 4, 305 and 409), the following effects are obtained.

1. Since a low-power and wide-band element can be used for the transistors (3, 4, 305, and 409) constituting the differential amplifier circuit, the video output circuit can have a wider band and lower cost.

2. In FIG. 7, there are two sets, but the output of the video output circuit can be increased by using the outputs of a plurality of sets of differential circuits per channel in parallel.

3. By appropriately setting the respective peaking frequencies (frequency characteristics) of a plurality of sets of differential circuits used for one channel, the overall frequency band of the video output circuit can be further expanded. Alternatively, various frequency characteristics can be realized by the video output circuit.

FIG. 7 shows the peaking capacitors 406, 412, etc., which have caused the problem in the conventional example, but these peaking are caused by smearing, streaking, etc. The correction is performed at an extremely weak level for the correction of the low-frequency characteristic (which may be remarkable due to a decrease in heat capacity due to miniaturization), and does not cause a problem. If the level is weak, it goes without saying that conventional peaking can be used together.

Next, FIG. 8 shows another example of the configuration of the peaking circuit that can further increase the peaking. In FIG. 8, peaking can be enhanced by the following factors.

1. PN connected to the common base transistor 514
Since the P-type is used to provide a push-pull output type (configured by transistors 3 and 514), it is possible to avoid the interruption of the above-described transistor and further increase the peaking signal current as long as the power condition due to the increase in the bias current allows.

2. Since the common base transistor 514 is used only for the inverted signal current, interference due to the non-inverted signal current (flowing through the transistor 3) is eliminated, and peaking can be enhanced to the maximum. (When the common base transistor is used, the input resistance of the common base transistor is effectively increased due to the effect of the non-inverted signal current.) However, an NPN is provided between the collector of the transistor 3 and the collector of the transistor 514 in FIG. It goes without saying that a cascade connection can be made by inserting a grounded base circuit of the transistor.

FIG. 11 shows an embodiment in which the instability of the clamp level is eliminated. In FIG. 11, a diode 707 connected between the emitter of the clamp transistor 7 and the clamp capacitor 8 performs a function of a clamp switch for performing a clamp operation only at the peak of a signal. Therefore, it is possible to always connect the base of the clamp transistor 7 to a variable voltage source for clamping (consisting of a capacitor 78 and a variable resistor 79). Therefore, the impedance of the base line of the clamp transistor 7 can be reduced, so that the instability of the clamp level is eliminated.

Next, FIG. 12 shows an embodiment of a clamp circuit suitable for a wideband video circuit by reducing the parasitic capacitance on the signal line. In the circuit shown in FIG. 11, the capacitance between the base and the collector of the transistor 7 and the diode 70 for the clamp switch are provided as parasitic capacitance on a signal line provided via the clamp capacitor 8.
7, the junction capacitance and the inter-terminal capacitance act. The above-described parasitic capacitance on the signal line directly acts as a constraint on the frequency band of the video circuit, and consequently increases the power consumption of the circuit. In FIG. 12, separating impedance circuits 709 and 711 are inserted between the signal line and the clamp circuit in order to reduce the above parasitic capacitance. When the resistors 710 and 712 are used for the separation impedance circuits 709 and 711, their resistance values are set sufficiently higher than the impedance in the high frequency range of the signal frequency of each of the parasitic capacitances connected in series. , Respectively, so that the clamp transistor 7 does not saturate and the clamp level does not fluctuate. The separation impedance circuits 709 and 711 can be used for various applications as a part of a transmission circuit by using a configuration including a general passive circuit such as a coil as long as the above impedance condition is satisfied. It is possible. Further, in order to reduce the parasitic capacitance, the collector of the transistor 7 in FIG. 1 can be connected to the emitter of the transistor 5 or 3.

Finally, an embodiment of a blanking circuit in which the above-described delay time when blanking is turned off is reduced is shown in FIG.
Shown in In FIG. 13, a blanking pulse signal source 6
The blanking pulse input from 1 is amplified and waveform-processed by transistors 602, 604, and 611, and then video output circuits 68 and 615 of each channel (R, G, B) including the blanking transistor 6 and the like. 6
13 is input. A specific method for reducing the delay time when the blanking is turned off using the circuit shown in FIG. 13 will be described below. Note that in the present invention, the terminal 62 can be used as an output terminal or the like without being connected to a voltage source if the voltage range is such that the transistor 6 is not saturated.

1. The resistance 63 is used (however, the resistance 61
6, 617 are 0Ω). The resistor 63 limits the minimum value of the current flowing when the blanking is OFF to the transistor 5 that is cut off during the blanking. If this condition is satisfied,
The resistor 63 can be replaced with a general impedance circuit. The minimum value of this current is determined by the blanking OF of transistor 5.
The delay time when the blanking is turned off can be reduced by ensuring that the recovery time to the state at the time of F does not increase.

2. Instead of the resistor 63, a circuit serving as a current path such as a constant current circuit is connected to the emitter of the transistor 5 (the resistors 616 and 617 are 0Ω). The above 1.
By the same principle as described above, the delay time when the blanking is turned off can be reduced. However, various applications such as removal of the temperature drift of the limiting current described above are possible.

3. The resistor 617 is used (however, the resistor 63
Is open to the high resistance region, and 616 is 0Ω). During blanking, the emitter potential of the blanking transistor 6 can be set to a certain value, and the emitter potential of the transistor 5 is also fixed to a certain value. Therefore, the resistance 61
By appropriately setting the resistance value of 7, the current flowing through the transistor 5 during the blang can be set.
If the current setting at the time of blanking is possible,
17 can be replaced with a general impedance circuit. By securing this current value to a value that does not increase the recovery time of the transistor 5 to the state when the blanking is turned off, the delay time when the blanking is turned off can be reduced. Also, by reducing the collector loss of the transistor 3,
3, a small-sized broadband element can be used.

4. The resistor 616 is used (however, the resistor 63
Is open, 617 is 0Ω). 3 above. By the same principle as described above, the delay time when the blanking is turned off can be reduced. However, when the resistor 617 is used, the mirror effect due to the effect of the signal voltage generated at the collector of the transistor 3 can be removed, and the circuit can have a wider band. In addition, 4. Similarly, the resistor 616 can be replaced with a general impedance circuit.

5. A combination of a plurality of the above methods 1 to 4.

Here, the process of blanking pulse amplification and waveform processing shown in FIG. 13 will be described. Transistor 6
The differential circuit composed of 02 and 604 is an extremely high-speed switching circuit because it amplifies if the input blanking pulse has an amplitude of 0.2 Vpp or more and can avoid the saturation of the transistor. The resistor 610 has a function of limiting the upper limit potential of the amplified blanking pulse to suppress a reverse voltage applied to the base-emitter junction of the transistor 5 during blanking within a breakdown voltage. The transistor 611 performs impedance conversion when distributing the above-described voltage-amplified and waveform-processed blanking pulse to each channel. In this case, immediately after the rising of the blanking pulse, a reverse base current may flow from the base of the transistor 611 to increase the upper limit potential of the blanking pulse. A capacitor 609 is added to absorb the reverse base current.

In all the embodiments except for the clamp circuit described above, it goes without saying that the polarities of the power supply and the active element can be inverted. Regarding the embodiment of the clamp circuit,
The polarity reversal described above is possible except when connected to the cathode or grid of a CRT. Further, it goes without saying that all the transistors in the embodiments of the present invention can be replaced with general active elements such as FETs, compound semiconductors, and electron tubes.

[0043]

As described above, the following effects can be obtained by using the present invention.

(1) The limit condition regarding the amplitude and frequency band of the peaking circuit can be expanded to about twice or more than that of the conventional circuit, and a large output and wide band of the amplifier circuit can be realized.

(2) A stable peak-clamp circuit whose clamp level does not fluctuate even by electrostatic induction or leakage current can be obtained.

(3) Since a high-speed blanking circuit with a particularly short delay time (for example, about 350 nsec) when blanking is turned off is obtained, a signal having a short blanking period (for example, about 4 μsec) for an ultra-high-definition display or the like is obtained. Can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing a conventional example.

FIG. 3 is a diagram showing a conventional example.

FIG. 4 is a diagram showing a conventional example.

FIG. 5 is a diagram illustrating a configuration example of a peaking circuit that forms a video output circuit in combination with the output circuit of the present invention.

FIG. 6 is a diagram illustrating a configuration example of a peaking circuit that forms a video output circuit in combination with the output circuit of the present invention.

FIG. 7 is a diagram illustrating a configuration example of a peaking circuit that forms a video output circuit in combination with the output circuit of the present invention.

FIG. 8 is a diagram illustrating a configuration example of a peaking circuit that forms a video output circuit in combination with the output circuit of the present invention.

FIG. 9 is a diagram showing a conventional example.

FIG. 10 is a diagram showing a conventional example.

FIG. 11 is a diagram showing an embodiment of the present invention.

FIG. 12 is a diagram showing an embodiment of the present invention.

FIG. 13 is a diagram illustrating a configuration example of a video output circuit configured using the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Input signal source, 2 ... Amplifier circuit which has a differential output, 5, 514 ... Common-base transistor, 9 ... CRT, 30, 40, 709, 711 ... Impedance circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Koji Kito, Inventor 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (56) References JP-A-61-220566 (JP, A) (58) Surveyed fields (Int.Cl. ⁶ , DB name) H04N 5/14-5/217

Claims (1)

(57) [Claims] An output side of a signal amplifying circuit (3) includes a clamping transistor (7), a clamping capacitor (8), a unidirectional conducting element (707), and a collector of the transistor (7). A structure in which a base is connected to a signal amplification circuit, a base is connected to a voltage source for clamping, and the one-way conductive element is connected between the capacitor and an emitter of the transistor, and an output signal of the signal amplification circuit is peak-clamped. An output circuit, characterized in that: