JP2917925B2 - Method of manufacturing thin film transistor and active matrix array for liquid crystal display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LDD (Lightly Dop
The present invention relates to a thin film transistor (hereinafter abbreviated as TFT) having an ed drain) structure and a method for manufacturing the same, and is a technique usable for an active matrix array for a liquid crystal display device.

[0002]

2. Description of the Related Art Heretofore, an LDD structure has been known as a technique for reducing a leak current of a TFT.

FIG. 5 is a cross-sectional view showing a manufacturing process of a conventional LDD-structured thin film transistor, and the manufacturing process will be described.

[0004] As shown in FIG.
An amorphous silicon thin film is formed on a (high heat resistant glass substrate) by a low pressure vapor phase epitaxy method (LPCVD method), and is heat-treated at 600 ° C. in a nitrogen atmosphere to crystallize the amorphous silicon thin film. To form The polycrystalline silicon thin film is processed into an island shape to form a silicon oxide thin film serving as a gate insulating film 14a. A gate electrode 15 is formed on the silicon oxide thin film. After the formation of the gate electrode, a first impurity implantation is performed by ion implantation using the gate electrode as a mask to form a low-concentration impurity implantation region (n ^- region) 13b. In the first impurity implantation, phosphorus (P) ions were implanted at an acceleration voltage of 80 KV and a dose of 1 × 10 ¹³ / cm ² . First after impurity implantation, after forming a mask of ^n-regions in the photoresist 25 as shown in FIG. 5 (b), the second impurity implantation was carried out high-concentration impurity implanted region (n ⁺ region) 13c
To form In the second impurity implantation, phosphorus (P) ions were implanted at an acceleration voltage of 80 KV and a dose of 1 × 10 ¹⁵ / cm ² .
After the second impurity implantation, the photoresist mask is removed,
Activate the implanted impurities. The activation treatment was performed at 900 ° C. for 2 hours. After the activation process, an interlayer insulating film 16 is formed as shown in FIG. Finally, after opening the contact holes, the source / drain electrodes 20, 2
1 is formed to complete the thin film transistor.

[0005]

SUMMARY OF THE INVENTION A TF having this LDD configuration
In T, in order to apply to an active matrix array used for a liquid crystal display device or the like, a simplification of a manufacturing process and higher performance, especially a further reduction of a leak current are required.

When a thin film transistor is manufactured by using the manufacturing method shown in FIG. 5, two doping steps of a high concentration and a low concentration are required to realize an LDD structure. In comparison, the number of doping steps increases and the manufacturing process becomes complicated.

An object of the present invention is to provide a method for forming high-concentration and low-concentration impurity-implanted regions in a single doping step, and at the same time to provide a method capable of further reducing a leak current.

[0008]

In order to solve this problem, the present invention relates to a thin film transistor using polycrystalline silicon as an active layer, comprising two layers having silicon oxide as a lower layer and tantalum oxide as an upper layer as a gate insulating film. Having a gate insulating film, performing impurity implantation with the tantalum oxide of the gate insulating film covering a low-concentration impurity region (LDD region) formed between the source and drain regions and the channel region of the thin film transistor; This is a method for manufacturing a thin film transistor, comprising a step of removing an tantalum oxide thin film on a low-concentration impurity implantation region after impurity implantation, and then forming an interlayer insulating film.

The present invention also provides an active matrix array for a liquid crystal display device in which peripheral circuits are integrated on the same substrate, wherein a thin film transistor for driving at least a pixel electrode is formed by the method for manufacturing a thin film transistor. An array.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

(Embodiment 1) FIG. 1 is an example of a process sectional view of a thin film transistor having an LDD structure using a manufacturing method of the present invention. First, as shown in FIG. 1, an amorphous silicon thin film is formed with a thickness of 50 nm by a plasma CVD method on a glass substrate 11 coated with silicon oxide. The amorphous silicon is heat-treated at 450 ° C. for 90 minutes in nitrogen to reduce the hydrogen concentration in the film, and then crystallized by excimer laser annealing to form a polycrystalline silicon thin film. The polycrystalline silicon thin film 13 is processed into the shape of a thin film transistor (channel region 13a, LDD region 13b, source / drain region 13c), and 85 nm of silicon oxide as the gate insulating film 14a is formed. A 50 nm tantalum oxide, which is the second gate insulating film 14b, is formed on the silicon oxide. A gate electrode 15 is formed on tantalum oxide. The gate electrode is made of titanium (Ti) 80 nm so as to be in contact with tantalum oxide, and neodymium is added to aluminum (Al) on titanium.
An alloy containing 3.5% of (Nd) is formed to a thickness of 150 nm, and has a total thickness of 230 nm. After forming the gate electrode, the tantalum oxide thin film as the second gate insulating film is
Etching is performed so as to cover the D region and remove the source and drain regions. For the etching of tantalum oxide, a reactive ion etching method using a mixed gas system of CF ₄ and oxygen was used.

After processing the tantalum oxide thin film into the above-described shape, phosphorus is implanted by an ion doping method at an acceleration voltage of 80 KV and an implantation dose of 1 × 10 ¹⁵ / cm ² . In the ion doping method, a gas obtained by mixing hydrogen gas with PH ₃ at a concentration of 5% is plasma-decomposed by high-frequency discharge, and the generated ions are injected into a sample without a mass separation step. Therefore, compared with the conventional ion implantation method, the ion implantation method contains a wider variety of ions and a complex ion of phosphorus and hydrogen, so that the impurity profile at the time of implantation is broader.
By utilizing this feature, in the manufacturing method of the present invention, the LDD region and the source and drain regions are formed by one-time impurity implantation. The implantation conditions are such that the source and the drain region of the thin film transistor are implanted under the optimum condition of low resistance. The optimum condition of the acceleration voltage V (KV) at this time is a range in which the relationship of A−35 ≦ V ≦ A + 10 holds when the thickness of the silicon oxide film serving as the gate insulating film is A (nm). In the case of this embodiment, since A = 85 (nm), 50 ≦ V ≦ 90 (KV)
In the examples, injection was performed at an acceleration voltage of 80 KV. At this time, since the LDD region is implanted through the laminated film of tantalum oxide and silicon oxide, the amount of impurities is reduced depending on the thickness of the tantalum oxide as compared with the source and drain regions, and the thickness of the tantalum oxide is reduced. By optimizing, the source and drain regions and the LDD region of the thin film transistor can be simultaneously formed by one-time impurity implantation. According to our study results, the tantalum oxide film thickness B (nm) can be obtained by assuming that the acceleration voltage at the time of implantation is V (KV) and the silicon oxide film thickness is A (nm).
An optimum value is obtained in a range satisfying the relationship of (AV) +10 <B <(AV) +80.

After the impurities are implanted into the thin film transistor, FIG.
As shown in (b), the tantalum oxide thin film on the LDD region is removed. Thereafter, as shown in FIG. 1C, an interlayer insulating film 16 made of silicon oxide is formed. Silicon oxide is formed at 430 ° C. by using a normal pressure CVD method,
In this step, the activation treatment of the impurity implanted earlier is performed simultaneously. 500 ° C. when the acceleration voltage V (KV) at the time of impurity implantation is in the range of A−35 ≦ V ≦ A + 10 described above.
Activation at the following low temperatures is possible. Finally, Fig. 1 (d)
After opening the contact holes and forming the source and drain electrodes 21 and 22 as shown in (1), hydrogen plasma treatment is performed at 350 ° C. to complete the thin film transistor.

FIG. 2 (c) is a comparison of current-voltage characteristics of an n-channel thin-film transistor manufactured by using the manufacturing method of the present invention, wherein a vertical axis indicates a drain current and a horizontal axis indicates a gate voltage. doing. The size of the thin film transistor is 12 μm in both channel width and channel length, and the LDD region length (ΔL) is 2.5 μm. The long dotted line shows the characteristics of the self-aligned thin film transistor having no LDD structure, and the thin film transistor having a negative gate voltage, that is, a thin film transistor having a large leakage current in a standby state and having such characteristics is used for driving a pixel of a liquid crystal display device. In this case, the voltage holding ability is low, causing crosstalk and image unevenness, which greatly affects display quality.

On the other hand, the characteristics of the thin film transistor (see FIG. 2B) manufactured by using the manufacturing method of the present invention are shown by solid lines. The leakage current of the thin film transistor was significantly improved as compared with the characteristics without the LDD structure. On the other hand, the characteristics of a thin film transistor (see FIG. 2A) having the same LDD structure but formed without removing the tantalum oxide film on the LDD region after the impurity implantation is shown by a dotted line. When the tantalum oxide on the LDD region is not removed after the impurity implantation even though the LDD structure is the same, the effect of reducing the leakage current is small, and the leakage current is significantly reduced by having the tantalum oxide removal step after the impurity implantation. .

(Embodiment 2) FIG. 3 shows an example of a method for manufacturing a thin film transistor array with a built-in drive circuit for a liquid crystal display device using the manufacturing method of the present invention.

First, as shown in FIG. 3, an amorphous silicon thin film is formed to a thickness of 50 nm on a glass substrate surface-coated with silicon oxide by a plasma CVD method. The amorphous silicon is heat-treated at 450 ° C. for 90 minutes in nitrogen to reduce the hydrogen concentration in the film, and then crystallized by excimer laser annealing to form a polycrystalline silicon thin film. The polycrystalline silicon thin film is processed into the shape of a thin film transistor, and silicon oxide, which is the gate insulating film 14a, is formed to a thickness of 85 nm. A 50 nm tantalum oxide, which is the second gate insulating film 14b, is formed on the silicon oxide. Next, a gate electrode 15 is formed on the p-channel thin film transistor. The gate electrode is made of titanium (Ti) 80 so as to be in contact with tantalum oxide.
nm, neodymium (N) on aluminum (Al) on titanium
An alloy containing 3.5% of d) was formed to a thickness of 150 nm, and a total of 2
It has a thickness of 30 nm. At this time, the n-channel thin film transistor is covered with the gate electrode material 15. After that, boron is implanted into the source and drain regions of the p-channel thin film transistor. Boron is formed by an ion doping method at an acceleration voltage of 60 KV and a dose of 5 ×.
The injection was performed at 10 ¹⁵ / cm ² .

After boron ion implantation, as shown in FIG. 3B, a gate electrode is formed on the n-channel thin film transistor, only the LDD region of the pixel TFT is covered with tantalum oxide, and the tantalum oxide on the source and drain regions is removed. Selectively remove. After processing the tantalum oxide thin film into the above shape, phosphorus is implanted by ion doping at an acceleration voltage of 80 KV and an implantation dose of 1 × 10 ¹⁵ / cm ² . In the ion doping method, a gas obtained by mixing hydrogen gas with PH ₃ at a concentration of 5% is plasma-decomposed by high-frequency discharge, and the generated ions are injected into a sample without a mass separation step. Therefore, the impurity profile at the time of implantation is broader than that of the conventional ion implantation method. By utilizing this feature, in the manufacturing method of the present invention, the LDD region and the source and drain regions are formed by one-time impurity implantation.

After injecting impurities into the thin film transistor, FIG.
The tantalum oxide thin film on the LDD region is removed as shown in FIG.

Thereafter, a first interlayer insulating film 16 made of silicon oxide is formed. The silicon oxide is formed at 430 ° C. by using the normal pressure CVD method, and the activation treatment of the impurity previously implanted in this step is simultaneously performed. The acceleration voltage V (KV) at the time of impurity implantation is A-35 ≦ V ≦ A +
When it is in the range of 10, activation at a low temperature of 500 ° C. or less is possible. ITO (Indium-Tin-Ox
ide) A pixel electrode 17 made of a film is formed, and a second interlayer insulating film 18 is formed. After opening the contact holes, source / drain wirings 20 and 21 are formed (FIG. 3D).

The silicon nitride to be the protective film 23 is plasma-CV
After forming at D and annealing at 350 ° C. in a hydrogen atmosphere, the silicon nitride / silicon oxide laminated film on the pixel electrode is selectively removed to complete the active matrix array (FIG. 3E).

FIG. 4 is an example of a sectional view of a configuration of a liquid crystal display device manufactured by using the active matrix array of FIG. 3, in which a pixel portion is enlarged and displayed. Translucent substrate 11
A liquid crystal 47 is held between the active matrix formed above and the opposing substrate 43 via an alignment film 46. The pixel electrode 17 is driven by using the thin film transistor as a switching element to charge the liquid crystal and display an image.

In this embodiment, the case where the pixel driving thin film transistor has the LDD structure has been described. However, the LDD structure may be used for at least a part of the n-channel thin film transistor in the driving circuit portion. effective.

[0024]

According to the manufacturing method of the present invention, it is possible to reduce the number of injection steps required for manufacturing an LDD thin film transistor at least twice or more. Also, by removing the second insulating film on the LDD region after the impurity implantation step as compared with the conventional LDD structure having the two-layer gate insulating film, the leak current can be greatly reduced, and the characteristics are greatly improved. Further, the LDD structure can be realized by a simple manufacturing process, and the process yield and the reliability of the device have been improved.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a thin film transistor manufactured by using a manufacturing method according to one embodiment of the present invention.

FIG. 2 is an explanatory diagram comparing current / voltage characteristics of a thin film transistor manufactured by using the manufacturing method of one embodiment of the present invention with a conventional example.

FIG. 3 is a process sectional view of an active matrix array for a liquid crystal display device manufactured by using the manufacturing method according to one embodiment of the present invention.

FIG. 4 is a cross-sectional view of a liquid crystal display device using an active matrix array according to one embodiment of the present invention.

FIG. 5 is a cross-sectional view of a manufacturing process of a conventional LDD structure.

[Explanation of symbols]

 Reference Signs List 11 glass substrate 13 polycrystalline silicon 13a channel region 13b LDD region 13c source / drain region 14 gate insulating film 14a first gate insulating film (silicon oxide) 14b second gate insulating film (tantalum oxide) 15 gate electrode 16 interlayer insulation Film 17 Pixel electrode 18 Interlayer insulating film 21, 22 Source and drain wiring 23 Protective film (silicon nitride) 41 Black matrix 42 Polarizer 43 Counter substrate 44 Color filter 45 Transparent conductive layer 46 Alignment film 47 Liquid crystal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/786 H01L 21/336 G02F 1/136 500

Claims (5)

(57) [Claims] 1. A thin film transistor using polycrystalline silicon as an active layer, comprising a two-layer gate insulating film having a lower layer of silicon oxide as a gate insulating film and a second insulating film as an upper layer, and a source and a drain of the thin film transistor. Lightly doped region (LDD) formed between the region and the channel region.
Region) is covered with the second insulating film, and the gate is
By implanting impurities using the electrode as a mask,
Source and drain regions and low-concentration impurity regions
The simultaneously formed, after the impurity implantation, the low concentration after removing only the second insulating film on the impurity regions, a method of manufacturing a thin film transistor having at least a step of forming an interlayer insulating film. 2. The thin film transistor according to claim 1, wherein tantalum oxide is used as the second insulating film, the film thickness is 20 nm or more and 100 nm or less, and the silicon oxide film thickness is 50 nm or more and 150 nm or less. Production method. 3. An ion doping method is used for impurity implantation, and the acceleration voltage V (KV) at the time of implantation is set so that the thickness of the silicon oxide film is A.
The method according to claim 1, wherein, when (nm), A-35 ≦ V ≦ A + 10. 4. Tantalum oxide is used as a second insulating film.
There, the second insulating film is a tantalum oxide film thickness B (nm)
However, when the acceleration voltage at the time of ion doping is V (KV) and the silicon oxide film thickness is A (nm), it is characterized by being in the range of (A−V) +10 <B <(A−V) +80. The method for manufacturing a thin film transistor according to claim 1. 5. A liquid crystal display, comprising: a thin film transistor for driving at least picture element electrodes in an active matrix array for a liquid crystal display device in which peripheral circuits are integrated on the same substrate. Active matrix array for display devices.