JP2948553B2 - Semiconductor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit, and more particularly to an improvement of a high-speed and low-power-consumption semiconductor circuit composed of fine elements.

[0002]

2. Description of the Related Art In recent years, with the rapid spread of portable devices and the like, low power consumption of LSIs has been desired. In order to realize a low power consumption type LSI, the internal power supply is being reduced. However, when the internal power supply voltage is reduced, the operation speed of the circuit is rapidly reduced. An effective method for solving this problem is to lower the threshold value (Low-Vt) of the transistor. However, when the threshold value of the transistor is reduced, the current flowing through the transistor increases, and the operation speed can be increased. However, there is a disadvantage in that the off-leak current in standby or active increases. Also,
When a variation occurs in the threshold voltage of a transistor due to a variation in a manufacturing process of the transistor, a new problem appears that the variation width greatly affects a small threshold voltage.

[0003] Regarding the problem of an increase in off-leak current in the standby mode, for example, Japanese Patent Laid-Open No. 6-208790 describes
As disclosed in Japanese Patent Application Laid-Open Publication No. H10-107, there is a technique for reducing the leakage current flowing through the circuit during standby by changing the potential of the source node of the transistor that is cut off during standby in a direction in which the leakage current decreases. is there.

[0004]

However, in the above prior art, the source voltage of the transistor is changed on the assumption that the threshold voltage of the transistor is a constant value. Also, with the temperature change at the time of use of the product, the variation of the threshold voltage of the transistor occurs, and when the threshold voltage increases, the operation speed of the circuit decreases, while when the threshold voltage decreases,
A serious problem occurs in that the off-leak current of the transistor increases.

A first object of the present invention is to provide a semiconductor circuit that suppresses an increase in leakage current and a decrease in operating speed due to variations in threshold voltage of a transistor.

It is a second object of the present invention to provide a semiconductor circuit which can reduce the leakage current of a transistor not only when the circuit is on standby but also when the circuit is active.

[0007]

In order to achieve the first object, according to the present invention, the leak current of a transistor is reduced by the gate-source voltage Vgs of the transistor and the threshold voltage of the transistor. Since the difference voltage Vgs is proportional to the difference voltage Vgs-Vt, the gate-source voltage Vgs is changed according to the change of the threshold voltage Vt, that is,
By changing the source voltage (power supply voltage) of the transistor, the off-state leakage current of the transistor is kept small and constant.

In order to achieve the second object,
According to the present invention, when the circuit is in an active state, a part of the period is forcibly controlled to a low power consumption state.

That is, a semiconductor circuit according to the first aspect of the present invention is a semiconductor circuit that switches between an active state and a standby state, wherein the transistor cuts off in the standby state and a power supply line connected to the transistor. And a power supply control circuit that controls the voltage of the power supply line to change in accordance with a change in the threshold voltage of the transistor.

According to a second aspect of the present invention, in the semiconductor circuit according to the first aspect, the power supply control circuit controls the power supply line according to a change in a threshold voltage of the transistor accompanying a change in a manufacturing process of the transistor. Is controlled so as to change the voltage.

According to a third aspect of the present invention, in the semiconductor circuit according to the first aspect, the power supply control circuit includes a threshold voltage detecting transistor for monitoring a threshold voltage of the transistor.

According to a fourth aspect of the present invention, in the semiconductor circuit according to the first aspect, the power supply control circuit includes a difference between a gate-source voltage Vgs of the transistor and a threshold voltage Vt of the transistor. The voltage of the power supply line is changed so that the voltage Vgs-Vt always becomes a constant value.

According to a fifth aspect of the present invention, in the semiconductor circuit according to the first aspect, the reference voltage level of the power supply line is set to a different voltage value between the active state and the standby state. I do.

According to a sixth aspect of the present invention, there is provided a semiconductor circuit comprising:
And a second power supply line; third and fourth power supply lines; a circuit block connected to the first, second, third and fourth power supply lines; A PMOS transistor and an NMOS transistor connected to one of the third and fourth power supply lines, and a voltage of the third power supply line,
Changing the threshold voltage of the PMOS transistor in accordance with a change in the threshold voltage of the PMOS transistor based on the voltage of the first power supply line;
A power supply control circuit for changing a voltage of the fourth power supply line in accordance with a change in a threshold voltage of the NMOS transistor with reference to a voltage of the second power supply line.

According to a seventh aspect of the present invention, in the semiconductor circuit according to the sixth aspect, the power supply control circuit includes the third power supply control circuit.
The voltage of the power supply line is changed so that the difference voltage between the gate-source voltage of the PMOS transistor and the threshold voltage of the PMOS transistor always becomes a constant value, and the voltage of the fourth power supply line is NMOS transistor gate
It is characterized in that the difference voltage between the source-to-source voltage and the threshold voltage of the NMOS transistor is changed so as to always have a constant value.

According to an eighth aspect of the present invention, in the semiconductor circuit according to the sixth aspect, the reference voltage levels of the third and fourth power supply lines have different voltage values in the active state and the standby state, respectively. It is characterized by being set.

According to a ninth aspect of the present invention, there is provided a semiconductor circuit having a circuit block that switches between an active state and a standby state, wherein the semiconductor circuit consumes less power in the standby state than in the active state. A low power consumption circuit for supplying power; and a pseudo standby in which, when in the active state, a part of the period of the active state is forcibly reduced to a standby state in which the power consumption is reduced by the low power consumption circuit. And a pseudo standby circuit for setting a state.

According to a tenth aspect of the present invention, in the semiconductor circuit according to the ninth aspect, the circuit block includes a transistor cut off in the standby state, and a power supply line connected to the transistor is provided. The power consumption reduction circuit includes a power supply control circuit that controls the voltage of the power supply line to change according to a change in a threshold voltage of the transistor in the standby state.

The invention according to claim 11 is the invention according to claim 10.
2. The semiconductor circuit according to claim 1, wherein said power supply control circuit includes a gate-source voltage Vgs of said transistor in said circuit block and a difference voltage Vg between a threshold voltage Vt of said transistor.
The voltage of the power supply line is changed so that s-Vt always becomes a constant value.

The twelfth aspect of the present invention provides the ninth aspect,
12. The semiconductor circuit according to 10 or 11, wherein the pseudo standby circuit comprises a signal generation circuit for generating a set signal, and the circuit when the circuit block is in an active state and no longer receives the set signal of the signal generation circuit. A set circuit for forcibly setting a block to the pseudo standby state.

According to a thirteenth aspect of the present invention, in the semiconductor circuit according to the ninth aspect, in the pseudo standby state, a signal holding unit that holds a value of a signal output from the circuit block immediately before the pseudo standby state. A circuit is provided.

The invention according to claim 14 is the invention according to claim 13.
5. The semiconductor circuit according to claim 2, wherein the signal holding circuit, when in the active state, generates a latch signal for holding an output signal of the circuit block;
A latch circuit that receives a latch signal of the signal generation circuit and latches an output signal of the circuit block.

According to a fifteenth aspect, the tenth aspect is provided.
In the above described semiconductor circuit, a reference voltage level of the power supply line is set to different voltage values in the active state and the standby state.

According to a sixteenth aspect, in the twelfth aspect,
15. The semiconductor circuit according to claim 14, wherein the signal generation circuit inputs an input signal to the circuit block, and generates a set signal or a latch signal based on the input signal.

According to the above configuration, the present invention is characterized in that:
According to the invention described in the above, the voltage of the power supply line connected to the transistor that is cut off in the standby state changes in accordance with the change in the threshold voltage of the transistor. Even if it fluctuates, the gate-source voltage of the transistor can be maintained at a constant value, so that the off-state leakage current of the transistor in the standby state can be suppressed to a small value.

According to the ninth to sixteenth aspects of the present invention, when the circuit is in the active state, a part of the period of the active state is forced by the pseudo standby circuit to reduce the standby state with low power consumption. Since the pseudo standby state is set equal to the state, the power consumption can be reduced even in the active state.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a semiconductor circuit according to a first embodiment of the present invention.

In the figure, Vcc is a first power supply line having a voltage of, for example, 1.0 V, Vss is a second power supply line which is a ground line, and Vcci
Is a third power supply line, and Vssi is a fourth power supply line. CS is a chip activation signal, and INV1 to INV5 are inverter circuits, each of which is configured by connecting one PMOS transistor QP1 to QP5 and one NMOS transistor QN1 to QN5 in series.

Reference numeral 20 denotes a circuit block, which is an AND circuit 25 that performs an AND operation on the input signal IN and the chip activation signal CS;
And a circuit in which the inverter circuits INV1 to INV5 are cascaded. The AND circuit 25 inputs the input signal IN to the first-stage inverter circuit INV1 when the chip activation signal CS is at a high level, and the circuit block 20 is activated, while the chip activation signal CS is Low Leve
At the time of l, the input signal IN is prevented from being input to the first-stage inverter circuit INV1, and the circuit block 20 enters a standby state.

In this embodiment, the inverter circuit INV1
Although description will be made by taking INV5 as an example, any logic circuit including at least an NMOS transistor or a PMOS transistor may be used.

Inverter circuit of each stage in circuit block 20
In INV1 to INV5, when the circuit block 20 is in the standby state, that is, when the chip activation signal CS is at Low Level, the output of the AND circuit 25 becomes Low Level, and the first, third, and fifth stages Eye inverter circuit INV1, INV
3. While the input signal of INV5 is at Low level, the input signals of the second and fourth inverter circuits INV2 and INV4 are at Hi level.
gh Level. Therefore, in the standby state, the NMOS transistors QN1, QN3, QN5 and the PMOS transistors QP2, QP4 are turned off. These NMOS transistors Q
To change the gate-source voltages Vgs of N1, QN3 and QN5, a fourth power supply line Vssi is connected to the sources of these NMOS transistors. In order to change the gate-source voltage Vgs of these PMOS transistors QP2 and QP4, the source of these PMOS transistors is provided with a third
Power supply line Vcci is connected.

A power supply control circuit 10 is provided to change the voltage of the third power supply line Vcci and the voltage of the fourth power supply line Vssi. The power supply control circuit 10
A power supply line Vcc, a second power supply line Vss, and a chip activation signal CS are inputted, and a threshold voltage Vt of the transistors QP1 to QP5 and QN1 to QN5, and a standby state or an active state determined by the chip activation signal CS. , The respective voltages of the third power supply line Vcci and the fourth power supply line Vssi are controlled.

FIG. 3 is a voltage waveform diagram of the third power supply line Vcci and the fourth power supply line Vssi controlled by the power supply control circuit 10. As shown in FIG. 3A, the reference voltage level of the third power supply line Vcci is controlled to be equal to the voltage of the first power supply line Vcc in the active state. It is controlled to a reference voltage level slightly lower than the reference voltage level in the state.
On the other hand, the reference voltage level of the fourth power supply line Vssi is controlled to be equal to the voltage of the second power supply line Vss in the active state, and is smaller than the reference voltage level in the active state in the standby state in order to reduce leakage current. The voltage is controlled to a higher reference voltage level. With the above configuration, the transistors QN1, QN3, QN5, QP
2. The gate-source voltage Vgs of QP4 becomes smaller than the gate-source voltage in the active state, and this value Vgs
The difference voltage Vgs-Vt between the threshold voltage Vt and the transistor threshold voltage Vt also becomes a small value. Accordingly, the leakage current of the transistor flowing in proportion to the difference voltage is also reduced. As a result, the leakage current flowing in the standby state is smaller than that in the active state.
The current consumption is small and the power consumption is low.

As described above, the inverter circuits INV1, INV3, INV whose inputs are at the low level in the standby state.
For 5, the fourth power supply line Vssi is connected. As shown in FIG. 3B, the voltage of the fourth power supply line Vssi is lower than a desired value due to a variation in the manufacturing process when the threshold voltages Vtn of the NMOS transistors QN1 to QN5 in the circuit block 20 are changed. Is larger than the reference voltage level shown by the solid line, the threshold voltage is controlled by the power supply control circuit 10 so as to be smaller by the increase. as a result,
In each of the active and standby states, NM
As the threshold voltage Vtn of the OS transistors QN1 to QN5 increases, the gate-source voltage Vgs of the NMOS transistor increases.
And the difference (Vgs-Vtn) between the gate-source voltage Vgs of the NMOS transistor and its threshold voltage Vtn is kept constant, thereby suppressing the leak current in the standby state. In addition, the effect of keeping the operating speed in the active state constant can be obtained.

Similarly, as shown in FIG. 3 (b), the threshold voltage Vtn of the NMOS transistors QN1 to QN5 constituting the inverter circuit in the circuit block 20 becomes a desired value due to a variation in the manufacturing process. When the voltage is lower than the value, the voltage of the fourth power supply line Vssi is controlled by the power supply control circuit 10 so as to be higher than the reference level by the amount of the decrease in the threshold voltage. As a result, in the active state and the standby state, the NMOS transistors QN1 to QN1
As the threshold voltage Vtn of N5 decreases, the gate-source voltage Vgs of the NMOS transistor decreases, and
The value of (Vgs-Vtn) of the MOS transistor is kept constant, whereby the leakage current is suppressed small in the standby state, and the operation speed of the inverter circuit becomes constant in the active state, thereby improving the operation performance. The effect that improvement can be achieved is produced.

In the semiconductor circuit according to the present embodiment, the PMOS transistors QP are connected to the inverter circuits INV1, INV3 and INV5 whose inputs are at the low level in the standby state.
No particular correction of threshold voltage is performed for QP3, QP3, and QP5.
1.Since the leakage current of QN3 and QN5 determines the leakage current of the semiconductor circuit, and the active speed (ON current) of these NMOS transistors determines the operating speed of the semiconductor circuit when active, the circuit configuration is adopted. It is.

On the other hand, as described above, the inverter circuits INV2, INV2 whose inputs become High level in the standby state.
The third power supply line Vcci is connected to the NV4. As shown in FIG. 3C, the voltage of the third power supply line Vcci is lower than the desired value due to the variation in the manufacturing process when the threshold voltage Vtp of the PMOS transistors QP1 to QP5 in the circuit block 20 is changed. Is larger than the reference voltage level indicated by the solid line, the threshold voltage is controlled by the power supply control circuit 10 so as to increase by the increased amount. Also, PM
On the contrary, when the threshold voltage Vtp of the OS transistors QP1 to QP5 becomes smaller than a desired value, the power supply control circuit is configured to make the threshold voltage lower than the reference voltage level shown by the solid line by an amount corresponding to the decrease of the threshold voltage. 10 is controlled. As a result, in each of the active state and the standby state, the gate-source voltage Vg of the PMOS transistors QP1 to QP5 is changed by the amount corresponding to the change in the threshold voltage Vtp.
s also changes, and the value of the difference (Vgs-Vtp) between the gate-source voltage Vgs of the PMOS transistor and the threshold voltage Vtp is kept constant, thereby reducing the leakage current in the standby state. The effect of keeping the operating speed in the active state constant while suppressing the effect is obtained.

Next, FIG. 4 shows a specific example of the power supply control circuit 10. The power supply control circuit 10 may have any circuit configuration as long as the operation described above is satisfied. The power supply control circuit 10 shown in FIG. 4 includes two threshold value detection circuits 70a and 70b for generating a voltage of the third power supply line Vcci and two voltage generation circuits 80a and 80
0b, and two threshold value detection circuits 100a and 100b for generating the voltage of the fourth power supply line Vssi and two voltage generation circuits 110a and 110b. The threshold detection circuits 70a and 100a and the voltage generation circuits 80a and 110a are for active use,
70b and 100b and voltage generating circuits 80b and 110b are for standby. In FIG. 4, CS is a chip activation signal for switching between a standby state and an active state of the semiconductor circuit, as in FIG. 1. When the chip activation signal CS is at a low level, the chip for standby is activated. Signal CS is High Level
Switch to active when.

The basic operation of the power supply control circuit 10 is that the threshold value detection circuits 70a, 70b, 100a and 100b
1 to QP5, QN1 to QN5, and generate potentials proportional to the threshold voltages, and use the generated potentials as voltage generation circuits 80a, 80b, and 110.
a, 110b, and outputs the held potential as the voltage of the third power supply line Vcci or the voltage of the fourth power supply line Vssi. Hereinafter, the operation will be described in detail.

Referring to FIG. 4, the active threshold detecting circuit 70a and the voltage generating circuit 80a for controlling the voltage of the third power supply line Vcci will be described.
The potential of the node ref1 is equal to the two resistors R in the threshold detection circuit 70a.
1, R2 and the threshold voltage of the threshold voltage detection transistor QP1. The threshold voltage detecting transistor QP1 is a transistor of the circuit block 20.
This is a transistor manufactured by the same process as QP1 to QP5 and QN1 to QN5. The potential of the node ref1 increases when the threshold voltage of the threshold voltage detection transistor QP1 increases, and decreases when the threshold voltage decreases. The values of the resistors R1 and R2 are set so that the potential of the node ref1 becomes the reference level of the voltage of the third power supply line Vcci in the active state shown in FIG.
Selected. Further, the voltage generation circuit 80a includes a current mirror circuit 120 and a charge transistor QP4, and the charge transistor QP4 is turned on and off.
By controlling f by the current mirror circuit 120, the voltage of the third power supply line Vcci is maintained at the same potential as the potential of the node ref1. That is, when the threshold voltage of the threshold voltage detecting transistor QP1 increases, the potential of the node ref1 increases, and when the threshold voltage decreases, the potential of the node ref1 also decreases.
Of the power supply line Vcci also changes.

Also, in the standby threshold detecting circuit 70b, the values of the two resistors R1 'and R2' are determined by setting the potential of the node ref1 'to the reference potential of the voltage of the third power supply line Vcci during standby. The voltage of the third power supply line Vcci at the time of standby can be generated by the voltage generation circuit 80b. Two threshold value detection circuits 100a and 100b for generating a voltage of the fourth power supply line Vssi and two voltage generation circuits
The same applies to 110a and 110b, and a description thereof will be omitted.

Therefore, by incorporating the power supply control circuit 10 shown in FIG. 4 into a chip, the threshold voltage of the transistor in the circuit block 20 becomes a voltage value other than a desired value due to a variation in the manufacturing process. Also, the third power line Vcc
The voltage of i and the voltage of the fourth power supply line Vssi can be changed to a voltage value corresponding to the fluctuated threshold voltage, and the transistors in the circuit block 20 are changed with the temperature change when the circuit block 20 is used. , The voltage of the third power supply line Vcci and the voltage of the fourth power supply line Vssi can be satisfactorily changed in response to the fluctuation.

In this embodiment, the power supply control circuit 10 including the threshold voltage detecting transistor QP1 is provided to cope with a change in the threshold voltage of the transistor due to a temperature change when the circuit block 20 is used. And the third power line V
Although the voltage of the cci and the voltage of the fourth power supply line Vssi were changed, for example, the threshold voltage of a transistor built in this chip is measured in advance for each chip, and the threshold voltage is measured only based on the information of the threshold voltage. The voltage of the third power supply line Vcci and the voltage of the fourth power supply line Vssi may be controlled. In this case, it is not possible to control the power supply voltage corresponding to the change in the threshold voltage due to the temperature change.

FIG. 2 shows the effect of the semiconductor circuit of this embodiment. In this figure, the horizontal axis represents the normalized leakage current, and the vertical axis represents the number of chips. The point where the normalized leak current is "1" is that the chip is a good chip in which the operating speed of the circuit and the leak current flowing therethrough are well traded off. If the value is smaller than the point "1", the transistor has a large threshold voltage and the leakage current is small, but the operation speed is low. The chip has a small threshold voltage and a high operation speed but a large leakage current. As shown in the figure, in the conventional case where the power supply control circuit 10 of the present embodiment is not used, the variation of the leakage current is large, whereas the power supply control circuit 10 of the present embodiment does not.
In the case where is used, the variation of the leak current is suppressed to a small value. This is an effect of the present embodiment in that the value of the voltage (Vgs-Vt) is kept constant. It can be seen that the operating speed is stabilized along with the suppression of the leak current.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
An embodiment will be described.

FIG. 5 shows a semiconductor circuit according to a second embodiment of the present invention, and FIG. 6 shows an operation timing chart of the semiconductor circuit of FIG. In the first embodiment, the leakage current at the time of standby is reduced. In the present embodiment, the leakage current is reduced at the time of active in addition to the time of standby.

The semiconductor circuit shown in FIG. 5 includes a power supply control circuit 10, first to fourth power supply lines Vcc, Vss, Vcci, Vssi, and a circuit block 30. The power supply control circuit (low power consumption circuit) 10 has the same configuration as the power supply control circuit 10 of the first embodiment shown in FIG. The circuit block 30
Is composed of a sub-circuit block 40 composed of an NMOS transistor and a PMOS transistor, a set circuit 50, and a latch circuit 60. The power control circuit 10 is controlled by the CS signal. The set circuit 50 is composed of a logical product circuit, receives the input signal IN1, the set signal SET, and the chip activation signal CS, takes a logical product of them, and outputs the resulting signal to the sub-circuit block 40. . Further, the latch circuit 60 is controlled by a latch signal LAT, latches an output signal from the output node node1 of the sub-circuit block 40, and outputs the latched signal from an output terminal OUT. Reference numeral 70 denotes a SET / LAT signal generation circuit (signal generation circuit) that receives the input signal IN1 and generates the set signal SET and the latch signal LAT based on the signal IN1.

The operation of the semiconductor circuit according to the present embodiment will be described below with reference to FIGS.

In the present semiconductor circuit, the circuit block 30
Are controlled between an active state and a standby state by a chip activation signal CS. Chip activation signal CS is High L
In a situation where the circuit block 30 is activated in the evel state, the input signal IN1 and the set signal SET are input to the input terminals of the set circuit 50, and the latch signal LAT is input to the latch circuit 60.

Now, when the set signal SET is at the low level, regardless of the state of the chip activation signal CS, the set circuit
The output of 50 is fixed at Low Level, and the circuit block 30 enters a standby state. In order to suppress the leakage current in the standby state to a predetermined value, the third and fourth power supply lines Vcc
The voltage levels of i and Vssi are controlled by the power supply control circuit 10 in the same manner as described in the first embodiment. Circuit block 30
Are active, the inverter circuits INV1, INV1
When the input signals of V3 and INV5 are at a high level and the input signals of the other inverter circuits INV2 and INV4 are at a low level, a leakage current flows through the MOS transistors QP1, QN2, QP3, QN4, and QP5. Can not be suppressed only by the configuration of the sub-circuit block 40.

On the other hand, when the chip activation signal CS is at a high level and the set signal SET is at a high level, the input signal I
When N1 is input to the set circuit 50, the input signal IN1 is input to the sub-circuit block 40 via the set circuit 50. The signal input to the sub circuit block 40 propagates through the sub circuit block 40, changes the state of the internal node node1, and is input to the latch circuit 60. The signal input to the latch circuit 60 is latched by the latch circuit 60 only when the latch signal LAT becomes High Level, and the voltage of the output terminal OUT has a waveform as shown in FIG. By latching the signal in the latch circuit 60, even if the set signal SET of the set circuit 50 transitions from High to Low and the output of the set circuit 50 is forcibly changed to Low Level,
The output of the latch circuit 60 does not change.

As described above, in the semiconductor circuit of the present embodiment, when the chip activation signal CS is at the high level,
If the signal is at a high level, the sub-circuit block 40 will be in an active state, but if the set signal is at a low level, the sub-circuit block 40 will be in a standby state and an internal node
node1 is fixed to Low Level. Therefore, the set signal SE
If the "H" level period of T is set shorter than the "H" level period of the input signal IN1, a part of the period in which the sub-circuit block 40 is in the active state is forcibly and pseudo-standby. can do. Therefore, the set circuit 50 and the SET / LAT signal generation circuit 70 constitute a pseudo standby circuit 80. Even during this period of the pseudo standby state, the output signal of the sub-circuit block 40 is latched by the latch circuit 60, so that the sub-circuit block 40 is apparently in the active state. The latch circuit 60 and the SET / LAT signal generation circuit 70 constitute a signal holding circuit 90 for holding the output signal value of the sub-circuit block 40 in the pseudo standby state.

Since the pseudo standby state is the same state as the standby state, the pseudo standby state during the active state of the sub-circuit block 40 is the same as described in the first embodiment. In the period of
Off-line of transistors constituting sub-circuit block 40
The current consumption can be suppressed to a small value, and an increase in current consumption in the active state can be suppressed.

FIG. 7 shows a specific configuration of the SET / LAT signal generation circuit 70. In the figure, the SET and LAT signal generation circuit 7
Numeral 0 denotes a circuit which receives an input signal IN1 to the set circuit 50, detects "H" input of the input signal IN1, and generates a set signal SET and a latch signal LAT.

FIG. 8 is a timing chart showing the operation of the SET and LAT signal generation circuit 70. The internal configuration of the SET / LAT signal generation circuit 70 of FIG. 7 will be described with reference to the timing chart of FIG. In FIG. 7, reference numerals 80 and 90 denote delay circuits constituted by inverter chains, which control the timing of signals at the nodes N1, N2 and N5. The delay circuit 80 is an odd number of inverters and the delay circuit 9
0 is constituted by an even number of inverters. The nodes N1 and N2 are counted from the input terminal N0 of the input signal IN1,
This is the output terminal of the odd-numbered inverter.

When the input signal IN1 is input to the node N0, signals delayed by time a and time b from the input signal IN1 propagate to the nodes N1 and N2, respectively. Where 2
The two times a and b are adjusted by the number of inverter stages of the delay circuit 80. The NAND circuit 150 generates a pulse of "L" level in the period a, and the pulse is inverted by the inverter INV1.
A T signal is generated.

The NAND circuit 151 and the NOR circuit 152
Respectively output pulses having a width of time b to nodes N3 and N4.
The NOR circuit 153 receives the output of the NAND circuit 151 and the output obtained by inverting the output of the NOR circuit 152 by the inverter INV2, and outputs the output signal to the delay circuit 90.
, And becomes the latch signal LAT. Here, the latch signal LAT
Can be adjusted by the number of inverter stages of the delay circuit 90. Of the latch signal LAT, NAND circuit 1
The pulse generated by 51 is a signal for latching the pulse of the output node node1 of the sub-circuit block 40, and the pulse generated by the NOR circuit 152 is the potential of the output node OUT of the latch circuit 60. Is a signal for resetting.

The operation timing of the set circuit 50 and the latch circuit 60 can be automatically generated by the SET and LAT signal generation circuit 70 based on the input signal IN1.
When the input signal IN1 does not change, the signal generation circuit 70 does not operate, and power consumption can be further reduced. The SET / LAT signal generation circuit 70 shown in FIG.
Any configuration may be used as long as it performs the same operation.

[0060]

As described above, according to the semiconductor circuits of the first to eighth aspects of the present invention, the voltage of the power supply line connected to the transistor that is cut off in the standby state is reduced by the voltage of the transistor. Since the threshold voltage is changed according to the change in the threshold voltage, even if the threshold voltage of the transistor changes due to a change in the manufacturing process, the gate-source voltage of the transistor can be maintained at a constant value, Accordingly, an effect is obtained that the off-state leakage current of the transistor in the standby state can be suppressed to a small value.

According to the semiconductor circuit of the ninth to sixteenth aspects, when the circuit is in the active state, a part of the period of the active state is forcibly set by the pseudo standby circuit. Since the pseudo standby state is set equal to the low power consumption standby state, it is possible to reduce the power consumption even in this active state.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a semiconductor circuit according to a first embodiment of the present invention.

FIG. 2 is a distribution diagram of a leakage current in the same semiconductor circuit.

FIG. 3A is an explanatory diagram of reference levels of voltages of third and fourth power supply lines of the semiconductor circuit, and FIG. 3B is a diagram illustrating a voltage V of a fourth power supply line;
FIG. 8C is an explanatory diagram of control for changing ssi, and FIG. 9C is an explanatory diagram of control for changing the voltage Vcci of the third power supply line.

FIG. 4 is a diagram showing an internal configuration of a power supply control circuit provided in the semiconductor circuit.

FIG. 5 is a diagram illustrating a semiconductor circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing operation timing of the semiconductor circuit.

FIG. 7 is a diagram showing an internal configuration of a SET and LAT signal generation circuit provided in the semiconductor circuit.

FIG. 8 is a diagram showing operation timing of the semiconductor circuit.

[Explanation of symbols]

 QN1 to QN5 NMOS transistors QP1 to QP5 PMOS transistors Vcc First power line Vss Second power line Vcci Third power line Vssi Fourth power line 10 Power control circuit (low power consumption circuit) QP1 For detecting threshold voltage Transistor IN1 input signal CS chip activation signal SET set signal LAT latch signal 20, 30 circuit block 40 sub circuit block 50 set circuit 60 latch circuit 70 SET / LAT signal generation circuit (signal generation circuit) 80 pseudo standby circuit 90 signal holding circuit

Claims (16)

(57) [Claims] 1. A semiconductor circuit that switches between an active state and a standby state, comprising: a transistor that is cut off in the standby state; a power supply line connected to the transistor; And a power supply control circuit for controlling to change the threshold voltage according to the variation of the threshold voltage. 2. The power supply control circuit controls the voltage of the power supply line to change in accordance with a change in a threshold voltage of the transistor accompanying a change in a manufacturing process of the transistor. 1
The semiconductor circuit according to the above. 3. The semiconductor circuit according to claim 1, wherein the power supply control circuit includes a threshold voltage detecting transistor that monitors a threshold voltage of the transistor. 4. The power supply control circuit according to claim 1, wherein a voltage difference between the gate-source voltage Vgs of the transistor and a threshold voltage Vt of the transistor is always a constant value Vgs-Vt. 2. The semiconductor circuit according to claim 1, wherein the voltage of the semiconductor circuit is changed. 5. The semiconductor circuit according to claim 1, wherein a reference voltage level of the power supply line is set to a different voltage value between the active state and the standby state. 6. A first and second power supply line, a third and fourth power supply line, a circuit block connected to the first, second, third and fourth power supply line, and the circuit A PMOS transistor and an NMOS built in the block and connected to one of the third and fourth power supply lines;
A transistor; changing a voltage of the third power supply line in accordance with a change in a threshold voltage of the PMOS transistor with reference to a voltage of the first power supply line; And a power supply control circuit for changing the threshold voltage of the NMOS transistor in accordance with a change in the threshold voltage of the NMOS transistor based on the voltage of the second power supply line. 7. The power supply control circuit changes a voltage of the third power supply line so that a difference voltage between a gate-source voltage of the PMOS transistor and a threshold voltage of the PMOS transistor always becomes a constant value. And changing the voltage of the fourth power supply line so that the difference voltage between the gate-source voltage of the NMOS transistor and the threshold voltage of the NMOS transistor always becomes a constant value. 7. The semiconductor circuit according to 6. 8. The semiconductor circuit according to claim 6, wherein reference voltage levels of the third and fourth power supply lines are set to different voltage values in the active state and the standby state, respectively. . 9. A semiconductor circuit having a circuit block that switches between an active state and a standby state, wherein the semiconductor circuit has a lower power consumption than the active state in the standby state. A pseudo standby circuit for forcibly setting a part of the period of the active state to a pseudo standby state equal to the standby state reduced in power consumption by the low power consumption circuit in the active state. A semiconductor circuit, comprising: 10. The circuit block includes a transistor that cuts off in the standby state, a power supply line connected to the transistor is provided, and the power saving circuit includes a power supply line in the standby state. 10. The semiconductor circuit according to claim 9, further comprising a power supply control circuit for controlling a voltage of the line to change according to a change in a threshold voltage of the transistor. 11. The power supply control circuit according to claim 1, wherein a difference voltage Vgs-Vt between a gate-source voltage Vgs of the transistor of the circuit block and a threshold voltage Vt of the transistor is always constant. 11. The semiconductor circuit according to claim 10, wherein a voltage of said power supply line is changed. 12. A pseudo standby circuit, comprising: a signal generation circuit for generating a set signal; and forcing the circuit block when the circuit block is in an active state and no longer receives the set signal from the signal generation circuit. And a set circuit for setting the pseudo standby state.
2. The semiconductor circuit according to 1. 13. The semiconductor circuit according to claim 9, further comprising a signal holding circuit for holding a value of a signal output from said circuit block immediately before said pseudo standby state in said pseudo standby state. 14. The signal holding circuit, when in the active state, generates a latch signal for holding an output signal of the circuit block, and receives the latch signal of the signal generation circuit, 14. The semiconductor circuit according to claim 13, further comprising a latch circuit for latching an output signal of the circuit block. 15. The semiconductor circuit according to claim 10, wherein a reference voltage level of said power supply line is set to a different voltage value between said active state and said standby state. 16. The semiconductor according to claim 12, wherein the signal generation circuit inputs an input signal to the circuit block, and generates a set signal or a latch signal based on the input signal. circuit.