JP2845232B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plated heat sink structure (hereinafter, referred to as a PHS structure), and more particularly to a semiconductor device having a high-power GaAs field-effect transistor (FET) that generates a large amount of heat. Semiconductor device.

[0002]

2. Description of the Related Art Generally, the channel temperature of a high-power GaAs FET rises during operation, but it is necessary to reduce the thermal resistance of the FET including the package and suppress the rise of the channel temperature in order to ensure reliability. In order to reduce the thermal resistance of the FET chip, the thickness of the GaAs substrate is reduced, and the rear surface is mounted close to a heat sink or package, so that the heat generated by the elements formed on the front surface of the GaAs substrate can be reduced. It is effective to quickly radiate heat from the back surface of the substrate. In this case, a metal layer such as an Au plating layer is formed on the back surface in order to maintain the mechanical strength of the FET chip. The structure manufactured in this way is called a PHS structure.

FIG. 7 shows a plan view of a conventional high power GaAs FET chip 21 having a PHS structure of this type and a sectional view taken along the line BB. An unillustrated FET element is formed on the surface of the GaAs substrate 22 and covered with an insulating film 23. The GaAs substrate 22 is polished or etched on the back side to be thinned to 30 to 50 μm.
And an Au plating film 2 having a thickness of 10 to 30 μm
5 are formed. Then, as shown in FIG. 8, the FET chip 21 is
7 and is mounted on the back surface by brazing with a solder 26 such as an AuSn alloy.

[0004]

When the FET chip is mounted on a package or the like as described above, A
It is necessary to heat at 300 ° C. or more to melt solder such as uSn alloy. At this time, as shown in FIG.
Due to the difference in the thermal expansion coefficient between the aAs substrate 22 and the Au plating film 25, the peripheral portion of the FET chip 21 is warped to the surface side, and the peripheral portion does not adhere to the package, and a gap is generated. For this reason, the solder 26 is formed thicker in this peripheral portion, and the thermal resistance of the peripheral portion of the FET chip having a thicker solder layer is higher than that of the central portion of the chip. As a result, the channel temperature of the FET element locally rises in the peripheral portion during operation, causing problems such as thermal runaway, thermal destruction, and deterioration in long-term reliability. In particular, high-power FETs employ a structure called unitary FETs arranged in parallel in order to gain gate width.However, increasing the gate width to improve output increases the chip width, so the chip length increases. The amount of warpage in the side direction increases, and as a result, the thermal resistance at both ends increases.

The thermal resistance of a GaAs FET chip is G
This is a value obtained by adding the thermal resistances of the respective portions of the aAs substrate, the solder layer, and the package base. Simply, it is determined by the area where the heat flows from the heat generating portion where the element is formed, the thickness of the layer, and the thermal conductivity of each material. AuSn solder, which is usually used at the time of assembly and mounting, operates the mounted FET for a long time to diffuse Sn, so that the thermal conductivity decreases and the thermal resistance of the solder layer increases.

In order to solve such a problem, Japanese Patent Application Laid-Open No. 61-23350 discloses a method in which a chip itself is formed to be thick and partially etched so that a portion immediately below an element portion is thinned. A structure for filling with Au has been proposed. In this structure, since the chip thickness is increased, the warpage of the chip at the time of assembly can be reduced, and the above problem can be avoided. However, since the thickness directly under the element portion is made thinner and the Au layer to be filled is formed thicker, the stress applied to the element portion becomes large when a temperature change occurs, and cracks occur in the thinned element portion. A new problem arises, which causes a reduction in chip reliability.

An object of the present invention is to provide a highly reliable semiconductor device which suppresses an increase in thermal resistance in a peripheral portion of a chip even when a warp occurs in the chip and makes the thermal resistance in the chip uniform. It is in.

[0008]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device having a PHS structure in which a relatively thick metal film is formed on the back surface of a semiconductor substrate having a semiconductor element formed on the surface. The semiconductor substrate is characterized in that the thickness of the peripheral portion of the semiconductor substrate including a part of the region is thinner than the central portion. The semiconductor element has, for example, an interdigit structure in which unit FETs are arranged in parallel, and the semiconductor substrate is formed such that the substrate thickness at both ends in the arrangement direction of the unit FETs is smaller than that at the center. Here, the substrate thickness at the peripheral portion of the semiconductor substrate is set to about 50 to 70% of the substrate thickness at the central portion, and the peripheral portion of the semiconductor substrate having the reduced substrate thickness is more than the central portion. 1/3 ~
It is preferably in the range of 1/5 length.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a high-power GaAsFE of the present invention.
In this embodiment, the present invention is applied to a T FET chip, where (a) is a plan view and (b) is a cross-sectional view taken along line AA. FET chip 1
The source electrode S,
A plurality of FETs having a gate electrode G and a drain electrode D
Are formed. Here, since it is necessary to increase the gate width to improve the output, a structure called a comb gate structure in which a plurality of unit FETs are arranged in parallel is used as a basic FET structure. In this case, the unit FET
When the finger length is constant, the gate width is determined by the number of fingers.
Although zero unit FETs are arranged, the lateral width of the chip increases accordingly, and the unit FETs are formed in a rectangular shape that is long in one direction (width direction) as illustrated.

The GaAs substrate 2 of the FET chip 1 is 3
Although it is formed as a thickness of about 0 to 50 μm, on the back surface, both ends 2 a in the width direction are cut over a region of １ ／ to １ ／ of the length in the width direction,
The thickness of both ends 2a is reduced to about 10 to 30 μm. Thereby, the thickness of the both ends 2a is
The thickness is 50 to 70% of the thickness of the central portion 2b. Then, a thin Ti /
An Au film 4 is formed, and an Au plating film 4 having a thickness of 10 to 30 μm is formed on the surface thereof by a plating method. An insulating film 3 for covering the FET is formed on the surface of the GaAs substrate 2. In this embodiment, the insulating film 3 does not exist in the periphery of the chip 1.

2 and 3 are sectional views showing a method of manufacturing the FET chip 1 shown in FIG. 1 in the order of steps. First, FIG.
1A, an FET element as shown in FIG. 1 is formed on the surface of a GaAs substrate 2, here, a GaAs wafer, and these FET element formation regions are covered with an insulating film 3; Is attached to the glass plate 12 with an adhesive 11 such as wax with the lower side facing down. In this state, Ga
The GaAs wafer is thinned by polishing the back surface of the As wafer 2. Further, using an etching solution such as sulfuric acid, hydrogen peroxide or a mixture of phosphoric acid and hydrogen peroxide, G
Perform aAs etching, and finally reduce the thickness to 30 to 50 μm. Next, as shown in FIG. 2B, a photoresist 13 is formed so as to cover the chip portion, and the above-mentioned etching solution or reactive ion etching (RIE) using a chlorine-based gas is used. As a result, the region between the chips is removed by etching, and separated into individual chips.

Further, as shown in FIG. 2C, a 2/3 to 4/5 region at the center in the width direction of the chip is covered with a photoresist 14, and the same reactive ion etching as described above is used. Then, both ends 2a of the chip are etched by about 10 to 20 μm to form both ends 2a even thinner. next,
As shown in FIG. 3A, after removing the photoresist, Ti / Ti is formed on the entire surface by a sputtering method as a plating underlayer.
An Au film 4 is deposited. Here, as the film thickness of Ti and Au, for example, Ti (1000 °) / Au (1000
Use Å). Next, after a photoresist 15 is formed so as to protect the chip separation region, an Au film 5 is formed to a thickness of 10 to 20 μm on the chip back surface region by using an electrolytic plating method. Thereafter, as shown in FIG. 3B, the photoresist is removed, and Ti / Au other than the Au-plated region is removed.
The film 4 is removed by etching by an ion milling method. Furthermore, the FET chip is completed by peeling the chip from the glass plate 12 to which the GaAs wafer is attached.

The FET chip thus formed is mounted on a package 17 using AuSn solder 16, as shown in FIG. At this time, soldering is performed with the Au plating film 5 on the back surface of the FET chip in contact with the package 17. Therefore, due to the heating at the time of the soldering, warpage occurs based on the difference in the coefficient of thermal expansion between the GaAs substrate 2 and the Au plating film 5, and both ends 2a of the chip 1 are curved upward.

Then, the F of the mounted FET chip is
When the FET is operated by energizing the ET element, part of the applied DC power becomes output power, but most is consumed as heat, and heat is generated in the FET formation region. FIG. 5 shows the FET chip of the present invention shown in FIG.
3 shows a channel temperature distribution in the long-side direction of the chip when the conventional FET chips shown in FIG. Here, the DC bias indicates a case where the drain voltage is 10 V and the drain current is 5 A, for example. As shown in FIG. 5, in the conventional chip, the channel temperature at both ends of the chip is increased, whereas in the chip of the present invention, the increase in the channel temperature at both ends is suppressed. Has become. From this, in the configuration of the present invention, an increase in thermal resistance in the peripheral portion of the chip is suppressed, and a highly reliable semiconductor device with uniform thermal resistance in the chip can be obtained.

FIG. 6 is a sectional view of an FET chip according to a second embodiment of the present invention. In this embodiment, both ends 2a of the FET chip 1A are made of GaAs, as shown in FIG.
The back surface of the substrate 2A is cut into a taber shape, and the thickness is gradually reduced with respect to the central portion 2b. An Au plating film 5 is formed on the back surface of the GaAs substrate 2A. With this configuration, the FET
By reducing the thickness of both ends of the chip, FET
Even when the thickness of the solder at both ends is increased due to warpage generated when the chip is mounted, the channel temperature distribution of the entire FET chip including both ends can be made uniform.

Here, in each of the above embodiments, an example is shown in which a plurality of FETs are arranged in one direction on the FET chip. However, the plurality of FETs are arranged in one direction and in a direction orthogonal thereto. When arranged, the thickness of the semiconductor substrate is reduced at the periphery of the FET chip.

Japanese Patent Application Laid-Open No. 6-177178 discloses a structure in which a peripheral portion of the back surface of a semiconductor chip is cut out and mounted on a substrate by soldering as in the present invention. The technology is not a semiconductor device having a PHS structure in which a plating film is formed relatively thickly on the back surface of the semiconductor chip, and furthermore, it is not intended to make the thermal resistance uniform due to the warpage generated in the semiconductor chip. Therefore, the actual configuration is different from the present invention. In addition, the technique disclosed in the publication suggests that the characteristics of a plurality of elements are made uniform by forming both ends in the arrangement direction of the plurality of elements thinner to make the thermal resistance uniform, as in the present invention. It does not do.

[0018]

As described above, according to the present invention, in a semiconductor device having a PHS structure, the thickness of a peripheral portion of a semiconductor substrate including a part of a region where a semiconductor element is formed is smaller than that of a central portion. As a result, even if the mounted semiconductor device is warped, the thermal resistance at the peripheral portion can be reduced to the same level as the central portion, and the overall thermal resistance of the semiconductor device can be made uniform. Element temperature distribution can be maintained. Thereby, high output GaAs
It is possible to obtain a sufficiently reliable semiconductor device even for an sFET.

[Brief description of the drawings]

FIG. 1 is a plan view and a cross-sectional view taken along line AA of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a first sectional view showing the method of manufacturing the semiconductor device in FIG. 1 in the order of steps;

FIG. 3 is a second sectional view illustrating the method of manufacturing the semiconductor device in FIG. 1 in the order of steps;

FIG. 4 is a sectional view showing a state where the semiconductor device of FIG. 1 is mounted.

FIG. 5 is a diagram showing a comparison between channel temperature distributions in a conventional semiconductor device and each semiconductor device of the present invention.

FIG. 6 is a cross-sectional view of a second embodiment of the present invention.

FIG. 7 is a plan view and a cross-sectional view taken along line BB of an example of a conventional semiconductor device.

8 is a sectional view of a state where the semiconductor device of FIG. 7 is mounted.

[Explanation of symbols]

 1, 1A FET chip 2, 2A GaAs substrate 2a Both ends 2b Central part 3 Insulating film 4 Ti / Au film 5 Au plating film

Claims (6)

(57) [Claims] In a semiconductor device having a plated heat sink structure in which a relatively thick metal film is formed on a back surface of a semiconductor substrate having a semiconductor element formed on a front surface, a region where the semiconductor element is formed is provided. A semiconductor device characterized in that the thickness of a peripheral portion of a semiconductor substrate including a part thereof is formed thinner than that of a central portion. 2. The semiconductor element is configured as an interdigit structure in which unit FETs are arranged in parallel, and the semiconductor substrate is formed such that the substrate thickness at both ends in the arrangement direction of the unit FETs is smaller than that at the center. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein a substrate thickness at a peripheral portion of the semiconductor substrate is set to about 50 to 70% of a substrate thickness at a central portion. 4. The semiconductor device according to claim 3, wherein a peripheral portion of the semiconductor substrate having a reduced substrate thickness has a length in a range of ３ to ５ of a central portion. 5. The semiconductor device according to claim 1, wherein the semiconductor substrate is a GaAs substrate, and the metal film on the back surface of the GaAs substrate is an Au plating film. 6. The semiconductor device according to claim 5, wherein the semiconductor device is mounted on a package or a heat sink with a brazing metal having wettability to a metal film on a back surface.