JP2795140B2 - Runaway monitoring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a runaway monitoring device for resetting a microcomputer when the microcomputer runs away.

[0002]

2. Description of the Related Art FIG. 1 shows an outline of a vehicle-mounted traveling position display device. In FIG. 1, reference numeral 1 denotes a direction sensor,
The direction sensor 1 uses a geomagnetic sensor for detecting the absolute running direction of the vehicle and an optical gyro for detecting the relative running direction of the vehicle. Reference numeral 2 denotes a distance sensor that generates a pulse corresponding to the number of rotations of the wheels, and 3 denotes various sensor signals such as an on / off signal of a brake switch, a parking switch, and the like, and a power supply voltage monitoring signal. Reference numeral 4 denotes a sensor signal processing unit for processing sensor signals such as a direction sensor 1 and a distance sensor 2. Reference numeral 5 denotes a GPS (Global Positioning System) receiver. The GPS receiver 5 receives radio waves transmitted from a plurality of satellites and performs calculations. By doing so, the position (latitude, longitude) of the receiving point can be obtained. Reference numeral 6 denotes a CD-ROM drive. The CD-ROM drive 6 reads map data from a CD-ROM 7 on which map data is recorded. Reference numeral 8 denotes a display / operation unit provided in the vehicle interior. The display / operation unit 8 is provided on a liquid crystal display 8A for displaying a map, a current traveling position, a direction, and the like of the automobile, and is provided on a front surface of the liquid crystal display 8A. The touch panel 8B includes switches for instructing enlargement and reduction of a display map,
A switch for instructing a route search, a switch for selecting a destination from the place names displayed on the liquid crystal display 8A, and the like are provided. Reference numeral 9 denotes an apparatus main body, which is installed in a trunk room or the like.

Next, the configuration of the apparatus main body 9 will be described.
10 is a CPU (Central Processing Unit) for performing various calculations, 11
Is a ROM (Read Only Memory) in which programs for various operations performed by the CPU 9 are stored, 12 is data from the azimuth sensor 1, the distance sensor 2, the GPS receiver 5, the CD-ROM drive 6, etc., and the operation results of the CPU 10, etc. (DRAM), 13 is a backup memory (SRAM) for holding necessary data even when power supply to the apparatus main body 9 is stopped, 14 is characters displayed on the liquid crystal display 8A, A memory (kanji, font ROM) in which patterns such as symbols are stored; 15 an image processor for forming a display image based on map data, current position data of the vehicle, etc .;
Map data, current location data and kanji output from
A memory (VRAM) for storing images to be displayed on the liquid crystal display 8A by synthesizing kanji and fonts such as street names and road names output from the font ROM 14;
This is an RGB conversion circuit for converting the output data of M16 into a color signal, and the color signal is output from the RGB conversion circuit 17 to the liquid crystal display 8A. Reference numeral 18 denotes a communication interface. Reference numeral 19 denotes a runaway monitoring unit. The runaway monitoring unit 19 monitors the runaway of the CPU 10 and resets the CPU 10 when the CPU 10 runs away.

In FIG. 1, an output of a direction sensor 1 and an output of a distance sensor 2 are transmitted to a CPU 10 via a sensor processing unit 4.
Sent to The CPU 10 calculates the current position of the vehicle, and obtains the latitude and longitude of the current position. Also GPS
The current position is corrected based on the data from the receiver 5. The map data of the unit corresponding to the current position is read from the CD-ROM 7 by the CD-ROM drive 6 based on the current position obtained in this manner, and the map data is stored in the memory (DRAM) 12 via the communication interface 18. Is stored. A part of the map data stored in the DRAM 12 is read by the CPU 10,
The image data is converted into image data by the image processor 15 and written into the image memory 16. The image data stored in the image memory 16 is converted into color signals by the RGB conversion circuit 17 and sent to the liquid crystal display 8A, where a map of a predetermined range centering on the current position is displayed. If the map data read from the DRAM 12 contains character codes and symbol codes, patterns corresponding to these character codes and symbol codes are read from the kanji and the font ROM 14, and characters such as place names are displayed on the liquid crystal display 8A together with the map. , School, etc. are displayed. Further, the current position displayed on the liquid crystal display 8A is sequentially changed based on the traveling speed and traveling azimuth sequentially obtained as the vehicle travels.

FIG. 2 shows a circuit configuration of the runaway monitoring section 19 of FIG. In FIG. 2, reference numeral 10 denotes the CPU,
The CPU 10 is controlled by the OS to sequentially activate tasks having different priorities and execute various processes. Reference numeral 20 denotes a watchdog timer that constitutes the runaway monitoring unit 19. The watchdog timer 20 includes a plurality of flip-flops. The output of the last flip-flop is connected to the reset terminal 22 of the CPU 10. The reset terminal 23 of the watchdog timer 20 is connected to the port 24 of the CPU 10,
The watchdog timer 20 is reset by a reset signal output from this port. 21
Is a clock generator, and a clock signal output from the clock generator 21 is
Is input to the first-stage flip-flop.

Next, regarding the operation of the conventional runaway monitoring device,
This will be described with reference to FIGS. FIG. 9 shows an idle task (task having the lowest priority) processing in the conventional example. In FIG. 9, in step S1, the CPU
HIGH is output from the port 24 of 10. Next, in step S2, a predetermined time is waited, and in step S3, the CPU 1
LOW is output from the port 24 of 0. Step S above
A reset signal is generated in 1 to S3, and the watchdog timer 20 is reset by the reset signal.
Next, in step S4, the process returns to step S1 after waiting for a predetermined time.

FIG. 10 shows the task processing of the conventional runaway monitoring device with the passage of time, and FIG. 11 shows the count value of the watchdog timer 20 in the operation shown in FIG. As shown in FIG. 10, the CPU 10 executes a task A, a task B, a task C, and a task D (idle task) under the control of the OS. Among tasks A to D, task A has the highest priority, and task B, task C,
Task D has a lower priority, and task D has the lowest priority. The generation of the reset signal shown in FIG. 9 is performed in task D. Task A in the travel position display device is a task of drawing a map, for example, task B is a task of reading data from the CD-ROM 7, task C is a task of determining whether a touch panel switch is on or off, and the like. It is.

As shown in FIG. 10, when a reset signal is applied to the watchdog timer 20 at the timing (# 1) during the execution of the idle task (task D) (the timing of step S1 in FIG. 9). , The watchdog timer 20 is reset. Thereafter, steps S2, S3, and S4 of FIG. 9 are executed. When a system call is notified to the OS after a lapse of a predetermined time in step S4, the processing of the idle task is interrupted, and the task C is activated. During the execution of the task C, when the OS is notified of the system call of the higher priority task, the higher priority task A is activated. When the task A ends, the processing of the task C that was being executed is restarted. When the processing of the task C is completed, the processing of the idle task D is restarted, and a reset signal is applied to the watchdog timer 20 at the timing (# 2). Thereafter, as shown in FIG. 10, the task with higher priority is executed with priority.
Task D is executed during a period in which tasks A to C are not processed,
A reset signal is applied to the watchdog timer 20 every time a predetermined time elapses during the execution period of the task D.

FIG. 11 shows the clock count value of the watchdog timer 20. Since the watchdog timer 20 is reset at the timing (# 1) in the task D, the clock count value becomes 0, and the next reset signal Until is applied, the clock count value of the watchdog timer 20 increases. When the idle task is executed at an appropriate frequency as shown in FIGS.
Since the watchdog timer 20 is reset before the reset signal is output to the PU 10, the CPU 10 is not reset.

FIGS. 12 and 13 show the above conventional example.
This shows an operation when a task with a high priority is continuously executed and an idle task is not executed at an appropriate frequency. After the reset signal is generated at the timing (# 1) in FIG. 12 and the watchdog timer 20 is reset, the tasks C, B, and A are continuously executed, and the task D is not executed for a predetermined time (t _R ) or more. Shows the case.
After the watchdog timer 20 is reset at the timing (# 1), the increased count value of the watch dog timer 20 reaches a predetermined count value (T _R), the watchdog timer 20 from CPU10 of the reset terminal 22
, A reset signal is output, the CPU 10 is reset, an initial task is started, and initialization processing is executed.
After that, the task B is executed, and when the task B is completed, the task D is executed and the timing during the execution of the task D (# 2)
, A reset signal is applied to the watchdog timer 20.

As described above, in the conventional runaway monitoring device,
Watchdog timer 20 for tasks with the lowest priority
When a high-priority task is continued, the CPU 10 is frequently reset, and the initial task is executed each time, so that the process is interrupted. Was. For example, in the case of the travel position display device shown in FIG.
When B and C are continuously executed, the CPU 10 is frequently reset, and the initial task is executed each time the reset is performed. Therefore, a task for drawing a map or the like (task A) and reading data from the CD-ROM 7 are performed. Task (task B), a task (task C) for determining whether a touch panel switch is on or off, and the like are interrupted.

In order to solve such a conventional problem, the set time (t _R ) of the watchdog timer 20 may be increased. However, in order to increase the set time (t _R ) of the watchdog timer 20, Must increase the number of flip-flops of the watchdog timer 20 or divide the clock generated by the clock generator 21 and apply the divided clock to the watchdog timer 20. The cost was high.

[0013]

As described above, in the above-mentioned conventional example, when the high-priority task is continuously executed, the watchdog timer is not reset, so that the CPU 10 is frequently reset. As a result, there is a problem that the processing is interrupted every time. To solve this problem, if the setting time of the watchdog timer is increased, the hardware configuration becomes large (for example, the number of flip-flop stages of the watchdog timer). And the hardware configuration becomes large, for example, a frequency divider for dividing the clock must be added separately).

The present invention solves the above-mentioned conventional problems, and does not interrupt the processing even if a high-priority task is continuously executed without increasing the hardware configuration. It is an object to provide a runaway monitoring device.

[0015]

In order to achieve the above object, the present invention provides processing means for executing a plurality of processes in accordance with priorities and executing a top priority interrupt process at predetermined time intervals. A watchdog timer for counting clock signals output from the clock generator and resetting the processing means when the count value reaches a predetermined value; an interrupt counter for counting the number of times of the interrupt processing; Determining means for determining whether the lowest priority processing among the plurality of processings has been executed while the interruption counter counts a predetermined value; and the interruption processing until the interruption counter reaches a predetermined value. Means for outputting a reset signal to the watchdog timer every time the interrupt counter reaches a predetermined value, and when it is determined that the processing with the lowest priority is being executed, Means for resetting the watchdog timer and outputting a reset signal to the watchdog timer when it is determined that the lowest priority processing is not being executed when the interrupt counter reaches a predetermined value. Means.

[0016]

According to the present invention, the clock signal output from the clock generator is counted by a watchdog timer, and the processing means is reset when the count value of the watchdog timer reaches a predetermined value. In the runaway monitoring device that prevents runaway by counting, the number of interrupt processes is counted by an interrupt counter, and the determination means determines whether or not the process with the lowest priority has been executed. Until the number of interrupt processing reaches a predetermined value, the watchdog timer is reset for each interrupt processing, and when the number of interrupt processing reaches the predetermined value, the processing with the lowest priority is executed by the determination unit. Only in such a case, the interrupt counter is reset and the watchdog timer is reset.

[0017]

FIG. 3 to FIG. 8 show an embodiment of the present invention.
It will be explained together. The hardware configuration of the present embodiment is the same as the conventional example, and is as shown in FIGS. FIG. 3 shows the processing of this embodiment. In this embodiment, tasks A, B,
A reset signal is generated by an interrupt process at regular intervals of higher priority than C and D, and the watchdog timer is reset. As shown in FIG. 3, when an interrupt occurs at regular intervals, it is determined in step S1 whether the count value of the interrupt counter is equal to or greater than n (n is a positive integer). Step S
If “1” is determined as YES, it is determined in step S2 whether the idle flag is set to “1”. Step S2
If the determination is YES, the process proceeds to step S3, and the idle flag is set to "0". The idle flag is set to "0" in step S3, the interrupt counter is set to "0" in step S4, and the process proceeds to the next step S5. On the other hand, if it is determined in step S1 that the count value of the interrupt counter is not equal to or more than n, the process proceeds to step S8, the interrupt counter is incremented, and the process proceeds to step S5. Step S5
Then, HIGH is output from the port of the CPU 10, and after waiting for a certain time in the next step 6, the CPU 1
The port of 0 is set to LOW. The above steps S5, S6
At S7, a reset signal to the watchdog timer 20 is generated.

FIG. 4 shows the processing of the idle task (task D) having the lowest priority. When the task D is executed, the idle flag "1" is set.

Next, the operation of this embodiment will be described with reference to FIGS. As shown in FIG. 5, when an interrupt request is generated at regular intervals during execution of the idle task (task D), the processing shown in FIG.
In step S1, the count value of the interrupt counter is set to n
(Set value n = 6). If the interrupt count value is 5 at the stage before the interrupt, the determination in step S1 is NO, and the process proceeds to step S8, where the interrupt count value is incremented. Therefore, the interrupt count value is 5 + 1 = 6. When step S8 is completed, the process proceeds to steps S5, S6, and S7, where a reset signal is issued to the watchdog timer 20, and the watchdog timer 20 is reset. When the above interrupt processing is completed, the task C is executed as shown in FIG. 5, a task A having a high priority is activated in the middle of the task C, and the second interrupt processing is performed when the task A is completed. Be started. Since the interrupt count value was 6 in the first interrupt process, the determination in step S1 of the second interrupt process is YES, and the process proceeds to step S2. In step S2, the idle flag is set to 1
However, since the idle task has been executed before the first interrupt processing, the determination in step S2 is YES, the process proceeds to steps S3 and S4, the idle flag is changed from 1 to 0, and the interrupt is performed. Change the count value from 6 to 0.
Next, the process proceeds to steps S5, S6, and S7, where a reset signal is output to the watchdog timer 20, and the watchdog timer 20 is reset. Therefore, the count value of the watchdog timer 20 becomes 0. When the second interrupt processing is completed, the suspended processing of the task C is resumed, and when the task C is completed, the task B is activated. During the execution of task B, a third interrupt process is performed. In the third interrupt process, the determination in step S1 is NO, and in step S8, the interrupt counter is incremented, and the interrupt count value changes from 0 to 1. When step S8 ends, the process proceeds to steps S5, S6, and S7, where the watchdog timer 20 is reset, and the third interrupt process ends. Similarly, in the fourth interrupt, the process proceeds to step S8, where the interrupt count value is incremented from 1 to 2, and further, S5, S6, S5
Proceed to 7 to reset the watchdog timer 20.
In the next fifth interrupt processing, the interrupt count value is incremented from 2 to 3 in step S8, and the subsequent step S5
In S6 and S7, the watchdog timer 20 is reset. In the next sixth interrupt process, the interrupt count value is incremented from 3 to 4 in step S8, and
At 5, S6 and S7, the watchdog timer 20 is reset. When the sixth interrupt processing is completed, the idle task is executed, so that the idle flag is changed from 0 to 1 as shown in FIG. In the seventh interrupt process thereafter, the interrupt count value is incremented from 4 to 5, and in the eighth interrupt process, the interrupt count value is incremented from 5 to 6. The determination in step S1 of the next ninth interrupt processing is YES. In this case, since the interrupt count value was 6 in the eighth interrupt process, the determination in step S1 of the ninth interrupt process is YES. In the next step S3, it is determined whether the idle flag is 1. As described above, since the idle task is executed after the sixth interrupt processing and the idle flag is 1, the determination in step S3 is YES, and In the next step S3, the idle flag is changed from 1 to 0.
, And the interrupt count value is changed from 6 to 0 in step S4. As described above, when the idle task is being executed while the interrupt processing at regular time intervals is performed a plurality of times (six times in this embodiment), the count value of the watchdog timer 20 as shown in FIG. Is the set value (T
_R ), the CPU 10 is not reset.

FIGS. 7 and 8 show a case where the idle task is not executed during a plurality of interrupt processes after the interrupt process is performed at the timing (# 2), and the idle task is not executed. Therefore, 1 does not stand for the idle flag,
In each interruption process, only steps S1 → S2 in FIG. 3 are repeated. Even if the interrupt processing is repeatedly performed a plurality of times, steps S5 to S7 are not executed, and the reset signal cannot be output to the watchdog timer 20.
For this reason, as shown in FIG.
Count value increases and reaches the set value (T _R ).
A reset signal is output to 0 and the CPU 10 is reset.

As described above, according to the above embodiment, since the reset signal of the watchdog timer 20 is generated by the highest priority interrupt processing, the CPU 10 can execute the high priority task continuously even if the high priority task is continuously executed. It will not be reset frequently. In the above embodiment, the CPU 10 is reset when the idle task is not executed while the interrupt processing is performed a predetermined number of times.
There is no need to increase the hardware configuration, such as increasing the number of stages of the watchdog timer or separately providing a frequency divider.

[0022]

The present invention has the above-described configuration, and according to the present invention, without increasing the hardware configuration, the CP
This has the advantage that the CPU can be reliably reset when U becomes abnormal.

[Brief description of the drawings]

FIG. 1 is a block diagram of a traveling position display device provided with a runaway monitoring device according to the present invention.

FIG. 2 is an electric circuit diagram of a runaway monitoring device according to one embodiment of the present invention.

FIG. 3 is a flowchart of the embodiment.

FIG. 4 is a flowchart of the embodiment.

FIG. 5 is a diagram illustrating the operation of the embodiment.

FIG. 6 is a view showing a count value of a watchdog timer of the embodiment.

FIG. 7 is an operation explanatory diagram of the embodiment.

FIG. 8 is a diagram showing a count value of a watchdog timer of the embodiment.

FIG. 9 is a flowchart of a conventional runaway monitoring device.

FIG. 10 is a diagram illustrating the operation of a conventional example.

FIG. 11 is a diagram showing a count value of a watch dog timer of the conventional example.

FIG. 12 is an operation explanatory diagram of the conventional example.

FIG. 13 is a diagram showing a count value of a watchdog timer of the conventional example.

[Explanation of symbols]

 10 Central Processing Unit 19 Runaway Monitoring Circuit 20 Watchdog Timer 21 Clock Generator

Claims (1)

(57) [Claims] 1. A processing means for executing a plurality of processes in accordance with priorities, executing a highest priority interrupt process at predetermined time intervals, counting a clock signal output from a clock generator, and determining a count value. A watchdog timer that resets the processing means when a predetermined value is reached; an interrupt counter that counts the number of times of the interrupt processing; and a plurality of processes during which the interrupt counter counts a predetermined value. Determining means for determining whether or not the lowest priority processing has been executed; means for outputting a reset signal to the watchdog timer for each of the interrupt processing until the interrupt counter reaches a predetermined value; Means for resetting the interrupt counter when it is determined that the lowest priority processing is being executed when the interrupt counter reaches a predetermined value; and Means for prohibiting output of a reset signal to the watchdog timer when it is determined that the lowest priority processing has not been executed when the predetermined value has been reached. .