JP2775733B2 - Digital waveform signal generator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital waveform signal generator capable of setting an output frequency with high accuracy. [Prior Art] With the spread of digital ICs, inverter control circuits have also been digitized in terms of both cost reduction and stability. Hereinafter, a digital waveform signal generator used for the PWM inverter according to the present application will be described. Figure 2
FIG. 2 is a block circuit diagram for generating an ON / OFF signal of a main switch of a PWM inverter. In the figure, 1 is a clock pulse generator, 2 is a frequency divider, 3 is a division ratio setter,
4 is a counter, 5 is a table ROM, 6 is a multiplying D / A converter, 7 is a voltage commander, 8 is a triangular wave generator, 9 is a comparator, 10 is a green amplifier, 11, 12, and 13 are main circuits. In the diagram schematically shown, 11 is a smoothing capacitor, 12 is a main switch element, and 13 is a load, which is constituted by the connections shown in the figure. Of these,
The clock pulse generator 1, the frequency divider 2, the division ratio setter 3, the counter 4, the table ROM 5, the multiplying D / A converter 6, and the voltage commander 7 constitute a waveform signal generator. Next, the operation of this circuit will be described. ON of main switch element
The ON / OFF signal is obtained by comparing the output voltage command v with the frequency-controlled triangular wave (PWM triangular wave) outputted from the triangular wave generator 8 by the comparator 9, and the ON / OFF signal is greened by the green amplifier 10. It is amplified and supplied to the main switch element.
An output voltage command v is obtained by multiplying a digital quantity X corresponding to a normalized waveform signal by a voltage V commanded by a voltage command unit 7 corresponding to the amplitude of the output voltage command v using a D / A converter 6. I have obtained it for multiplying. A digital quantity X corresponding to a normalized waveform signal is obtained by dividing one cycle into time sections having a predetermined number N of equal time periods and determining a representative value (for example, a maximum value) of the waveform signal in each time section. Are stored in the table ROM 5 with an address signal, and data having an address signal equal to the currently input address signal is output as a digital quantity X. The address signal input to the table ROM 5 is generated by the counter 4. This counter 4 is reset to a sea where the count value exceeds N. That is, the rising of the input pulse to the counter 4 is at the time of address update, and the interval between the input pulses to the counter 4 is the address update pitch. An address update signal serving as an input pulse to the counter 4 is a reference clock signal (frequency
f _CLK ) is obtained by dividing the frequency by a frequency divider 2 having a variable dividing ratio. That is, the output voltage frequency can be controlled by increasing or decreasing the set value n of the frequency division ratio setting device 3. The output frequency f ₀ in this circuit is such that the address update pitch is
f _CLK / n, which is given by the following equation, considering that one cycle is divided into N equal parts in the table ROM and the representative value of the waveform signal in that time interval is stored. f ₀ = f _CLK / nN Further, the setting resolution Δf ₀ of the output frequency f ₀ by increasing / decreasing the set value n of the frequency division ratio setting device 3 is given by the following equation, considering that the set value n is a natural number. Given. Δf ₀ = f ₀ (n) −f ₀ (n + 1) = f ₀ / n + 1 That is, the setting resolution of the output frequency is a value substantially inversely proportional to the frequency division ratio n. [Problems to be Solved by the Invention] However, in the inverter, the output frequency of 1000 to
In many cases, a setting resolution of 1/2000 is required. For example, an inverter used for a controller for setting the resonance frequency of the vibrator corresponds to this case. Now, f ₀ = 200H
If z, N = 64 and n = 2048, the frequency f _CLK of the reference clock signal is 26.2 MHz from the above equation. This frequency is a value close to the upper limit of the operation speed of a general digital IC, and is not a frequency that can be adopted to obtain stable operation as a digital circuit. That is, there is a limit in increasing the value of the frequency of the reference clock signal in order to obtain a highly accurate output frequency resolution in terms of the operating frequency of a digital circuit that processes the signal. [Means for Solving the Problem] Then, what kind of means other than increasing the value of the frequency of the reference clock signal is available as a means for obtaining highly accurate output wave number resolution? The present invention proposes a means for increasing the setting resolution of the dividing ratio as this means.
That is, by adding a means for increasing or decreasing the set value of the frequency division ratio of one or two or more time sections to the conventional waveform signal generating apparatus, of the time sections obtained by dividing one cycle by an arbitrary number, When viewed as one whole cycle, the same effect as when the frequency division ratio is set at a resolution higher than a natural number is obtained. [Operation] By increasing the setting resolution of the division ratio, the resolution of the output frequency is increased without increasing the value of the frequency of the reference clock signal. Embodiment FIG. 1 is a circuit diagram when the invention is applied to a circuit for generating an ON / OFF signal of a main switch of a PWM inverter. In the figure, the same parts as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted. The frequency division ratio setting unit 3 is configured to be able to set up to the first place below the decimal point and to output the integer part and the decimal part separately. An adder 14 receives the output of the integer portion of the frequency division ratio setting device 3 and the output of the shift register 16, adds these, and outputs the result to the frequency frequency divider 2 as a frequency division ratio setting value. Reference numeral 15 denotes an interpolation table ROM, which stores data indicating which time section in one cycle the frequency division ratio is to be increased / decreased, in a form corresponding to the first digit below the decimal point. Reference numeral 16 denotes a shift register which outputs data of the interpolation table ROM 15 to the adder 14 at a predetermined timing one bit at a time. The configuration of the waveform output device of the present invention is obtained by adding the adder 14, the interpolation table ROM 15, and the shift register 16 to the configuration of the conventional waveform output device and modifying the frequency division ratio setting device 3 as described above. Hereinafter, the operation of the waveform output device in this configuration will be specifically described for the case where the waveform signal is a sine wave. One cycle is 64
Note that the sine wave is an equivalent waveform in each quadrant of the four quadrants, and divided into 16 time-segment groups for each quadrant, and each group is processed equivalently. Accordingly, the data handled by the present apparatus is 16 bits long in consideration that the data in the interpolation table ROM 15 is data in which each time interval corresponds to 1 bit. That is, the frequency division ratio setting device 3
It shall be set as a hexadecimal number. Due to the operability problem, in order to use decimal notation input, 10
A configuration may be adopted in which a conversion device for converting hexadecimal data to hexadecimal data is provided, but the following description is limited to processing as hexadecimal data. First, the frequency division ratio is set in the frequency division ratio setting unit 3 by a numerical value from the decimal point to the first place in the hexadecimal system. The data of the integer part of the hexadecimal data of the dividing ratio set by the dividing ratio setting unit 3 is one input of the adder 14. The data of the decimal part of the hexadecimal data of the division ratio is the interpolation table
The information is input to the ROM 15 as numerical value information of the first digit after the decimal point. The interpolation table ROM 15 stores 16 numerical values corresponding to 0 to 15 in the first digit after the decimal point. Each data is 16-bit length data as described above. The same bit as the numerical value of the first digit after the decimal point is set to 1 and the other data is set to 0, and 1 bit is possible in 16 bits Place them as evenly as possible. Specifically, the table data is as shown in FIG. The interpolation table ROM15 shifts the data corresponding to the first digit below the decimal point.
Output to 16. The shift register 16 updates a predetermined bit (MSB or L) when updating the output signal to the waveform signal corresponding to each time period.
After the data of (SB) is output to the adder 14, the data is shifted left or right in a predetermined direction. The adder 14 adds the integer part of the set value of the dividing ratio and the 1-bit data input from the shift register 16 and outputs the result to the frequency divider 2 as the dividing ratio of the frequency divider 2. When this operation is repeated 16 times, the setting of the division ratio of the time section for one quadrant is completed. At this time, the data in the shift register 16 becomes 0. Therefore, in order to set the frequency division ratio in the next quadrant and thereafter, the shift register 16 is prepared with 32 bits and has a bit length of 16 bits × 2. As a register, 16-bit data corresponding to the value of the first digit after the decimal point is moved between the two registers and used, or the setting of the division ratio in the time section of one quadrant is completed. It is necessary to newly output the data from the interpolation table ROM 15 to the shift register 16. By the repetition of the above, the setting of the division ratio of the time section for four quadrants is completed. Now, the numerical value of the first digit below the decimal point is M (0 ≦ M <16)
Then, the number of 1 bits in the time section of one quadrant is M, and the number of 1 bits in the time section of 4 quadrants is 4M. Since the number of time sections in one cycle is 64, if the frequency of the reference clock signal is f _CLK and the integer part of the set value of the dividing ratio is n ₁ , the cycle T of the waveform signal is given by the following equation. can get. _{T = (n 1 / f CLK} ) * (64-M) + ((n + 1) / f CLK) * 4M = (64 / f CLK) * (n 1 + M / 16) Thus, the output frequency f ₀ is expressed by the following equation Is obtained. _{f 0 = f CLK / {64} * [n 1 + M / 16]} By comparing this expression and f ₀ in the prior art, the frequency division ratio n corresponds to _{(n + M / 1 16)} , which is just, 1st decimal place
It can be seen that the division ratio is expressed in hexadecimal notation including the decimal place. That is, when the present apparatus is viewed in one cycle unit, it indicates that the division ratio in hexadecimal notation including the first decimal place is set, and the output frequency corresponding thereto is obtained. Next, consider the resolution of the output frequency of this device. From the above equation, setting resolution Delta] f ₀ of the output frequency f ₀ Considering that the set value of the division ratio can be set to a first position below the decimal point, is given by the following equation. Δf ₀ = f ₀ (M) −f ₀ (M + 1) = f ₀ / {16 * [n ₁ + (M + 1) / 16]} That is, the resolution of the output frequency is determined by the setting value of the dividing ratio.
It is inversely proportional to the value multiplied by 16. Since this set value is expressed in hexadecimal notation, multiplying the set value of the dividing ratio by 16 is equivalent to carrying up one digit. Here, comparing with the conventional technology, in the conventional technology, when f ₀ = 200 Hz and N = 64, the reference clock frequency f _{CLK was} 26.2 MHz with the output frequency resolution n = 2048. If the output frequency is expressed in hexadecimal, n = h “800”. Hereinafter, in the present device, since the decimal point can be set to the first place after the decimal point, n = h “80.0”. Even in this case, the resolution of the output frequency is equivalent. Because, as described above, the resolution of the output frequency is inversely proportional to the value obtained by multiplying the set value of the dividing ratio by 16 and, as a result, the resolution of the output frequency is almost n = 800 (n = 2048 in decimal notation). This is because the value is inversely proportional. Here, the prior art as well as f ₀ = 200 Hz, if the frequency f _CLK calculation of N = 64, n = h reference clock signal as a "80.0", 1.64MHz, and the resolution of the prior art the same output frequency prior It is obtained at a frequency f _CLK of the reference clock signal which is 1/16 of the frequency f _CLK of the reference clock signal of the technology. In this device, the division ratio of any time section of all time sections is set to 1
Since the resolution of the dividing ratio is increased by increasing the number, the waveform distortion will be considered. f _CLK = 1.64 MHz, N = 64, n
= If h "80.0", timed temporary section than n / f _CLK 78.
0 μsec, and the time limit of the temporary section when the division ratio of the time section is increased by 1 is 78.7 μsec from (n + 1) / f _CLK , and 0.7 μsec, that is, an error of 1/128 in the temporary section. Further, since the time sections in which the frequency division ratio is increased by 1 are considered so as to be evenly arranged in one cycle as much as possible, it is considered that there is no problem in waveform distortion. The third aspect of the present invention relates to the case where the waveform signal is a sine wave
Although the embodiment of the digital waveform signal generating apparatus described in the section has been described, various implementations of the apparatus can be considered based on the technical idea of the present invention. For example, in order to optimize the bit pattern data in correspondence with the waveform signal, it is obvious that the number of bits of the data is changed or other measures are taken. In this embodiment, only the hardware is used, but it is also possible to use software. That is, a program for storing and outputting a digital quantity X corresponding to a normalized waveform signal and a program for managing an interval for activating the digital quantity X are incorporated in a microcomputer, a predetermined interface is installed, and the two By combining these programs, the functions of the present apparatus can be realized. In this case, in order to make the present apparatus correspond to the waveform signal, only the program needs to be changed, and the change is easy. Further, since the operation speed of the microcomputer is slower than that of the digital IC unit, the technical idea of the present invention that can increase the accuracy of the output frequency without increasing the frequency of the reference clock signal is particularly effective. [Effect] The accuracy of the output frequency can be increased without increasing the operation speed of the digital waveform signal generator. Further, it is possible to create a high-resolution digital waveform signal generator which could not be created due to the limitation of the operating frequency in the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment in which the present invention is applied to a circuit for generating an ON / OFF signal of a main switch of a PWM type inverter, and FIG. O of the main switch of the inverter
FIG. 3 is a circuit diagram showing a conventional circuit for generating an N / OFF signal, and FIG. 3 is a diagram showing data stored in a table ROM in one embodiment of the present invention. 1 Clock pulse generator 2 Frequency divider 3 Frequency divider setting unit 4 Counter 5 Table ROM 6 Multiplying D / A converter 7 Voltage commander 14 Adder 15: Interpolation table ROM 16: Shift register

Claims (1)

(57) [Claims] Storage means 5 for storing a waveform representative value of each time section obtained by dividing the cycle of a waveform signal having a fixed cycle into a predetermined number of time sections having equal time periods; clock signal generating means 1 serving as a time reference; A frequency dividing ratio variable frequency divider 2 for dividing a signal to generate a pulse having a period equal to a time period of a time section, a frequency dividing ratio setting means 3 for setting a frequency dividing ratio of the frequency divider 2, A digital waveform signal generator comprising waveform output means for updating a waveform representative value output from the storage means at the time of rising of the pulse and outputting a waveform signal corresponding to each time section; The division ratio setting means 3 can output an integer part and a decimal part, and in a time interval corresponding to the output of the decimal part, adds a predetermined value to the output of the integer part to set the division ratio. Dividing ratio change hand to change A digital waveform signal generator comprising stages 14, 15, and 16. 2. The dividing ratio changing means makes each time section correspond to one bit, and the bit corresponding to the time section for changing the dividing ratio is 1 bit.
And a storage means 15 for storing a predetermined number of bit pattern data in which the other bits are 0, and a bit corresponding to a decimal output of the frequency division ratio setting means 3 among the bit pattern data stored in the storage means 15. A shift register 16 for inputting pattern data in advance from the storage means 15 and shifting the bit pattern data bit by bit when updating an output signal to a waveform signal corresponding to each time interval, and a predetermined bit of the shift register 16 2. The digital waveform signal generator according to claim 1, further comprising an adding means for adding data to a frequency division ratio at a timing earlier than the shift of the bit pattern data of the shift register when updating the output signal. 3. In the bit pattern data stored in the storage means 15, bits corresponding to the time interval for changing the frequency division ratio are arranged as evenly as possible, and at the same time, in the case of a waveform signal in which the same pattern repeats, the same bit is used. 3. The digital waveform signal generator according to claim 2, wherein bit pattern data having bits corresponding to the number of time intervals in the pattern is created, and the bit pattern data is used repeatedly.