JP2600410B2 - Video processing circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video processing circuit for enlarging and reducing a video in a vertical direction, and more particularly to a vertical address control when writing or reading a video memory.

BACKGROUND ART FIG. 4 is a block diagram of a conventional video processing circuit for enlarging or reducing a video. In the figure, (31) is a frequency divider for dividing the horizontal synchronizing signal HS, (32) is a vertical address counter, and (33) is a video storage unit.

The video storage unit (33) specifies a horizontal synchronization signal HS that forms one image by a vertical address, and assigns a predetermined number of dots of each horizontal synchronization signal HS, for example, 960 dots to each digital-to-digital converted dot in a horizontal address. Specified by.

When the image corresponding to the luminance signal stored in the video storage unit (33) is enlarged or compressed and displayed, the frequency divider (31) divides the horizontal synchronizing signal HS into 1 / ^2N. The divided signal is output as a count-up signal to a vertical address counter (32) that manages the vertical address of the video storage unit (33). The vertical address counter (32) counts up by the frequency-divided signal, and uses the count value as a vertical address.

The conventional video processing circuit uses a vertical address counter (32)
When writing the luminance signal in the vertical address of the video memory section (33) specified by is a reduction of only thinning of 1/2 ^N, reduction of only thinning of 1/2 ^N in the case of reading However, there has been a problem that arbitrary enlargement and reduction is impossible at all.

DISCLOSURE OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a video processing circuit capable of arbitrarily and easily enlarging and reducing a video.

According to one embodiment of the present invention, there is provided a video processing apparatus comprising: a phase locked loop (hereinafter, referred to as a PLL circuit) in which a vertical synchronization signal of a video signal is input to one phase comparison input;
The VCO signal output terminal of the circuit is connected to the input terminal, the output terminal is connected to the other phase comparison input terminal of the PLL circuit, and an arbitrary frequency division ratio N can be set, and the VCO signal is divided by 1 / N. A vertical address counter that counts the VCO signal of the PLL circuit, and a vertical address storage unit that stores the count value of the vertical address counter in synchronization with the input of the horizontal synchronization signal. By causing the stored count value to be read or written to the video storage means as a vertical address, vertical expansion or reduction can be performed according to the difference between the update cycle of the vertical address counter and the update cycle of the vertical address storage unit. Do. Further, a storage unit for storing the frequency division ratio N is provided in the frequency divider, and the storage unit is configured to be writable by an external information processing device.

A video processing device according to another aspect of the present invention includes a video storage unit that stores a digital video signal, a phase synchronization with a vertical synchronization signal included in the video signal, and an arbitrarily set integer multiple of the vertical synchronization signal. Means for generating a signal, a vertical address counter for counting an integer multiple of the signal, and means for storing a count value of the vertical address counter in synchronization with a horizontal synchronization signal included in the video signal. An image is enlarged or reduced by writing a video signal into the video storage means using the count value as a vertical address.

According to still another aspect of the present invention, there is provided a video processing device comprising: a video storage unit for storing a digital video signal; a vertical synchronization signal included in the video signal being in phase with an arbitrary multiple of the vertical synchronization signal; , A vertical address counter for counting an integer multiple of this signal, and a means for storing the count value of the vertical address counter in synchronization with a horizontal synchronization signal included in the video signal. The image is enlarged or reduced by reading the video signal from the video storage means using the counted value as a vertical address.

Therefore, according to the present invention, since the clock frequency of the video storage unit is adjusted by using the PLL circuit or a circuit corresponding thereto, very inexpensive and stable characteristics can be obtained, and the frequency of the composite video signal can be obtained. Because it is not affected by the above, it can cope with various types of composite video signals.

Furthermore, since enlargement and reduction of an image can be easily adjusted with an external CPU, a personal computer, or the like, it is extremely useful in the digital image field in the future.

In addition, the present invention can be easily applied to a video digitizing unit for writing a video, displaying a video for reading, and the like, and is an indispensable invention for a video processing circuit of a video personal computer, an intelligent terminal, etc. which will be widely used in the future. .

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of the video processing circuit of the present invention, FIG. 2 is a timing chart showing the operation of the video processing circuit shown in FIG. 1, and FIGS. FIG. 4 is an explanatory diagram showing a relationship between a video storage unit and a video, and FIG. 4 is a block diagram of a conventional video processing circuit.

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a video processing circuit according to one embodiment of the present invention. In the figure, reference numeral (11) denotes a synchronization signal separator for separating the vertical synchronization signal VS and the horizontal synchronization signal HS from the composite video signal CS. Reference numeral (12) denotes a PLL circuit, which includes a phase comparator (13), a low-pass filter (14), and a VCO (15). (16) is a frequency divider, and (17) is a storage unit.
(18) is a vertical address counter, (19) is a vertical address storage unit, and (20) is a video storage unit. (21) is an external CPU or personal computer (hereinafter simply referred to as CPU), and (2)
2) is a CPU bus.

Next, the operation of the video processing circuit configured as described above will be described. Here, an example will be described in which a certain value, for example, an A value is stored in the storage unit (17) from the CPU (21) via the CPU bus (22).

First, the composite video signal CS is input to the synchronizing signal separator (11), where the vertical synchronizing signal VS, which has been synchronizing and separated, is output to the PLL circuit (1).
The phase comparison input A of 2) is entered. At this time, the vertical synchronization signal VS resets the vertical address counter (18) and the vertical address storage unit (19) of the video storage unit (20),
Further, the value A stored in the storage unit (17) is read into the frequency divider (16).

Next, the clock signal CK output from the VCO (15) incorporated in the PLL circuit (12) is supplied to the vertical address counter () regardless of the horizontal synchronization signal HS cycle-separated by the synchronization signal separator (11). 18) Count up. The frequency divider (16) counts up the read A value every time the clock signal CK is input. Divider (16) is A
When counting up to the value, a carrier signal is generated from the frequency divider (16) and sent to the phase comparison input B of the PLL circuit (12).

Therefore, the phase comparator (13) obtains a phase difference between the phase comparison input A and the phase comparison input B, and the phase difference is sent to the low-pass filter (14) to be converted into a voltage. In the VCO (15), the clock frequency is changed according to the converted voltage, and the process is repeated until the phase difference between the phase comparison input A and the phase comparison input B is minimized, that is, a locked state is generally reached.

Then, during the vertical synchronization period obtained in this locked state, reading from the video storage unit (20) according to the A value stored in the storage unit (17), that is, information corresponding to the vertical resolution, and the video storage unit (20) ) Is written.

Also, the frequency divider (16) is simply an up counter,
A signal obtained by comparing with the value from the storage unit (17) and finding a match can be used as a carrier signal output from the frequency divider (16).

FIG. 2 is a time chart showing an operation when accessing the video storage section (20) after the PLL circuit (12) is locked, and the operation will be described below based on this time chart.

First, the frequency divider (16) and the vertical address counter (18) are reset by the fall of the vertical synchronization signal VS, and the vertical synchronization signal VS is input to the phase comparison input A of the PLL circuit (12) at the rising timing. You. Further, a phase comparison signal PC obtained by dividing the frequency of the VCO signal sent from the VCO (15) by the divider (16) is sent to the phase comparison input B of the PLL unit (12).
The state where the rising of the vertical synchronizing signal VS and the rising of the phase comparison signal PC are input indicates that the PLL circuit (12) is locked.

Then, the rising edge of the VCO signal causes the vertical address counter (18) to count up asynchronously with the horizontal synchronization signal HS. However, in this state, the vertical address counter (1
8) is only for counting up, the count value of the vertical address counter (18) is stored in the vertical address storage unit (19) by the fall of the horizontal synchronization signal HS, and the video storage unit (20) is stored based on the vertical address. The writing of video data or the reading of video data is performed on the data portion of.

Note that the rising and falling timings of each signal in FIG. 2 are merely examples, and the present invention is not limited to this example.
It goes without saying that it will be different as appropriate according to the characteristics of the element to which it is applied.

By changing the A value of the storage section (17), the output frequency of the PLL circuit (12), that is, the frequency of the VCO signal changes, and therefore the count value of the vertical address counter (18) also changes. 20) The interval of vertical thinning when accessing can be adjusted arbitrarily. Therefore, the video signal can be arbitrarily enlarged or reduced in the vertical direction.

FIG. 3 is an explanatory diagram thereof, where FIG. 3A shows the contents of the video data in the video storage unit (20). For example, if the frequency of the VCO signal is set to be twice that of the horizontal synchronization signal HS, the video storage unit (2) shown in FIG.
The video data in the vertical direction (0) is read out every other video data. For this reason, as shown in FIG. 3B, video data thinned out line by line in the vertical direction is obtained, thereby obtaining a video reduced in half in the vertical direction.

In order to obtain an image enlarged twice, if the frequency of the VCO signal is set to be half of the horizontal synchronizing signal HS, the same video data is obtained adjacently in the vertical direction. An image enlarged twice in the vertical direction is obtained.
In this case, contrary to the above, FIG. 3 (b) shows the contents of the video data in the video storage unit (20), and FIG. 3 (a) shows the read video.

FIG. 3 (b) shows the contents of the video signal, in which the video is reduced in half in the vertical direction and the video storage unit (2
When writing to (0), the frequency of the VCO signal is set to be twice the horizontal synchronization signal HS. By reading the video signal at every other vertical address, the video data in the vertical direction is thinned out and reduced by a factor of 1/2 in the vertical direction, and the video data as shown in FIG. Storage unit (2
0).

The frequency of the VCO signal that defines the resolution in the vertical direction of the video can be arbitrarily set by the A value stored in the storage unit (17). Therefore, any enlargement or reduction in the vertical direction of the video can be performed. You can do it freely.

INDUSTRIAL APPLICABILITY The present invention can be applied to a video digitizing unit for writing a video storage unit, a video display for reading, and the like. It is indispensable for the circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04N 3/223 H04N 3/223 5/04 5/04 Z

Claims (5)

(57) [Claims] 1. A PLL circuit in which a vertical synchronizing signal of a video signal is input to one phase comparison input, a VCO signal output terminal of the PLL circuit is connected to an input terminal, and an output terminal is connected to the other phase of the PLL circuit. A frequency divider connected to the comparison input terminal and configured to be able to set an arbitrary frequency division ratio N, dividing the VCO signal by 1 / N; a vertical address counter for counting the VCO signal of the PLL circuit; A vertical address storage unit that stores the count value of the address counter in synchronization with the input of the horizontal synchronization signal, and reads or writes the video storage unit using the count value stored in the vertical address storage unit as a vertical address. The video processing apparatus performs enlargement or reduction in the vertical direction according to a difference between the update cycle of the vertical address counter and the update cycle of the vertical address storage unit. 2. The frequency divider according to claim 1, wherein a storage unit for storing the frequency division ratio N is provided in the frequency divider.
The video processing circuit according to the item. 3. The video processing circuit according to claim 2, wherein the storage unit for the frequency division ratio N has a structure that can be written by an external information processing device. 4. A video storage means for storing a digital video signal, and means for generating a signal which is in phase with a vertical synchronization signal included in the video signal and which is an arbitrary multiple of the vertical synchronization signal. A vertical address counter for counting the signal of the integral multiple, and means for storing a count value of the vertical address counter in synchronization with a horizontal synchronizing signal included in the video signal. An image processing apparatus for enlarging or reducing an image by writing the image signal in the image storage unit as a direction address. 5. A video storage means for storing a digital video signal, and means for generating a signal which is in phase with a vertical synchronizing signal included in the video signal and is arbitrarily set to an integer multiple of the vertical synchronizing signal. A vertical address counter for counting the signal of the integral multiple, and means for storing a count value of the vertical address counter in synchronization with a horizontal synchronizing signal included in the video signal. An image processing apparatus for enlarging or reducing an image by reading the video signal from the video storage means as a direction address.