JP2693629B2 - Register file - Google Patents

Description

The present invention relates to a register file used in a microprocessor or the like.

[Conventional technology]

Microprocessors are becoming ever faster due to the demands of the times. As one of the techniques for increasing the speed of a microprocessor, a register file having a configuration called a register window has been proposed. This is to divide the register file into multiple windows and switch the windows each time branching to or returning from the subroutine, eliminating the saving of register data to the memory at the time of branching the subroutine and accelerating the processing of the microprocessor. It is a thing. In addition, the registers between the windows are partially overlapped, and the data can be transferred between the subroutines in the overlapped portions. In the register file having such a configuration, even the same address signal is different from the real address on the register depending on the window value. Therefore, in order to make the addresses correspond to the registers in a one-to-one correspondence, the address conversion as described later is performed.

FIG. 4 is a block diagram showing the structure of a register file using such address conversion. In the figure, the address conversion circuit 31 has an address signal Ai and a window signal Wi.
Is input, and the address is converted and given to the address decoder 32 as an address conversion signal Bi as described later. The address decoder 32 decodes this address signal, and its output is connected to the register array 33 via the parallel word line Wr. The register array 33 is composed of a register block 36 including a register composed of a large number of memory cells 34, a precharge circuit 35, and an input / output circuit 37. For example, if you have 8 windows and 1 window
32 registers are allocated, 8 registers of each window are common to all windows, 8 registers are common to previous window, other 8 registers are 1
The number of registers is 136 if it is common to the register window of the destination. The register block 36 has a memory cell having a capacity corresponding to this register, and the word line
The register is selected by Wr and Ww. When writing data to the register array 33, an address signal Ci and a window signal Xi, which are externally applied, are applied to the address conversion circuit 38. The address conversion circuit 38 is the address conversion circuit 31.
At the same time, the address conversion signal Di is generated and a predetermined register in the register block 36 is selected via the address decoder 39.

Now, in the address conversion circuit 31, the address signal Ai =
8. When the window signal Wi = 2, the address signal Ai = 24, and the window signal Wi = 1, the conversion formula when the address conversion signal Bi = 48 is assigned is shown by the following formula.

Bi = MOD [Ai + 8 + Wi × 16] FIG. 5 is a conventional address assignment diagram, and FIG. 6 is a circuit diagram showing an example of a conventional address conversion circuit 31. In the figure, the address signal Ai is input to y0 to y4, the window signal is input to x0 to x2, and the address conversion signal Bi is output as z0 to z7.

Next, the operation of this device will be described. In the read operation, the address signal Ai from the outside and the window signal Wi designating the window are input to the address conversion circuit 31,
The address conversion shown in the figure is performed and becomes the address conversion signal Bi. The address signal conversion Bi is decoded by the address decoder 32, and the word line Wr corresponding to the address conversion signal Bi
Drive. The word line Wr controls the memory cell 34 of the register block 36 in the register array 33, and discharges the read bit line Br precharged by the precharge circuit 35 to read the data in the memory cell 34 as a read bit. Output to line Br. Next, the data on the read bit line Br is input to the input / output circuit 37, and the data in the memory cell 34 is output from the input / output circuit 37 to the outside.

In the write operation, the address signal Ci is externally input to the address conversion circuit 38 and converted into an address in the same manner as in FIG. 5 to become the address conversion signal Di. The address conversion signal Di is decoded by the address decoder 39 and drives the word line Ww corresponding to the address conversion signal Di. Write data input from the outside is input to the input / output circuit 37 and output to the write bit line Bw. The word line Ww activates the memory cell 34 of the register block 36 and the data of the write bit line Bw is written in the memory cell 34 of a predetermined register.

[Problems to be solved by the invention]

When address conversion is performed in such a conventional register file, Ai is a 5-bit signal because it is necessary to select 32 register units, and Wi is 3 because it is necessary to select 8 windows. It becomes a bit signal. In the address conversion circuit 31, for example, Ai = 1
When 5, Wi = 7, the following conversion is performed.

When Ai = 31 and Wi = 7, the following conversion is performed.

Therefore, the carry signal of the 4th bit is successively transmitted to the upper bits. That is, in the calculation of +8, the lower 3 bits do not change, but the upper 4 bits change due to carry from the lower side as shown in the figure, and a 4-bit adder is required for calculating Bi. It can be seen that in the address translation device shown in FIG. 6, z6 is affected by the carry signal of the operation result of y3 and y4. For this reason, there is a problem that the address conversion is delayed due to the delay of the carry signal and the access time is delayed.

The present invention has been made in view of such conventional problems, and provides a register file in which the address conversion time is shortened by optimizing the address allocation, and as a result, the access time is shortened. Is a technical issue.

[Means for solving the problem]

In the invention of claim 1 of the present application, the number of windows is W, the window number is Wi, and the number of registers allocated per window is 2 ^N (N ≧ 3, N is a natural number). A register file in which the number is 2 ^(N-1) and the number of registers that can be accessed in common in each window is 2 ^(N-2) .It is a register block having multiple register areas and data connected to the register blocks. When the input / output circuit for inputting, the address signal given from the outside is Ai, and the window number is Wi, the address of the register area of the register block is MOD [{Wi × 2 ^(N-1) + A
i-2 ^(N-2) } / {2 ^ (<< log ₂ W >> + N-1)}], and the address assignment of the memory cell common to each window is 2 ^.
An address conversion circuit that outputs an address conversion signal that is (<< log ₂ W >> + N-1) + Ai, and an address decoder that decodes the output of the address conversion circuit and selects the register area of the register block are provided. It is a feature.

(Y = << X >> represents the maximum integer that satisfies Y <X. 2 ^ X
Represents 2 ^X. MOD (Y / X) represents the surplus of Y by X. In the invention of claim 2 of the present application, the number of windows is W, the window number is Wi, and the number of registers allocated per window is 2 ^N (N ≧ 3, N is a natural number), and the windows are overlapped. A register file in which the number of registers is 2 ^(N-1) and the number of registers that can be accessed in common in each window is 2 ^(N-2) .This register file has multiple register blocks and multiple registers. When the input / output circuit connected to the block and inputting data, the address signal given from the outside is Ai and the window number is Wi, the address of the register area of the register block is MOD [{Wi
× 2 ^(N-1) + Ai-2 ^(N-2) } / {2 ^ (<< log ₂ W >> + N-
1)}], and an address conversion circuit that outputs an address conversion signal in which the address allocation of the memory cells common to each window is 2 ^ (<< log ₂ W >> + N−1) + Ai, and N− of the address conversion signals. An address decoder for decoding a 2-bit lower address conversion signal; and block data for decoding the remaining upper bits of the address conversion signal and selecting an input / output circuit connected to each register block. It is a feature.

[Action]

According to the inventions of claims 1 and 2 having such features, the address allocation of the registers of the register window is performed by the address conversion circuit MOD [{Wi × 2 ^(N-1) + Ai-2
^(N-2) } / {2 ^ (<< log ₂ W >> + N-1)}].
In this way, when the value of Ai is smaller than 2 ^(N-2) during address translation, it becomes a register common to all windows. The conversion formula in that case is 2 ^ (<< log ₂ W >> + N-1) + Ai, and 2 ^ (<< l
Since og ₂ W >> + N-1) has a digit larger than Ai, carry does not occur and carry delay does not occur.

When the value of Ai is larger than 2 ^(N-2), Ai-2 ^(N-2) does not generate a borrow, so conversion can be performed only by inverting the bit corresponding to 2 ^(N-2) . The remainder is taken to mask the carry signal to the upper bits.

In addition, since address signals of N-2 bits or less do not change even if the address is converted, 2 ^(N-2) memory cells are used as one block, N-2 bits are used for register access, and upper bits are used for input. The output circuit is selected. In this way, the address translation time is not added to the access time and high speed access is possible.

〔Example〕

FIG. 1 is a block diagram of an embodiment of a register file according to the present invention. It is assumed that the register file of this embodiment has eight windows w0 to w7 and 32 registers are allocated to each window. Register array
It consists of 136 registers, and one register block consists of 8 registers. Address conversion circuit 11
Outputs the address select true symbol Br and the block select signal Sr based on the address signal Ai and the window signal Wi, and the lower 3 bits are given to the address decoder 12 as they are. The address decoder 12 decodes this 3-bit address, and its output end is connected to a plurality of register blocks 14 in the register array 13 via the word line Wr. Register block 14 is 8
Each register is composed of 17 register blocks 14a to 14q as one block. As shown in the figure, each register block has a precharge circuit 15 that keeps the potential of the bit line Br high beforehand in order to speed up the operation of the memory.
And a memory cell 16 corresponding to the capacity of the register. Further, each register block 14a is provided in the register array 13.
Input / output circuits 17a to 17q corresponding to 14q to 14q are provided. The block select signal Sr is applied to the block decoder 18, and the 5-bit block select signal is decoded to select one of the input / output circuits 17a to 17q.

When writing data, the address signal Ci and the window signal Xi are given to the address conversion circuit 19. The address conversion circuit 19 outputs the same signal as the address conversion circuit 11, and is supplied to the address decoder 20. The address decoder 20 fully decodes this signal to activate the word line Ww connected to the memory cell of each register block.

FIG. 2 shows an example of address allocation according to this embodiment. As shown in this figure, register address "00" ~
The register of "07" is the register where window w0 and window w7 overlap, register address "08" ~
Registers of "15" are unique to window w0, registers of register addresses "16" to "23" are windows.
Registers such that w0 and window w1 overlap, and the registers with register addresses "128" to "135" are common to each window w0 to w7. An example of the address conversion circuit 11 for allocating such register addresses is shown in FIG. In this figure, the lower 3 bits y0 to y2 of the input address signal Ai are given as they are to the address decoder 12 as the address select signal Br, and the upper 2 bits y3 and y4 of the address signal Ai and the 3-bit input signal of the window signal Wi are input. The addresses are exchanged by x0 to xi, and the outputs z3 to z7 of the block select signal Sr are used as signals for selecting the input / output circuits 17a to 17q. In this case, the address conversion signal Bi of the address conversion circuit 11 is given by the following equation.

Bi = MOD [{Wi × 16 + Ai-8} / 128] Next, the operation according to this embodiment will be described. First, in the read operation, the address signal Ai and the window signal Wi input from the outside are input to the address conversion circuit 11, but since the lower 3 bits of the address signal Ai do not change even by the address conversion, they are input to the address decoder 12 as they are. . The address decoder 12 selects a register address corresponding to the lower 3 bits of the address signal Ai, and the respective register blocks 14 in the register array 13 via the word line Wr.
It controls the memory cells 16 of a to 14q. Then, by discharging the bit line Br precharged by the precharge circuit 15 of each register block 14, the data of the memory cell 16 is output to the bit line Br.
The data output to the bit line Br is input to the input / output circuits 17a to 17q. The output of the address conversion circuit 11 is also given to the block decoder 18 as a block select signal Sr, and is decoded and given to the input / output circuits 17a to 17q, so that one input / output circuit is selected and data is output to the outside. To be done.

Here, the operation of the address conversion circuit 11 will be described.
The address signal Ai is input as y0 to y4, the window signal Wi is input as x0 to x2, and the converted address is
It is output as z0 to z7.

(A) When the address signal Ai is 31 and Wi is 7, the address conversion circuit 11 performs the following address conversion.

(B) When Ai = 23 and Wi = 7, the following address calculation is performed.

Further, when the upper 2 bits 3y and y4 of the address signal Ai are both 0, a common address is selected for each register window in the address allocation diagram shown in FIG. 2, and therefore the NAND circuit 21 shown in FIG. By the output of, z7 becomes 1 and a common register in the register window is selected.

(C) When Ai = 7, the following address calculation is performed.

In this way, since no carry is generated in the upper 3 bits from the lower side during address conversion, the upper address can be converted by using a 3-bit adder as shown in the address conversion circuit 11 in FIG. . Further, in the circuit of FIG. 3, when the address signal bits y3 and y4 are "0", the NAND circuit 21
Therefore, z7 becomes "1", but since the carry signal of the operation result does not affect z6, the circuit becomes smaller than the case where the conventional 4-bit adder shown in FIG. 6 is used. High-speed conversion is possible.

Further, in the write operation, the address signal Ci and the window signal Xi are externally input to the address conversion circuit 19, the address conversion signal Di converted from the address conversion circuit 19 is input to the address decoder 20, and the input signal of the address decoder 20 is input. Full decoding is performed to drive the word line Ww corresponding to the address conversion signal Di. Data is externally input / output circuit 17a of each of the register blocks 14a to 14q in the register array 13.
It is input to ~ 17q and outputs data to the bit line Bw of each register block. One memory cell 16 of the register block is controlled by the word line Ww and written in the memory cell 16 of the specific register block.

For this reason, we have 8 windows and one window
When 32 registers are allocated, in the conventional example, a 4-bit adder is needed because +8 is included in the conversion formula, but 3 bits out of 5 bits of the address signal Ai change even after address conversion. Therefore, by configuring one block of registers with eight registers, the register file of this embodiment can perform address conversion using a 3-bit adder. Address conversion can be speeded up, and register file access can be speeded up. Further, by selecting the register by the remaining 2 bits and the window signal Wi, the address conversion time is not added to the access time, so that high speed access becomes possible.

Although the present invention is applied to the read side address in the present embodiment, it can be applied to the write side.

Further, in this embodiment, the register common to each window is assigned to the minimum side of the address signal Ai, but even if it is assigned to the maximum side, the same effect can be obtained by inverting the address signals.

〔The invention's effect〕

As described in detail above, according to the present invention, the address signal from the outside is Ai, the window number is W, the window number is Wi, and the number of registers allocated per window is 2 ^N.
(N ≧ 3, N is a natural number), the number of overlapping registers in each window is 2 ^(N-1), and the number of accessible registers common to each window is 2 ^(N-2). ,
Assign the address of the memory cell to MOD [{Wi × 2 ^(N-1) + A
i-2 ^(N-2) } / {2 ^ (<< log ₂ W >> + N-1)}], and the address assignment of the memory cell common to each window is 2 ^.
(<< log ₂ W >> + N-1) + Ai.
In this way, N- of the address signal Ai is obtained by address conversion
Carrying from one bit or less can be eliminated, and the speed can be increased.

Further, according to the present invention, the address is converted and the register is accessed by accessing the register by N-2 bits of the address signal which is not translated at the time of address translation and selecting the data from the register by the output of the address translation circuit. It can be executed in parallel, resulting in faster register file access.

[Brief description of the drawings]

FIG. 1 is a block diagram of a register file according to an embodiment of the present invention, FIG. 2 is an address allocation diagram of the register file of the present embodiment, FIG. 3 is a circuit diagram of an address conversion circuit in the present embodiment, and FIG. Is a block diagram of an example of a conventional register file, FIG. 5 is an address allocation diagram of the conventional register file, and FIG. 6 is a circuit diagram of an address conversion circuit of the conventional register file. 11,19 ...... Address conversion circuit, 12,20 ...... Address decoder, 13 ...... Register array, 14a to 14q ...... Register block, 15 ...... Precharge circuit, 16 ...... Memory cell, 17
a to 17q …… I / O circuit, 18 …… Block decoder.

Claims (2)

(57) [Claims] 1. The number of windows is W, the window number is Wi,
The number of registers allocated per window is 2 ^N (N ≧ 3,
N is a natural number) and the number of registers that overlap each other in each window is 2 ^(N-1) , and the number of registers that can be accessed in common in each window is 2 ^(N-2) . When a register block having a plurality of register areas, an input / output circuit connected to the register block for inputting data, an address signal given from the outside is Ai, and a window number is Wi, the address of the register area of the register block is MOD [{Wi × 2 ^(N-1) + Ai-2 ^(N-2) } / {2 ^
(<< log ₂ W >> + N-1)}], and the address allocation of the register area common to each window is 2 ^ (<< log ₂ W >> + N
-1) An address conversion circuit that outputs an address conversion signal of + Ai, and an address decoder that decodes the output of the address conversion circuit and selects the register area of the register block. . (Y = << X >> represents the maximum integer that satisfies Y <X. 2 ^ X
Represents 2 ^X. MOD (Y / X) represents the remainder of Y in X. ) 2. The number of windows is W, the window number is Wi,
The number of registers allocated per window is 2 ^N (N ≧ 3,
N is a natural number) and the number of registers that overlap each other in each window is 2 ^(N-1) , and the number of registers that can be accessed in common in each window is 2 ^(N-2) . If a plurality of register blocks having a plurality of register areas, an input / output circuit connected to each of the register blocks and inputting data, an externally applied address signal is Ai, and a window number is Wi, the register areas of the register blocks The address of MOD [{Wi × 2 ^(N-1) + Ai-2 ^(N-2) } / {2 ^
(<< log ₂ W >> + N-1)}], and the address allocation of the memory cell common to each window is 2 ^ (<< log ₂ W >> + N-
1) An address conversion circuit that outputs an address conversion signal of + Ai, an address decoder that decodes an N-2 bit lower address conversion signal of the address conversion signal, and a remaining upper bit of the address conversion signal. A block decoder for decoding and selecting an input / output circuit connected to each of the register blocks.