KR100187493B1 - Internal address generating method of 3 directional communicating systoric structured pipelined memory - Google Patents

Abstract

The present invention introduces the concept of pipeline to memory address decoding, and divides the entire memory block into several smaller memory blocks to improve the data output of the entire memory. It relates to an internal address generating method.

The upper decoder partially decodes the entire input address to generate brow, bcol, and sel_blk signals for selecting each sub memory block. Each row and column delay buffer uses the brow and bcol signals to determine whether valid data moves in the diagonal direction starting from the adjacent sub memory block. The sel_blk signal determines which block is selected on the diagonal selected using the brow and bcol signals.

Description

Internal address generation method of pipelined memory of three-way communication structure

1 is a block diagram of an entire memory having a 4 × 4 sub memory block,

2 is a block diagram of a higher decoder.

The present invention relates to a VLSI of a pipelined memory architecture using a systolic structure. In particular, the present invention relates to a Systolic Pipelined Memory Architecture (VLSI) that performs three-way communication to reduce the delay for initial data and to obtain a high output data amount. The present invention relates to a method of generating an internal address.

Conventionally, the entire memory block is divided into several small sub-memory blocks and a decoder block for generating internal addresses, and each block communicates only with adjacent blocks in the vertical or horizontal direction, thereby reducing a slight time delay for initial data. A pipelined memory architecture and a method of generating internal addresses have been proposed in which a two-way communication is performed, which always yields a constant amount of output data regardless of memory capacity. However, such a conventional two-way communication structure has a problem that it takes a lot of time for address decoding and slow data access because each memory block can communicate only with adjacent blocks in the vertical or horizontal direction.

The present invention minimizes the connection time delay and reduces the time required to decode the address in each pipeline stage of the pipelined memory, so that the entire system operating frequency is reduced to the access speed of only one sub-memory block regardless of the number of blocks. It is an object of the present invention to provide a method for generating an internal address of a systolic pipelined memory of three-way communication that can improve data access speed by using a determinant.

In the method of generating an internal address of the VLSI according to the present invention, a row delay buffer selection signal brow, a column delay beeper selection signal bcol for selecting each sub memory block by partially decoding the entire input address input to the upper decoder, and Generating a signal sel_blk indicating a pipeline depth between the sub-memory block to be selected and the higher decoder; Determining whether valid data moves in a diagonal direction starting from an adjacent sub memory block by using a row delay buffer selection signal brow and a column delay buffer selection signal bcol in each row and column delay buffer; And generating an address for the selection block on the selected diagonal line using the row delay buffer selection signal brow, the column delay buffer selection signal bcol, and the pipeline depth signal sel_blk.

Systolic pipelined memory with three-way communication has the following characteristics:

First, the address decoding is divided into three stages using a hierarchical structure.

Second, it divides into the same number of small sub-memory blocks in the vertical and horizontal directions.

Third, connect each stage with a pipeline.

Fourth, the decoder block and the memory blocks only communicate with adjacent small memory blurs in the vertical, horizontal, and diagonal directions.

The total memory is divided into five devices: upper decoder, row delay buffer, column delay buffer, sub memory block, and output buffer. Each part always plays its own role independently and communicates only with neighboring devices.

FIG. 1 shows a block of the entire memory and a communication method between the respective blocks using 4X4 sub memory blocks as an example. Each block is connected to the pipeline by a register. In FIG. 1, the address decoding method in each sub memory block is the same as the conventional memory structure.

FIG. 2 shows the details of the higher decoder in the overall memory structure of FIG. The upper decoder determines whether the data is valid based on the input data valid signal, and partially decodes the address of the entire memory block to generate various control signals related to the sub memory block selection and the data flow. The upper 4 bits of the address coming into the input are decoded by the controller and the adder through a comparator, so that a row delay buffer selection signal (hereinafter referred to as brow) and a column delay buffer selection signal (hereinafter referred to as bcol) for selecting each sub-memory block. Then, a signal representing the pipeline depth between the sub-memory block to be selected and the upper decoder (hereinafter referred to as sel_blk) is generated, and the lower bits of the input address representing the address value in each sub-memory block are the lower row delay buffer and the column delay. Passed directly to the buffer. The brow and bcol signals need to select 16 sub-memory blocks independently in order to determine which diagonal blocks are selected in the sub-memory block arrangement as in Fig. 1, so the upper 4 bits of the input address are needed and the highest 2 The bit selects the sub memory block in the column direction and the remaining two bits select the sub memory block in the row direction. sel_blk selects one of the sub-memory blocks on each diagonal line selected by brow and bcol.

The row delay buffer and the column delay buffer move in a diagonal direction starting from the adjacent row of the row (column) delay buffer and the adjacent sub memory block in the adjacent sub memory block according to the input brow, bcol, and sel_blk signal values. A signal indicating whether data is valid (hereinafter referred to as vadd_row (vadd_col)) is transmitted, and a control signal of an upper decoder is transmitted to an adjacent next row delay buffer or column delay buffer. The row delay buffer has the same structure as the column delay buffer except that there is a subtractor. The subtractor selects only one of the sub-memory blocks on the diagonal line so that the sel_blk signal representing the minimum path from the upper decoder to the sub-memory block to be selected is zero in the block to be selected.

Each sub memory block selection principle and control signal value are as follows.

In the comparator of the higher decoder, if you find the difference between two upper bits of the input address (each higher bit is equal to the input of a smaller decoder inside the upper decoder), you can see the position of the diagonal where the block you want to select is located. The controller generates brow and bcol signals. In the adder, the larger value of the two upper bits shows how many pipeline stages are selected from the higher decoder.

Address [n-1: n-2]-If address [n-3: n-4] = 0, then the comparator's role

bcol = address [n-1: n-2]-address [n-3: n-4] + 1; Controller role

brow = 1; Controller role

sel_blk = address [n-1: n-2] + 1; The role of the adder

Otherwise,

brow = address [n-3: n-4]-address [n-1: n-2] + 1; Controller role

bcol = 1; Controller role

sel_blk = address [n-3: n-4] + 1; The role of the adder

The control signal for selecting the sub memory block uses the above algorithm.

The upper decoder transfers the row address of brow, sel_blk and the sub memory block to the row delay buffer using the above algorithm, and transfers the bcol signal, the column address of the sub memory block, and the data for the memory write operation to the column delay buffer.

In the above algorithm, all blocks located on or above the main diagonal of the sub-memory block array are all browsed to select the row delay buffer of one row and the column delay buffer at which bcol is the difference between the two upper addresses. It is necessary to decrease the value of sel_blk by 1 for each step among sub-memory blocks located diagonally starting from a block perpendicular to the buffer. For example, the sub memory 34 is selected with control signals brow = 1, bcol = 2 and sel_blk = 4 of the higher decoder. The devices flashed in FIG. 1 have values of devices through which valid signals have passed to select this block and control signals for selecting this block. In contrast, the blocks below the diagonal cause bcol to select the row delay buffer of one column and the row delay buffer at which the brow corresponds to the address difference, and the diagonal direction starts from the block adjacent to this row delay buffer. The position of selects one block from the sub memory blocks by using the sel_blk value. Set to the minimum path value to be selected by sel_blk. Table 1 shows the combinations of the brow, bcol, and sel_blk signals for selecting each memory block when the sub memory block is composed of 4 × 4.

[Table 1] Control signal values for sub memory block selection

When one sub memory block is selected through the above process, a read or write operation is performed using a lower address indicating an address in the memory block transferred through the row delay buffer and the column delay buffer.

Claims (1)

In a method for generating an internal address in vlsi of a pipelined memory architecture of a systolic structure, A row delay buffer selection signal brow, a column delay buffer selection signal bcol for selecting each sub memory block by partially decoding the entire input address inputted to the upper decoder, and between the sub memory block to be selected and the upper decoder. Generating a signal sel_blk indicative of pipeline depth; Determining whether valid data moves in a diagonal direction starting from an adjacent sub memory block by using a row delay buffer selection signal brow and a column delay buffer selection signal bcol in each row and column delay buffer; Generating an address for a selected diagonal block selected using the row delay buffer selection signal brow, column delay buffer selection signal bcol, and pipeline depth signal sel_blk. Way.