JP2518065B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2518065B2 JP2518065B2 JP1288102A JP28810289A JP2518065B2 JP 2518065 B2 JP2518065 B2 JP 2518065B2 JP 1288102 A JP1288102 A JP 1288102A JP 28810289 A JP28810289 A JP 28810289A JP 2518065 B2 JP2518065 B2 JP 2518065B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- aluminum
- electrode
- layer
- element body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、シリコン素体表面にアルミニウム，ニッケ
ルおよび金あるいは銀を積層して電極を形成し、その電
極に接続導体をはんだ付けする半導体素子の製造方法に
関する。The present invention relates to a semiconductor element in which aluminum, nickel and gold or silver are laminated on the surface of a silicon body to form an electrode, and a connection conductor is soldered to the electrode. Manufacturing method.
半導体素体の所定の領域に電気的接続を行うため、そ
の領域の表面に電気を形成し、接続導体をはんだ付けす
る方法は広く行われている。この場合、電極は半導体素
体に良好なオーム性接触をすること、その電極へのはん
だ付け性の良好なことが要求される。単一の金属でこの
両者を兼ね備えたものは得難いため、電極を異なる金属
の蒸着，積層によって形成することも広く行われてい
る。このような積層構造としては、半導体がシリコンの
場合、シリコン側からチタン−ニッケル−金，クロム−
ニッケル−金，アルミニウム−ニッケル−金あるいはア
ルミニウム−ニッケル−銀等がある。In order to electrically connect to a predetermined region of the semiconductor element body, a method of forming electricity on the surface of the region and soldering the connection conductor is widely used. In this case, the electrode is required to make good ohmic contact with the semiconductor body and have good solderability to the electrode. Since it is difficult to obtain a single metal having both of these, it is widely used to form electrodes by vapor deposition and lamination of different metals. As such a laminated structure, when the semiconductor is silicon, titanium-nickel-gold, chromium-
Examples include nickel-gold, aluminum-nickel-gold, aluminum-nickel-silver, and the like.
上記のような電極をシリコン素体上に積層する場合、
シリコン表面と金属とのオーム性接触の不良あるいは金
属蒸着時の損傷の発生により、例えば順方向特性あるい
は逆耐圧などの電気的特性が低下するという問題が生じ
た。順方向電圧降下が増大する原因としては、シリコン
素体の表面不純物濃度が低いことが考えられ、この場
合、表面不純物濃度を上げるため、シリコン素体に再ド
ープを行うことによって、順方向電圧を低くしている。
しかし、それによって製造工程に再ドープという余分な
工程が必要となる。また他の方法として、シリコン素体
と金属との合金化を進め、あるいはシリコン素体に生じ
た損傷を取り去るため、蒸着後400℃以上でのアニール
を行うこともある。この場合も、アニール工程という余
分な工程が必要となり、さらに積層構造表面に常温放置
中の表面の変質を防ぐために設ける金あるいは銀などの
貴金属層の変色を招き、はんだの濡れ性を損なう問題が
あった。When stacking the above electrodes on a silicon body,
Due to the poor ohmic contact between the silicon surface and the metal or the occurrence of damage at the time of vapor deposition of the metal, there arises a problem that electrical characteristics such as forward characteristics and reverse breakdown voltage are deteriorated. A possible cause of the increase in the forward voltage drop is that the surface impurity concentration of the silicon element body is low. In this case, in order to increase the surface impurity concentration, the silicon element element is re-doped to increase the forward voltage. It is low.
However, this requires an extra step of re-doping in the manufacturing process. As another method, annealing at 400 ° C. or higher may be performed after vapor deposition in order to promote alloying between the silicon element body and a metal or to remove damage generated in the silicon element body. In this case as well, an extra step such as an annealing step is required, and further, there is a problem that the discoloration of a noble metal layer such as gold or silver provided to prevent deterioration of the surface of the laminated structure during standing at room temperature is impaired, and the wettability of the solder is impaired. there were.
本発明の目的は、上述の問題を解決し、半導体素体と
の良好なオーム性接触が得られると共に表面層へのはん
だの濡れ性の良好な電極を有し、順方向電圧降下などの
電気的特性の良好な半導体素子を少ない工程数で製造す
る方法を提供することにある。An object of the present invention is to solve the above-mentioned problems, to obtain a good ohmic contact with a semiconductor element body, and to have an electrode with good wettability of solder to a surface layer, and to provide an electrical property such as forward voltage drop. It is an object of the present invention to provide a method for manufacturing a semiconductor element having excellent static characteristics in a small number of steps.
上記の目的を達成するために、本発明は、シリコン素
体の表面上にシリコン素体に接する層がアルミニウム蒸
着層である積層構造の電極を有し、その電極に接続導体
がはんだ付けされる半導体素子の製造方法において、ア
ルミニウム層蒸着時に半導体素体を200〜300℃に加熱す
るものとする。In order to achieve the above-mentioned object, the present invention has an electrode having a laminated structure in which a layer in contact with the silicon element body is an aluminum vapor deposition layer on the surface of the silicon element body, and a connecting conductor is soldered to the electrode. In the method for manufacturing a semiconductor device, the semiconductor element body is heated to 200 to 300 ° C. during the vapor deposition of the aluminum layer.
シリコン素体に不純物を拡散して所定の導電型の領域
を形成するとき、拡散温度で素体表面に酸化膜が形成さ
れ、不純物がその酸化膜に吸い出されて表面不純物濃度
が低下する。このため、その上に蒸着されたアルミニウ
ムとシリコンとの良好なオーム性接触が得られなくな
る。しかるに蒸着時にシリコン素体にバックヒートをか
けることによりアルミニウムがシリコンと固溶し、良好
なアルミニウム・シリコン接触が得られる。When an impurity is diffused into a silicon element body to form a region of a predetermined conductivity type, an oxide film is formed on the surface of the element body at the diffusion temperature, and the impurity is sucked into the oxide film to reduce the surface impurity concentration. This makes it impossible to obtain a good ohmic contact between the aluminum and silicon vapor-deposited thereon. However, aluminum is solid-dissolved with silicon by back-heating the silicon body during vapor deposition, and good aluminum-silicon contact can be obtained.
第１図は本発明の一実施例のダイオード素子を示し、
ｎ型シリコン基板１の表面に酸化膜３のマスクを被着
し、アクセプタの拡散によりｐ型領域２を形成したもの
である。この基板１のｐ型領域２の側に先ずアルミニウ
ム層４を電子ビーム蒸着するが、その際、バックヒート
により基板１の温度を種々変化させる。次いで、ニッケ
ル層５および金層６を順次蒸着するが、この際には基板
１は加熱しない。このようにして形成したアルミニウム
−ニッケル−金電極の上にはんだ７を用いてリード線８
をろう付けする。FIG. 1 shows a diode element of one embodiment of the present invention,
A mask of an oxide film 3 is deposited on the surface of an n-type silicon substrate 1, and a p-type region 2 is formed by diffusing acceptors. The aluminum layer 4 is first electron-beam evaporated on the p-type region 2 side of the substrate 1, and at this time, the temperature of the substrate 1 is changed variously by back heating. Then, the nickel layer 5 and the gold layer 6 are sequentially deposited, but the substrate 1 is not heated at this time. The lead wire 8 is formed on the aluminum-nickel-gold electrode thus formed by using the solder 7.
Braze
第２図は、このようにして製造したダイオードの順方
向電圧VFおよびリード線８を引っ張ったときのはんだと
電極の密着強度とアルミニウム蒸着時の基板温度との関
係曲線である。第２図に示すように、順方向電圧は温度
を上げるほど良くなり、400℃以上では飽和する。一
方、電極とはんだの密着強度は、温度を上げるとはんだ
付け面の変質によって弱くなり、350℃以上で急激に濡
れ性が落ちた。従って、ろう付強度，順方向特性を考え
ると、200〜300℃が最適の基板加熱温度である。200〜3
00℃のバックヒートは、複雑な装置を用いないで行うこ
とができる。FIG. 2 is a relational curve of the forward voltage V F of the diode thus manufactured, the adhesion strength between the solder and the electrode when the lead wire 8 is pulled, and the substrate temperature during aluminum vapor deposition. As shown in FIG. 2, the forward voltage becomes better as the temperature rises and saturates at 400 ° C. or higher. On the other hand, the adhesion strength between the electrode and the solder weakened due to the deterioration of the soldering surface when the temperature was raised, and the wettability dropped sharply at 350 ° C or higher. Therefore, considering the brazing strength and forward characteristics, 200 to 300 ° C is the optimum substrate heating temperature. 200 ~ 3
Back heating at 00 ° C can be performed without using a complicated device.
第３図は、第１図に示したダイオードにおいて、本発
明に基づきアルミニウム蒸着時に200〜300℃のバックヒ
ートをシリコン基板に行ったもの、バックヒートを行わ
ないものおよびバックヒートは行わないが蒸着後400℃
のアニールを行ったものの順方向特性をそれぞれ実線3
1,破線32および鎖線33に示す。本発明の実施例の素子は
400℃の熱アニールを行ったものとまったく同等の特性
が得られた。FIG. 3 shows the diode shown in FIG. 1 in which a silicon substrate is backheated at 200 to 300 ° C. during aluminum vapor deposition according to the present invention, a backheat is not performed, and a backheat is not performed. After 400 ℃
The solid line 3 shows the forward characteristics of
1, indicated by dashed line 32 and dashed line 33. The device of the embodiment of the present invention is
The same characteristics as those obtained by thermal annealing at 400 ° C were obtained.
本発明は、ダイオードに限らず他のシリコン半導体素
子にも、またアルミニウム−ニッケル−金積層構造に限
らず、シリコン素体に接してアルミニウム層をもつ電極
構造を有する他の素子に適用できる。INDUSTRIAL APPLICABILITY The present invention can be applied not only to the diode but also to other silicon semiconductor elements, and not only to the aluminum-nickel-gold laminated structure, but also to other elements having an electrode structure having an aluminum layer in contact with the silicon element body.
本発明によれば、シリコン素体側がアルミニウム層か
らなる積層電極構造形成の際に、アルミニウム層蒸着時
に素体を200〜300℃に加熱することにより、電極表面の
はんだ付け性を害することなく、アルミニウム・シリコ
ン間に損傷の残らぬ良好なオーム性接触が得られた。す
なわち、再ドープあるいは後アニールの工程を必要とす
ることなく、蒸着時の条件のみで電気的特性のすぐれた
半導体素子が製造でき、特に電流容量100A以上の大電流
素子の製造に極めて有効である。According to the present invention, when forming the laminated electrode structure in which the silicon body side is made of an aluminum layer, by heating the body to 200 to 300 ° C. during the aluminum layer deposition, without impairing the solderability of the electrode surface, A good ohmic contact was obtained between the aluminum and silicon without any damage. That is, it is possible to manufacture a semiconductor element having excellent electric characteristics only under the conditions during vapor deposition without requiring a step of re-doping or post-annealing, and it is extremely effective particularly for manufacturing a large current element having a current capacity of 100 A or more. .
第１図は本発明の一実施例によるダイオード素子の断面
図、第２図は第１図の素子のアルミニウム蒸着時のシリ
コン基板温度と順方向電圧およびはんだ密着強度との関
係線図、第３図は第１図の構造の素子のアルミニウム層
形成条件が異なる場合の電流−電圧特性線図である。 1:シリコン基板、2:p型領域、4:アルミニウム層、5:ニ
ッケル層、6:金層、7:はんだ、8:リード線。1 is a cross-sectional view of a diode device according to an embodiment of the present invention, FIG. 2 is a relational diagram of the silicon substrate temperature, forward voltage and solder adhesion strength during aluminum deposition of the device of FIG. The figure is a current-voltage characteristic diagram when the aluminum layer forming conditions of the element having the structure of FIG. 1 are different. 1: Silicon substrate, 2: P-type region, 4: Aluminum layer, 5: Nickel layer, 6: Gold layer, 7: Solder, 8: Lead wire.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 9169−4Ｍ Ｈ０１Ｌ 21/92 ６０４Ｒ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location 9169-4M H01L 21/92 604R
Claims (1)
する層がアルミニウム蒸着層である積層構造の電極を有
し、その電極に接続導体がはんだ付けされる半導体素子
の製造方法において、アルミニウム層蒸着時に半導体素
体を200〜300℃に加熱することを特徴とする半導体素子
の製造方法。1. A method for manufacturing a semiconductor element, comprising: an electrode having a laminated structure in which a layer in contact with the silicon element body is an aluminum vapor-deposited layer on a surface of the silicon element body; A method for manufacturing a semiconductor element, which comprises heating a semiconductor body to 200 to 300 ° C. during layer deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1288102A JP2518065B2 (en) | 1989-11-06 | 1989-11-06 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1288102A JP2518065B2 (en) | 1989-11-06 | 1989-11-06 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03148847A JPH03148847A (en) | 1991-06-25 |
| JP2518065B2 true JP2518065B2 (en) | 1996-07-24 |
Family
ID=17725822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1288102A Expired - Fee Related JP2518065B2 (en) | 1989-11-06 | 1989-11-06 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2518065B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4716400B2 (en) * | 2004-06-11 | 2011-07-06 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| KR101007902B1 (en) | 2009-03-25 | 2011-01-14 | 서울반도체 주식회사 | Driving circuit for light emitting diode |
-
1989
- 1989-11-06 JP JP1288102A patent/JP2518065B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03148847A (en) | 1991-06-25 |
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