JP2584050B2 - I / O conversion buffer memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output conversion buffer memory particularly used in the field of data processing such as image processing.

2. Description of the Related Art As a conventional buffer memory, for example, there is a two-port SRAM MB8421 / 8422 described in "Fujitsu Semiconductor Device Data Book, 1987, Memory", pp. 645-654.

FIG. 7 is a configuration diagram of a data processing device using a conventional buffer memory. In FIG. 7, reference numeral 11 denotes a data processing device for processing in the X direction, and 12 denotes a two-port static ram (hereinafter referred to as a static RAM) having a memory capacity of 2K × 8 and a size of 48 pins per chip for storing an intermediate result of the processing. A ram is abbreviated as SRAM), and a data processing device 13 performs processing in the Y direction.

As described above, in the data processing device configured using the buffer memory of the two-port SRAM, the data processing device
11 writes the intermediate result processed in the X-direction in the X-direction from the L-side port of the buffer memory 12 of the 2-port SRAM, and the data processor 13 writes the R
The intermediate results are read out from the side ports in the order of the Y direction and processed in the Y direction.

However, in the above-described configuration, since the writing order and reading order of the buffer memory are different, a writing or reading address calculation mechanism is required on the data processing device 11 or the data processing device 13 side. Also, since it is composed of SRAM, the number of pins per chip is large, and the capacity is very small compared to the dynamic ram (hereinafter abbreviated as DRAM). There is a problem that it is not suitable as a conversion buffer memory.

In view of the foregoing, the present invention provides a large-capacity input / output conversion buffer memory capable of converting the order of data at the time of input and the order of data at the time of output so as to facilitate data processing. The purpose is to provide.

Means for Solving the Problems The present invention provides an address conversion memory for inputting a write designation address as an address, outputting a write address as data, and inputting a write address and a read address. A selector that separates and outputs addresses and column addresses, and a write data group is sequentially input to the matrix specified by the write address via the random port at the time of writing, and from the row specified by the read address at the time of reading This is an input / output conversion buffer memory including a two-port dynamic memory group for sequentially outputting read data groups via a serial port.

In another invention, an address conversion memory for inputting a read designation address as an address and outputting the read address as data, and a write address and a read address as inputs, selecting one of them, and then selecting a row address and a column. A selector that separates and outputs addresses, and a write data group is sequentially input to the row specified by the write address via the serial port at the time of writing, and at the time of reading, data is read from the matrix specified by the read address And a two-port dynamic memory group for sequentially outputting groups via random ports.

According to the present invention, the data group is sequentially input from the random port in the order of the write address specified by the address conversion memory, and the data group is sequentially output from the serial port in the column direction of the specified read address row.

According to another aspect of the present invention, a data group is sequentially input from a serial port in the column direction of a specified write address row, and the data group is sequentially output from a random port in the order of a read address specified by the address conversion memory.

FIG. 1 is a configuration diagram of an input / output conversion buffer memory according to an embodiment of the present invention. In FIG. 1, 1 is an address conversion memory for inputting a designated address as an address, and outputting an actual address as data. 2 is for inputting a write address and a read address. A selector that separates and outputs a column address, 31 to 34 input data from random ports,
This is a two-auto dynamic memory that outputs data from a serial port.

The operation of the input / output conversion buffer memory of the present embodiment configured as described above will be described below.

First, writing will be described with reference to the timing chart of FIG. It is assumed that address conversion data is input to the address conversion memory 1 in advance. The write designation address is converted into a write address by the address conversion memory 1, separated into a row address R 1 and a column address C 1 via the selector 2, and is divided into a two-port dynamic memory group 31.
To 34 are input as write addresses. And 2
Write control signal to port dynamic memory group 31-34
Write data D11 to D14 are sequentially input together with WE1 to WE4, and n data are written in one cycle. Similarly, in the next cycle, the data D21 to D21 are stored in the row address R2 and the column address C2 of the two-port dynamic memory groups 31 to 34.
24 are written respectively.

Next, the reading time will be described with reference to the timing chart of FIG. A read address of a line or the like is separated into a row address R3 and a column address C3 via the selector 2 and input to the two-port dynamic memory groups 31 to 34 as a read address. And the two-port dynamic memory group 31
After the common serial clock signal SC is input to ~ 34,
The serial enable signals SE1 to SE4 are sequentially enabled, and the data D31 to D34 are read. After that, the common serial clock signal SC and separate serial enable signal SE
1 to SE4 are sequentially input, and data of the same row is sequentially read from the two-port dynamic memory groups 31 to 34 in the column direction.

The above-described writing and reading can be performed simultaneously within a range where there is no conflict at the time of address input.

As described above, according to the present embodiment, a two-port DRAM is used, an address conversion memory is provided around the DRAM, and a plurality of data are continuously input within one cycle from a random port at the time of writing. A large-capacity memory is realized by the amount of hardware, and the input order and the output order can be converted to perform high-speed writing and reading.

In the present embodiment, the translation address is stored in advance in the address translation memory. However, the translation address may be updated and used during writing.

FIG. 2 is a configuration diagram of an input / output conversion buffer memory according to another embodiment of the present invention. In FIG. 2, reference numeral 1 denotes an address conversion memory, and reference numeral 2 denotes a selector, which is the same as that in FIG. Numerals 41 to 44 denote a two-port dynamic memory for inputting data from a serial port and outputting data from a random port, and a latch for fetching data and sequentially outputting data by an output enable signal.

The operation of the input / output conversion buffer memory of the present embodiment configured as described above will be described below.

First, writing will be described with reference to the timing chart of FIG. The first write address is separated into a row address R5 and a column address C5 via the selector 2 and input to the two-port dynamic memory groups 41 to 44 as write addresses. And the two-port dynamic memory group 41
~ 44 together with the serial clock signals SC1 ~ SC4 and the data D3
1 to D34 are sequentially written. Thereafter, the serial clock signals SC1 to SC4 are sequentially input, and data is sequentially written to the two-port dynamic memory groups 41 to 44 in the column direction of the same row.

Next, the reading operation will be described with reference to the timing chart of FIG. It is assumed that address conversion data is input to the address conversion memory 1 in advance. The read designation address is converted into a read address by the address conversion memory 1 and separated into a row address R7 and a column address C7 via the selector 2 to be separated into a two-port dynamic memory group 41.
~ 44 is input as the read address. And 2
The n pieces of data are simultaneously read from the port dynamic memory groups 41 to 44 within one cycle, and are temporarily taken into the latch groups 51 to 54 by the clock signal CK. After that, the output enable signals OE1 to OE4 are sequentially enabled, and the data D7
1 to D74 are read. At the same time, in the next cycle, the row addresses R8,
Data D81 to D84 are read from the column address C8 via the latch groups 51 to 54, respectively.

The above-described writing and reading can be performed simultaneously within a range where there is no conflict at the time of address input.

As described above, according to the present embodiment, a two-port DRAM is used, and an address translation memory and a latch are provided around the DRAM.
By taking in a plurality of data from a random port into a latch at the time of reading in a single cycle, it is possible to convert the input order and the output order with a large-capacity memory and write and read at high speed.

In the present embodiment, the translation address is stored in advance in the address translation memory. However, the translation address may be used while updating the translation address when reading.

Further, in the above two embodiments, the two-port dynamic memory group is constituted by four dynamic memories, but it goes without saying that the number of dynamic memories can be arbitrarily constituted according to the application.

Effect of the Invention As described above, according to the present invention, the order of input and output of large-volume data can be converted at high speed, and the practical effect is large.

[Brief description of the drawings]

FIGS. 1 and 2 are diagrams showing the configuration of an input / output conversion buffer memory according to an embodiment of the present invention, FIGS. 3 and 5 are timing diagrams at the time of writing in the embodiment, and FIGS. FIG. 7 is a configuration diagram of a data processing apparatus using a conventional buffer memory. 1 ... Address conversion memory, 2 ... Selector, 31-34 ... 2-port dynamic memory, 41-44 ... 2-port dynamic memory, 5 ... Latch.

Claims (4)

(57) [Claims] An address conversion memory for inputting a write designation address as an address and outputting the write address as data, a write address and a read address as inputs, selecting one of the addresses, and then selecting a row address and a column address. A selector that separates and outputs, and at the time of writing, the write data group is sequentially input to the matrix specified by the write address via the random port, and at the time of reading, the read data group is read from the row specified by the read address A two-port dynamic memory group for sequentially outputting data via a serial port. 2. The two-port dynamic memory group comprises n memories for respectively storing n data in the data group, and has a common address line, data line, RAS signal line, and CAS signal line, and 2. The method according to claim 1, wherein different data are sequentially input from the random port by different write control signals within one cycle, and different data are sequentially output from the serial port by different serial control signals during reading. Input / output conversion buffer memory. 3. An address conversion memory for inputting a read designation address as an address and outputting the read address as data, a write address and a read address as inputs, and selecting either one of the address, a row address and a column. A selector that separates and outputs addresses, and a write data group is sequentially input to the row specified by the write address via the serial port at the time of writing, and at the time of reading, data is read from the matrix specified by the read address A two-port dynamic memory group for sequentially outputting groups via random ports. 4. The two-port dynamic memory group comprises n memories for storing n data in the data group and n latches, respectively.
The signal line and the CAS signal line are common. When writing, separate data is sequentially input from the serial port with separate serial control signals, and when reading, separate data is temporarily stored in the latch from the random port within one cycle from the random port 4. The input / output conversion buffer memory according to claim 3, wherein the data is sequentially output from the latch.