JP2019186841A - AD converter - Google Patents

Abstract

To provide an AD converter capable of shortening a period of each step of the successive approximation to be operable speedily.SOLUTION: An AD converter 1A comprises: DA conversion unit 10A; a comparator 20; and a control unit 30A. The DA conversion unit 10A includes n capacitative elements C-Cand n switches SW-SW. A first end of each capacitative element Cis either a first reference potential VREFH of high voltage, a second reference potential VREFL of low voltage or open according to a setting of the switch SWconfigured by a control signal from the control unit 30A. The control unit 30A outputs, when controlling setting of each switch of the DA conversion unit 10A, a control signal commanding the first end of any capacitative element of the DA conversion unit 10A to open in any step of the successive approximation.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a successive approximation AD converter.

  An AD converter (ADC, analog-to-digital converter) can input analog data and output digital data corresponding to the input analog data. Among them, a successive approximation register (SAR) AD converter includes a DA converter, a comparator, and a controller as main components. The DA converter includes a plurality of capacitive elements and a plurality of switches. The successive approximation type AD converter has fewer analog circuits than other types of AD converters, suppresses static current, and is suitable for process miniaturization with low power consumption. Therefore, successive approximation type AD converters have been actively studied in recent years.

  As described in Non-Patent Document 1, the successive approximation type AD converter generally performs the operations of the initialization step and the successive approximation step as follows. In the initialization step, the DA conversion unit initializes the charge of each capacitive element. After this initialization step, each successive comparison step is performed. In each successive comparison step, the DA converter sets each switch based on a control signal given from the controller, and outputs analog data corresponding to the setting to the comparator. The comparison unit evaluates the size of the analog data output from the DA conversion unit based on the input analog data, and outputs the evaluation result to the control unit. Based on the evaluation result output from the comparison unit, the control unit sets each of the DA conversion units in the next step of the successive comparison so that the analog data output from the DA conversion unit approaches a value corresponding to the input analog data. Outputs control signals that control switch settings.

  The control unit determines the value of the most significant bit (MSB) of the digital data to be output in the first step, and sequentially determines the value of the lower bit in each subsequent step. In step, the value of the least significant bit (LSB) is determined. For example, if the digital data to be output is 4-bit data [d3, d2, d1, d0], the control unit determines the value of d3 of the MSB in the first step 1 and the bit d2 in the next step 2. In the next step 3, the value of bit d1 is determined, and in the final step 4, the value of dSB of LSB is determined.

  In the operation of such a successive approximation type AD converter, the DA converter is used when shifting from the initialization step to the first step 1 of the successive approximation and when shifting from each step of the successive approximation to the next step. The setting of the plurality of switches changes, and the amount of charge of each capacitive element of the DA converter changes. The change in the charge amount of the plurality of capacitive elements of the DA converter causes charge transfer via a reference voltage terminal called kickback. By this kickback, the potential of the reference potential supply line that supplies the reference potential to the DA converter varies. In particular, since the kickback is large in the initial step of the successive approximation, the amount of fluctuation in the potential of the reference potential supply line is also large.

  If the comparison unit evaluates the magnitude of the analog data output from the DA conversion unit at a timing when the fluctuation of the reference potential supplied from the reference potential supply line to the DA conversion unit is large, the evaluation result is erroneous and finally obtained. The digital data that is received may be erroneous. Therefore, the comparison unit evaluates the magnitude of the analog data output from the DA conversion unit at a timing after the fluctuation of the reference potential supplied from the reference potential supply line to the DA conversion unit is stabilized and the reference potential is stabilized. It is preferable to do. In this case, the period of each step of the successive comparison must be set longer than the time required for the reference potential to stabilize after the transition to the step. The AD converter is required to increase the speed, but the time required for the reference potential to stabilize after the transition to the step hinders the speed-up of the AD converter.

  Non-Patent Documents 2 and 3 describe techniques for shortening the period of each step of successive comparison. The technique described in Non-Patent Document 2 speeds up the buffer that outputs the reference potential to the reference potential supply line and adjusts the offset at the time of evaluation by the comparison unit, thereby shortening the period of each step. Plan.

  The AD converter described in Non-Patent Document 3 includes a first DA conversion unit including a plurality of capacitance elements having a small capacitance value and a second DA conversion unit including a plurality of capacitance elements having a large capacitance value. The AD converter separates the second DA converter while performing the successive comparison using the first DA converter in each step, and sets the switch setting of the first DA converter determined in each step to the second DA converter. Reflected in the switch settings of By performing successive approximation using the first DA converter, the kickback is reduced and the period of each step of successive approximation is shortened. The second DA converter is used to compensate for accuracy degradation due to thermal noise. In this AD converter, it is necessary to provide an analog switch between the output end of the DA conversion unit and the input end of the comparison unit.

Behzad Razavi, “A Tale of TwoADCs: Pipelined Versus SAR,” IEEE Solid-State Circuits Magazine, Volume: 7, Issue: 3, pp. 38-46, 2015. Chi-Hang Chan, Yan Zhu, Cheng Li, Wai-Hong Zhang, Iok-Meng Ho, Lai Wei, Seng-Pan U, Rui Paulo Martins, “60-dBSNDR 100-MS / s SAR ADCs With Threshold Reconfigurable Reference ErrorCalibration, ”IEEE Journal of Solid-State Circuits, Volume 52, Number 10, pp.2576-2588, October 2017. Yong Lim and Michael P. Flynn, “A 1 mW 71.5 dB SNDR 50 MS / s 13 bit fully differential ring amplifierbased SAR-assisted pipeline ADC,” IEEE Journal of Solid-State Circuits, Volume50, Number 12, pp.2901-2911 , December 2015.

  The technique described in Non-Patent Document 2 is not preferable because it increases the power consumption by increasing the speed of the buffer. The technique described in Non-Patent Document 3 is not preferable in that it is necessary to provide an analog switch between the output end of the DA conversion unit and the input end of the comparison unit by providing two DA conversion units.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an AD converter that can shorten the period of each step of successive approximation and can easily operate at high speed.

  An AD converter according to a first aspect of the present invention is a successive approximation AD converter that outputs digital data corresponding to input analog data, and is set based on (1) a plurality of capacitive elements and a control signal. A plurality of switches, and by setting all or a part of the plurality of switches, the first end of the capacitor corresponding to the switch among the plurality of capacitors is set to the first reference potential and the second A DA converter that outputs data corresponding to the setting of each of a plurality of switches as either a reference potential or an open from an output terminal in which the second ends of the plurality of capacitive elements are connected in common; (2) A comparison unit that compares the data output from the DA conversion unit with the input analog data and outputs a comparison signal representing the comparison result; and (3) a DA for each successive comparison step based on the comparison signal. Conversion part And a control unit for generating and outputting a control signal so that the difference between the data output and the input analog data is reduced.

  The AD converter according to the second aspect of the present invention is a successive approximation AD converter that outputs digital data according to input analog data, and is set based on (1) a plurality of capacitive elements and a control signal. A plurality of switches, and after the input analog data is held by the plurality of capacitors, the capacitance corresponding to the switch among the plurality of capacitors is set by setting all or some of the plurality of switches. The first end of the element is any one of the first reference potential, the second reference potential, and the open, and data corresponding to the setting of each of the plurality of switches is connected to the second ends of the plurality of capacitive elements in common. A DA converter that outputs from the output terminal; (2) a comparator that compares the data output from the DA converter with a reference level and outputs a comparison signal representing the comparison result; and (3) a comparison signal. Based on the sequential each comparison step, and a control unit that the difference between the data and the reference level output from the DA conversion unit generates and outputs a control signal so as to reduce.

  In the first aspect or the second aspect of the present invention, when the control unit controls the setting of each of the plurality of switches of the DA conversion unit, in any step of the successive comparison, the control unit includes a plurality of capacitance elements of the DA conversion unit. A control signal instructing to open the first end of any of the capacitive elements is output.

  In the first aspect or the second aspect of the present invention, when the control unit controls the setting of each of the plurality of switches of the DA conversion unit, in at least the first step of the successive comparison, the control unit sets the plurality of capacitance elements of the DA conversion unit. It is preferable to output a control signal instructing to open the first end of any of the capacitive elements.

  Further, in the first aspect or the second aspect of the present invention, when the control unit controls the setting of each of the plurality of switches of the DA conversion unit, the plurality of capacitance elements of the DA conversion unit as the successive comparison step proceeds. It is preferable to output a control signal instructing to gradually increase the sum of the capacitance values of the capacitive elements whose first end is the first reference potential or the second reference potential.

  An AD converter according to a third aspect of the present invention is a successive approximation type AD converter that outputs digital data corresponding to a difference between first input analog data and second input analog data. A capacitance element and a plurality of switches set based on the first control signal, and after setting the first input analog data by the plurality of capacitance elements, setting of all or some of the plurality of switches By setting the first end of the capacitive element corresponding to the switch among the plurality of capacitive elements as one of the first reference potential, the second reference potential, and the open, the first data corresponding to the setting of each of the plurality of switches is obtained. A first DA converter that outputs from an output terminal in which the second ends of the plurality of capacitive elements are connected in common; (2) a plurality of capacitive elements and a plurality of switches set based on the second control signal; When In addition, after the second input analog data is held by the plurality of capacitive elements, the first of the capacitive elements corresponding to the switch among the plurality of capacitive elements is set by setting all or some of the plurality of switches. The output terminal is formed by connecting the second data of each of the plurality of capacitive elements in common to the second data corresponding to the setting of each of the plurality of switches, with the terminal being one of the first reference potential, the second reference potential, and the open. (3) a comparison unit for comparing the first data and the second data, and outputting a comparison signal representing the comparison result, and (4) sequentially based on the comparison signal. And a control unit that generates and outputs a first control signal and a second control signal so that a difference between the first data and the second data is reduced for each comparison step.

  In the third aspect of the present invention, the control unit controls the setting of each of the plurality of switches of each of the first DA conversion unit and the second DA conversion unit, and in any step of the successive comparison, the first DA conversion unit and the second DA conversion unit A first control signal and a second control signal instructing to open the first end of any one of the plurality of capacitive elements of each of the conversion units are output.

  In the third aspect of the present invention, the control unit controls the setting of each of the plurality of switches of the first DA conversion unit and the second DA conversion unit, at least in the first step of the successive comparison, It is preferable to output a first control signal and a second control signal instructing to open the first end of any one of the plurality of capacitive elements of each of the 2DA conversion units.

  In addition, when the control unit controls the setting of each of the plurality of switches of each of the first DA conversion unit and the second DA conversion unit, as the successive comparison step proceeds, a plurality of each of the first DA conversion unit and the second DA conversion unit It is preferable to output a first control signal and a second control signal instructing to gradually increase the sum of the capacitance values of the capacitive elements having the first end as the first reference potential or the second reference potential among the capacitive elements. .

  The AD converter according to the present invention can shorten the period of each step of successive approximation and can easily operate at high speed.

FIG. 1 is a diagram illustrating a configuration of the AD converter 1A. FIG. 2 is a table for explaining a first operation example of the AD converter 1A. FIG. 3 is a table for explaining a second operation example of the AD converter 1A. FIG. 4 is a table for explaining a third operation example of the AD converter 1A. FIG. 5 is a table for explaining a fourth operation example of the AD converter 1A. FIG. 6 is a table for explaining a fifth operation example of the AD converter 1A. FIG. 7 is a table for explaining a sixth operation example of the AD converter 1A. FIG. 8 is a table for explaining a seventh operation example of the AD converter 1A. FIG. 9 is a diagram illustrating a configuration of the AD converter 1B. FIG. 10 is a diagram illustrating a circuit example of each switch SW _n of the AD converter 1B. FIG. 11 is a timing chart for explaining the operation of each switch SW _n of the AD converter 1B. FIG. 12 is a diagram illustrating a configuration of the AD converter 1C. FIG. 13 is a table for explaining a first operation example of the AD converter 1C. FIG. 13A shows the operation of the first DA converter 11 of the AD converter 1C. FIG. 13B shows the operation of the second DA converter 12 of the AD converter 1C. FIG. 14 is a table for explaining a second operation example of the AD converter 1C. FIG. 14A shows the operation of the first DA converter 11 of the AD converter 1C. FIG. 14B shows the operation of the second DA converter 12 of the AD converter 1C.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. The present invention is not limited to these exemplifications, but is defined by the scope of the claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.

(First configuration example)
FIG. 1 is a diagram illustrating a configuration of the AD converter 1A. The AD converter 1A of the first configuration example shown in this figure includes a DA converter 10A, a comparator 20, and a controller 30A. The AD converter 1A outputs digital data corresponding to the input analog data Ain from the control unit 30A.

The DA conversion unit 10A includes N capacitive elements C _{0 to} C _N−1 , N switches SW _{0 to} SW _N−1 and a switch SW _RST . The N switches SW _{0 to} SW _N-1 are set based on a control signal output from the control unit 30A. The first end of the capacitive element C _n is connected to the corresponding switch SW _n. The first end of the capacitive element C _n is the setting of the switch SW _n, the first reference potential VREFH high potential, is either the second reference potential VREFL and open low potential. The second end of the capacitive elements C _n constitute the output terminals are connected in common. The switch SW _RST is provided between the output terminal and the second reference potential supply line. The DA conversion unit 10A outputs data CTOP corresponding to the setting of each of the _N switches SW _{0 to} SW _N−1 from the output terminal to the comparison unit 20.

N is an integer of 2 or more, and n is an integer of 0 or more and (N-1) or less. In addition, the first end of any _one of the _N capacitive elements C _{0 to} C _N-1 may be at a constant potential, and in this case, a switch corresponding to the capacitive element is not necessary. is there.

  The comparison unit 20 compares the data input to each of the two input terminals, and outputs a comparison signal representing the comparison result to the control unit 30A. In the first configuration example, the comparison unit 20 inputs the data CTOP output from the DA conversion unit 10A to one input terminal, and inputs the input analog data Ain to the other input terminal.

  Based on the comparison signal output from the comparison unit 20, the control unit 30A controls the control signal so that the difference between the data CTOP output from the DA conversion unit 10A and the input analog data Ain is reduced at each successive comparison step. And outputs the control signal to the DA converter 10A. Below, some operation examples of AD converter 1A are shown. Among these operation examples, an operation example in which all the capacitive elements are connected to the first reference potential VREFH or the second reference potential VREFL in each step of the successive comparison is a comparative example, and any of the steps in the successive comparison has any An example of the operation in which the capacitor element is in an open state is an embodiment.

FIG. 2 is a table for explaining a first operation example of the AD converter 1A. In the first operation example, N = 4, the capacitance value of the capacitive element C ₀ is C, the capacitance value of the capacitive element C ₁ is C, the capacitance value of the capacitive element C ₂ is 2C, and the capacitance of the capacitive element C ₃ The value is 4C. The capacitance value of each capacitive element is indicated by a multiple of the unit capacitance value C. The table has the potential of the first end of the control signals Ccode and the capacitors C _n in each step of the successive approximation is shown. “H” indicates that the first end of the capacitive element is connected to the first reference potential VREFH having a high potential, and “L” indicates that the first end of the capacitive element is connected to the second reference potential VREFL having a low potential. Indicates that Ccode is a 3-bit control signal given from the control unit 30A to the DA conversion unit 10A in order to control the setting of each switch of the DA conversion unit 10A. Setting of the switch SW ₃ is controlled by c2 which is MSB of Ccode [c2, c1, c0] . Setting of the switch SW ₂ is controlled from c1 which is the second bit of Ccode. Setting of the switch SW ₁ is controlled by c0 the LSB of Ccode. Since the capacitive element C ₀ is always connected to the second reference potential VREFL having a low potential, the switch SW ₀ may be omitted.

In the initialization step, both ends of each of the four capacitive elements C _{0 to} C ₃ are set to the second reference potential VREFL by the four switches SW _{0 to} SW ₃ and the switch SW _RST . As a result, the charges of the four capacitive elements C _{0 to} C ₃ are initialized, and the data CTOP output from the DA converter 10A to the comparator 20 is initialized. When the initialization step is completed, the switch SW _RST is turned off.

In a first step 1 the sequential comparison after the initialization step, that is given Ccode [1, 0, 0] to the DA conversion unit 10A from the control unit 30A, the capacitive element C ₃ is connected to a first reference potential VREFH The capacitive elements C ₂ , C ₁ , C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 4C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 4C. The data CTOP output from the DA converter 10A in such a connected state of each capacitive element is (VREFH + VREFL) / 2.

  In step 1, the data CTOP output from the DA converter 10A and the input analog data Ain are compared in magnitude by the comparator 20, and a comparison signal representing the comparison result is output from the comparator 20 to the controller 30A. Then, according to the comparison result of step 1, the control unit 30A determines the Ccode to be given to the DA conversion unit 10A in step 2 next to the successive comparison. Step 2 is divided into Case 1 and Case 2 according to the comparison result of Step 1. If the data CTOP is smaller than the input analog data Ain, the process proceeds to case 1. If the data CTOP is larger than the input analog data Ain, the process proceeds to case 2.

In case 1 of step 2 of the successive approximation, Ccode [1,1,0] is given from the control unit 30A to the DA conversion unit 10A, so that the capacitive elements C ₃ and C ₂ are connected to the first reference potential VREFH. The capacitive elements C ₁ and C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 6C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 2C. The data CTOP output from the DA converter 10A in such a connected state of each capacitive element is (3VREFH + VREFL) / 4.

  In case 1 of step 2, the data CTOP output from the DA converter 10A and the input analog data Ain are compared in magnitude by the comparator 20, and a comparison signal representing the comparison result is output from the comparator 20 to the controller 30A. . Then, according to the comparison result of case 1 in step 2, the control unit 30A determines the Ccode to be given to the DA conversion unit 10A in step 3 next to the successive comparison. Step 3 after case 1 of step 2 is divided into case 1-1 and case 1-2 according to the comparison result of case 1 of step 2. If the data CTOP is smaller than the input analog data Ain, the process proceeds to case 1-1. If the data CTOP is larger than the input analog data Ain, the process proceeds to case 1-2.

In step 2 of the case 2 of the successive approximation, the DA conversion unit 10A from the control unit 30A that is given Ccode [0,1,0], the capacitor C ₂ is connected to the first reference potential VREFH, the capacitor C ₃ , C ₁ and C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 2C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 6C. The data CTOP output from the DA converter 10A in such a connected state of each capacitive element is (VREFH + 3VREFL) / 4.

  In case 2 of step 2, the data CTOP output from the DA converter 10A and the input analog data Ain are compared in magnitude by the comparator 20, and a comparison signal representing the comparison result is output from the comparator 20 to the controller 30A. . Then, according to the comparison result of case 2 in step 2, the control unit 30A determines the Ccode to be given to the DA conversion unit 10A in step 3 next to the successive comparison. Step 3 after case 2 of step 2 is divided into case 2-1 and case 2-2 according to the comparison result of case 2 of step 2. When the data CTOP is smaller than the input analog data Ain, the process proceeds to case 2-1, and when the data CTOP is larger than the input analog data Ain, the process proceeds to case 2-2.

In case 1-1 of step 3, Ccode [1,1,1] is given from the control unit 30A to the DA conversion unit 10A, so that the capacitive elements C ₃ , C ₂ , C ₁ are connected to the first reference potential VREFH. is, the capacitor C ₀ is connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 7C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is C. Therefore, the data CTOP output from the DA converter 10A is (7VREFH + VREFL) / 8.

In case 1-2 of step 3, when Ccode [1,0,1] is given from the control unit 30A to the DA conversion unit 10A, the capacitive elements C ₃ and C ₁ are connected to the first reference potential VREFH, and the capacitance The elements C ₂ and C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 5C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 3C. Therefore, the data CTOP output from the DA converter 10A is (5VREFH + 3VREFL) / 8.

In case 2-1 of step 3, when Ccode [0,1,1] is given from the control unit 30A to the DA conversion unit 10A, the capacitive elements C ₂ and C ₁ are connected to the first reference potential VREFH, and the capacitance The elements C ₃ and C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 3C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 5C. Therefore, the data CTOP output from the DA converter 10A is (3VREFH + 5VREFL) / 8.

In Case 2-2 Step 3, the DA conversion unit 10A from the control unit 30A that is given Ccode [0,0,1], the capacitive element C ₁ is connected to the first reference potential VREFH, capacitive element C ₃ , C ₂ , C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 7C. Therefore, the data CTOP output from the DA converter 10A is (VREFH + 7VREFL) / 8.

  Thus, in the first step 1 of the successive approximation, the Ccode given from the control unit 30A to the DA conversion unit 10A is temporarily set to [1,0,0], and the data CTOP output from the DA conversion unit 10A The input analog data Ain is compared in magnitude, and c2 which is the MSB of Ccode is determined based on the comparison result. In the next step 2, the Ccode given from the control unit 30A to the DA conversion unit 10A is temporarily set to [c2,1,0], and the data CTOP output from the DA conversion unit 10A and the input analog data Ain are large or small. Comparison is made, and c1 which is the second bit of Ccode is determined based on the comparison result.

  In the final step 3, the Ccode given from the control unit 30A to the DA conversion unit 10A is temporarily set to [c2, c1,1], and the data CTOP output from the DA conversion unit 10A and the input analog data Ain are large or small. Based on the comparison result, c0 which is the LSB of Ccode is determined. Then, Ccode finally obtained after step 3 (or digital data obtained based on this Ccode) is output from the control unit 30A as digital data corresponding to the input analog data Ain.

FIG. 3 is a table for explaining a second operation example of the AD converter 1A. In the second operation example, N = 5, the capacitance value of the capacitive element C ₀ is C, the capacitive value of the capacitive element C ₁ is C, the capacitive value of the capacitive element C ₂ is 2C, and the capacitance of the capacitive element C ₃ with a value of 2C, and 2C the capacitance value of the capacitor _{C 4.} Whereas the capacitance of the capacitor C ₃ in the first operation example of the prior was 4C, the sum of the capacitance of the capacitor C _3, C ₄ in the second operation example is 4C. Therefore, when the capacitive elements C ₃ and C ₄ provided in parallel with each other are set to the same potential based on c2 of Ccode, the second operation example is equivalent to the first operation example.

  FIG. 3 shows the transition from the initialization step to the successive comparison step 1, the transition from the step 1 to the next step 2 case 1, and the transition from the step 1 to the next step 2 case 2. In addition, the charge transfer amount (kickback charge transfer amount) via the reference potential supply line in each of them is also shown. If V = VREFH−VREFL, the amount of charge transfer when shifting from the initialization step to the successive comparison step 1 is 2 CV. The amount of charge transfer when shifting from step 1 to case 1 of the next step 2 is CV / 2. The amount of charge transfer when shifting from step 1 to case 2 of the next step 2 is 3 CV / 2.

FIG. 4 is a table for explaining a third operation example of the AD converter 1A. As in the case of the second operation example described above, in this third operation example, N = 5, the capacitance value of the capacitive element C ₀ is C, the capacitance value of the capacitive element C ₁ is C, and the capacitive element C ₂ the capacitance value 2C, and 2C the capacitance value of the capacitor C _3, and 2C the capacitance value of the capacitor C _4.

  FIG. 4 shows two cases A and B in the first step 1 of the successive approximation. In this figure, “z” indicates that the first end of the capacitive element is not connected to either the first reference potential VREFH or the second reference potential VREFL and is in an open state (high impedance state).

In case A, the capacitive elements C ₄ , C ₃ , and C ₂ are opened, the capacitive element C ₁ is connected to the first reference potential VREFH, and the capacitive element C ₀ is connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is C.

In Case B, the capacitor C ₄ is connected to the first reference potential VREFH, the capacitor C _3, C ₂ are in an open state, a capacitor C _1, C ₀ is connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 2C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 2C.

  In both cases A and B of Step 1 of the third operation example, the data CTOP output from the DA converter 10A is (VREFH + VREFL) / 2. This is the same value as the data CTOP output from the DA converter 10A in step 1 of each of the first operation example and the second operation example.

  However, in case A of step 1 of the third operation example, the amount of charge transfer when shifting from the initialization step to step 1 of the successive comparison is CV / 2. This is ¼ of the amount of charge transfer when moving to step 1 of each of the first operation example and the second operation example. Further, in case B of step 1 of the third operation example, the amount of charge transfer when shifting from the initialization step to step 1 of the successive comparison is CV. This is ½ of the amount of charge transfer when moving to step 1 of each of the first operation example and the second operation example.

  As described above, when the control unit 30A controls the setting of each switch of the DA conversion unit 10A for each step of the successive comparison, the control unit 30A performs the first of the capacitive elements of the DA conversion unit 10A in any step of the successive comparison. A control signal instructing to open one end is output to the DA converter 10A. By doing in this way, since the sum total of the capacitance values of the capacitive elements used in the successive comparison can be reduced, the kickback can be reduced. In addition, the period of each step of successive approximation can be shortened, and the AD converter can be speeded up.

  Kickback tends to be large at the first step of successive approximation and decrease as the step progresses. Therefore, when controlling the setting of each switch of the DA conversion unit 10A, the control unit 30A opens the first end of any capacitive element of the DA conversion unit 10A in at least the first step 1 of the successive comparison. It is preferable to output a control signal instructing to the DA converter 10A. When the control unit 30A controls the setting of each switch of the DA conversion unit 10A, the first end of the plurality of capacitive elements of the DA conversion unit 10A is set to the first reference potential VREFH or the first as the successive comparison step proceeds. It is preferable to output, to the DA converter 10A, a control signal that instructs to gradually increase the sum of the capacitance values of the capacitive elements having the 2 reference potential VREFL. Further, the control unit 30A sets the first ends of all the capacitive elements of the DA conversion unit 10A to the first reference potential VREFH or the second reference potential VREFL in the last step of the successive approximation or until the last step. It is preferable to output a control signal instructing to the DA converter 10A.

FIG. 5 is a table for explaining a fourth operation example of the AD converter 1A. In the fourth operation example, N = 8, and the capacitance values of the eight capacitive elements C _{0 to} C ₇ are C. The sum of the capacitance values of the capacitive elements C ₇ , C ₆ , C ₅ , and C ₄ is 4C, and the sum of the capacitance values of the capacitive elements C ₃ and C ₂ is 2C. Accordingly, the capacitive elements C ₇ , C ₆ , C ₅ , C ₄ provided in parallel with each other are set to the same potential based on c2 of Ccode, and the capacitive elements C ₃ , C ₃ provided in parallel with each other are set. by C ₂ is set to the same potential to each other based on c1 of Ccode, fourth operation example becomes equivalent to the first operation example.

FIG. 6 is a table for explaining a fifth operation example of the AD converter 1A. Similarly to the case of the fourth operation example described above, in this fifth operation example, N = 8 and the capacitance values of the eight capacitive elements C _{0 to} C ₇ are C.

In the fifth operation example, in the first step 1 of the successive approximation, the DA conversion unit 10A from the control unit 30A that is given Ccode [1, 0, 0], the capacitive element C ₄ to the first reference potential VREFH The capacitive element C ₀ is connected to the second reference potential VREFL, and the other capacitive elements are opened. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is C. Therefore, the data CTOP output from the DA converter 10A is (VREFH + VREFL) / 2.

In case 1 of step 2, Ccode [1,1,0] is given from the control unit 30A to the DA conversion unit 10A, so that the three capacitive elements C ₆ , C ₄ , and C ₂ are set to the first reference potential VREFH. One capacitor element C ₀ is connected to the second reference potential VREFL, and the other capacitor elements are opened. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 3C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is C. Therefore, the data CTOP output from the DA converter 10A is (3VREFH + VREFL) / 4.

In Case 2 of Step 2, Ccode [0,1,0] to the DA conversion unit 10A from the control unit 30A that is given, one of the capacitor C ₂ is connected to the first reference potential VREFH, 3 pieces of The capacitive elements C ₆ , C ₄ , and C ₀ are connected to the second reference potential VREFL, and the other capacitive elements are opened. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 3C. Therefore, the data CTOP output from the DA converter 10A is (VREFH + 3VREFL) / 4.

In case 1-1 of step 3, Ccode [1,1,1] is given from the control unit 30A to the DA conversion unit 10A, so that the seven capacitive elements C ₇ , C ₆ , C ₅ , C ₄ , C ₃ , C ₂ and C ₁ are connected to the first reference potential VREFH, and one capacitive element C ₀ is connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 7C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is C. Therefore, the data CTOP output from the DA converter 10A is (7VREFH + VREFL) / 8.

In the case 1-2 of Step 3, Ccode [1,0,1] is given from the control unit 30A to the DA conversion unit 10A, so that the five capacitive elements C ₇ , C ₆ , C ₅ , C ₄ , C ₁ is connected to the first reference potential VREFH, and the three capacitive elements C ₃ , C ₂ , C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 5C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 3C. Therefore, the data CTOP output from the DA converter 10A is (5VREFH + 3VREFL) / 8.

In case 2-1 of step 3, Ccode [0, ₁ , ₁ ] is given from the control unit 30A to the DA conversion unit 10A, so that the three capacitive elements C ₃ , C ₂ , C ₁ have the first reference potential. The five capacitive elements C ₇ , C ₆ , C ₅ , C ₄ , and C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 3C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 5C. Therefore, the data CTOP output from the DA converter 10A is (3VREFH + 5VREFL) / 8.

In Case 2-2 Step 3, the DA conversion unit 10A from the control unit 30A that is given Ccode [0,0,1], 1 single capacitor element C ₁ is connected to the first reference potential VREFH, 7 The capacitive elements C ₇ , C ₆ , C ₅ , C ₄ , C ₃ , C ₂ , C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 7C. Therefore, the data CTOP output from the DA converter 10A is (VREFH + 7VREFL) / 8.

  As described above, the data CTOP output from the DA converter 10A in the fifth operation example in each step and each case is the data CTOP output from the DA converter 10A in the first to fourth operation examples described above. The same value as In the fifth operation example, in step 1 and step 2 of the successive comparison, a control signal instructing to open the first end of any capacitive element of the DA converter 10A is output to the DA converter 10A. By doing in this way, since the sum total of the capacitance values of the capacitive elements used in the successive comparison can be reduced, the kickback can be reduced. In addition, the period of each step of successive approximation can be shortened, and the AD converter can be speeded up.

FIG. 7 is a table for explaining a sixth operation example of the AD converter 1A. As in the case of the fourth and fifth operation examples described above, in this sixth operation example, N = 8, and the capacitance values of the eight capacitive elements C _{0 to} C ₇ are C. However, in each of the above-described fourth and fifth operation examples, the connection of each capacitive element is determined based on Ccode [c2, c1, c0] expressed in binary code, but in this sixth operation example, The connection of each capacitive element is determined based on a thermometer code obtained by decoding Ccode [c2, c1, c0].

In the sixth operation example, in the first step 1 of the successive approximation, the four capacitive elements C _{0 to} C ₃ are connected to the first reference potential VREFH, and the four capacitive elements C _{4 to} C ₇ are connected to the second reference potential VREFH. Connected to potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (VREFH + VREFL) / 2.

In Case 1 of Step 2, the six capacitive elements C _{0 to} C ₅ are connected to the first reference potential VREFH, and the two capacitive elements C ₆ and C ₇ are connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (3VREFH + VREFL) / 4.

In case 2 of step 2, the two capacitive elements C ₀ and C ₁ are connected to the first reference potential VREFH, and the six capacitive elements C _{2 to} C ₇ are connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (VREFH + 3VREFL) / 4.

In case 1-1 of Step 3, the seven capacitive elements C _{0 to} C ₆ are connected to the first reference potential VREFH, and the one capacitive element C ₇ is connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (7VREFH + VREFL) / 8.

In Step 1-2 of Step 3, the five capacitive elements C _{0 to} C ₄ are connected to the first reference potential VREFH, and the three capacitive elements C _{5 to} C ₇ are connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (5VREFH + 3VREFL) / 8.

In the case 2-1 of Step 3, the three capacitive elements C _{0 to} C ₂ are connected to the first reference potential VREFH, and the five capacitive elements C _{3 to} C ₇ are connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (3VREFH + 5VREFL) / 8.

In Case 2-2 Step 3, one of the capacitor C ₀ is connected to the first reference potential VREFH, 7 pieces of the capacitor C ₁ -C ₇ is connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (VREFH + 7VREFL) / 8.

  As described above, the data CTOP output from the DA converter 10A in the sixth operation example in each step and each case is the data CTOP output from the DA converter 10A in the first to fifth operation examples described above. The same value as

FIG. 8 is a table for explaining a seventh operation example of the AD converter 1A. As in the case of the fourth to sixth operation examples described above, in this seventh operation example, N = 8 and the capacitance values of the eight capacitive elements C _{0 to} C ₇ are C. Similarly to the case of the sixth operation example described above, also in the seventh operation example, the connection of each capacitive element is determined based on the thermometer code obtained by decoding Ccode [c2, c1, c0].

In the seventh operation example, in the first step 1 of the successive approximation, one capacitor element C ₃ is connected to the first reference potential VREFH, the one capacitor element C ₇ is connected to the second reference potential VREFL, Other capacitive elements are in an open state. Therefore, the data CTOP output from the DA converter 10A is (VREFH + VREFL) / 2.

In case 1 of step 2, three capacitors C ₁ , C ₃ , C ₅ are connected to the first reference potential VREFH, one capacitor C ₇ is connected to the second reference potential VREFL, and other capacitors. The element is in an open state. Therefore, the data CTOP output from the DA converter 10A is (3VREFH + VREFL) / 4.

In step 2 of the case 2, one capacitor element C ₁ is connected to the first reference potential VREFH, 3 pieces of the capacitor C _3, C _5, C ₇ is connected to the second reference potential VREFL, other capacity The element is in an open state. Therefore, the data CTOP output from the DA converter 10A is (VREFH + 3VREFL) / 4.

In case 1-1 of Step 3, the seven capacitive elements C _{0 to} C ₆ are connected to the first reference potential VREFH, and the one capacitive element C ₇ is connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (7VREFH + VREFL) / 8.

In Step 1-2 of Step 3, the five capacitive elements C _{0 to} C ₄ are connected to the first reference potential VREFH, and the three capacitive elements C _{5 to} C ₇ are connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (5VREFH + 3VREFL) / 8.

In the case 2-1 of Step 3, the three capacitive elements C _{0 to} C ₂ are connected to the first reference potential VREFH, and the five capacitive elements C _{3 to} C ₇ are connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (3VREFH + 5VREFL) / 8.

In Case 2-2 Step 3, one of the capacitor C ₀ is connected to the first reference potential VREFH, 7 pieces of the capacitor C ₁ -C ₇ is connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (VREFH + 7VREFL) / 8.

  As described above, the data CTOP output from the DA converter 10A in the seventh operation example in each step and each case is the data CTOP output from the DA converter 10A in the first to sixth operation examples described above. The same value as In the seventh operation example, in step 1 and step 2 of the successive approximation, a control signal instructing to open the first end of any capacitive element of the DA converter 10A is output to the DA converter 10A. By doing in this way, since the sum total of the capacitance values of the capacitive elements used in the successive comparison can be reduced, the kickback can be reduced. In addition, the period of each step of successive approximation can be shortened, and the AD converter can be speeded up.

(Second configuration example)
FIG. 9 is a diagram illustrating a configuration of the AD converter 1B. The AD converter 1B of the second configuration example shown in this figure includes a DA conversion unit 10B, a comparison unit 20, a control unit 30B, and a switch 40. The AD converter 1B outputs digital data corresponding to the input analog data Ain from the control unit 30B.

The DA conversion unit 10B includes N capacitive elements C _{0 to} C _N−1 and N switches SW _{0 to} SW _N−1 . The N switches SW _{0 to} SW _N-1 are set based on a control signal output from the control unit 30B. The first end of the capacitive element C _n is connected to the corresponding switch SW _n. The first end of the capacitive element C _n is the setting of the switch SW _n, the first reference potential VREFH high potential, is either the second reference potential VREFL and open low potential. The second end of the capacitive elements C _n constitute the output terminals are connected in common. The DA converter 10B holds the input analog data Ain by the N capacitive elements C _{0 to} C _N-1 and then compares the data CTOP corresponding to the setting of each of the _N switches SW _{0 to} SW _N-1. 20 output.

N is an integer of 2 or more, and n is an integer of 0 or more and (N-1) or less. In addition, the first end of any _one of the _N capacitive elements C _{0 to} C _N-1 may be at a constant potential, and in this case, a switch corresponding to the capacitive element is not necessary. is there.

  The comparison unit 20 compares the data input to each of the two input terminals, and outputs a comparison signal representing the comparison result to the control unit 30B. In the second configuration example, the comparison unit 20 inputs the data CTOP output from the DA conversion unit 10B to one input terminal, and inputs the reference level VCM to the other input terminal. The reference level VCM is, for example, an average value of the first reference potential VREFH and the second reference potential VREFL. Alternatively, the reference level VCM may be set to a value at which the comparison unit 20 can operate with the highest performance (for example, high sensitivity and high SN ratio). The switch 40 is provided between the two input terminals of the comparison unit 20.

  Based on the comparison signal output from the comparison unit 20, the control unit 30B controls the control signal so that the difference between the data CTOP output from the DA conversion unit 10B and the input analog data Ain is reduced at each successive comparison step. And outputs the control signal to the DA converter 10B.

In the AD converter 1B, in the initialization step, the switch 40 is turned on to initialize CTOP to VCM, and the input analog data Ain is held in each capacitor element C _n by the setting of each switch SW _n. The The AD converter 1B can perform the same operation as that of the above-described AD converter 1A in each successive comparison step after the initialization step.

  When the control unit 30B controls the setting of each switch of the DA conversion unit 10B for each successive comparison step, the control unit 30B opens the first end of any capacitive element of the DA conversion unit 10B in any step of the successive comparison. Is output to the DA converter 10B. By doing in this way, since the sum total of the capacitance values of the capacitive elements used in the successive comparison can be reduced, the kickback can be reduced. In addition, the period of each step of successive approximation can be shortened, and the AD converter can be speeded up.

  When controlling the setting of each switch of the DA conversion unit 10B, the control unit 30B instructs to open the first end of any capacitive element of the DA conversion unit 10B in at least the first step 1 of the successive comparison. It is preferable to output a control signal to the DA converter 10B. When the control unit 30B controls the setting of each switch of the DA conversion unit 10B, the first end of the plurality of capacitive elements of the DA conversion unit 10B is connected to the first reference potential VREFH or the first level as the successive comparison step proceeds. It is preferable to output to the DA converter 10B a control signal instructing to gradually increase the sum of the capacitance values of the capacitive elements having the 2 reference potential VREFL. Further, in the final step of the successive approximation, the control unit 30B converts the control signal that instructs the first ends of all the capacitive elements of the DA conversion unit 10B to be the first reference potential VREFH or the second reference potential VREFL. It is preferable to output to the unit 10B.

FIG. 10 is a diagram illustrating a circuit example of each switch SW _n of the AD converter 1B. Each switch SW _n includes a PMOS transistor M1, an NMOS transistor M2, a PMOS transistor M3, and an NMOS transistor M4. These MOS transistors operate as switches in which conduction / non-conduction between the source and the drain is set according to the magnitude of the gate voltage.

PMOS transistor M1 is provided between the supply line and the capacitance element C _n the first reference potential VREFH. The PMOS transistor M1 inputs a signal output from the gate circuit G1 to the gate, and ON / OFF setting is controlled based on the gate voltage.

NMOS transistor M2 is provided between the supply line and the capacitance element C _n the second reference potential VREFL. The NMOS transistor M2 is controlled to be turned on / off based on a signal output from the gate circuit G2.

PMOS transistor M3 and NMOS transistor M4 are provided in parallel with each other between the input analog data Ain is linear and capacitive element C _n input. The on / off setting of the PMOS transistor M3 is controlled based on the signal ASWn. The NMOS transistor M4 is controlled to be turned on / off based on the signal ASWp.

  The gate circuit G1 receives the signal Cntl and the signal ACtp and supplies a signal having a negative logical product of the values of these two signals to the gate of the PMOS transistor M1. The gate circuit G2 inputs the signal Cntl and the signal ACTn, and gives a signal having a negative logical sum of the values of these two signals to the gate of the NMOS transistor M2. The gate circuits G1 and G2 are preferably provided in the DA converter 10B.

  Cntl is any bit of Ccode that is a binary code or any bit of a thermometer code obtained by decoding Ccode. ACTp and ACTn are complementary signals, and when one is at a high level, the other is at a low level. ASWp and ASWn are complementary signals, and when one is at a high level, the other is at a low level.

When ASWp is at a high level, depending on the closing switch 40, the input analog data Ain is held in the capacitor element C _n. When both ASWp and ACTp is at a low level, the capacitor C _n is in an open state. When ASWp is at a low level and ACTp is at a high level, the capacitive element C _n is connected to the first reference potential VREFH or the second reference potential VREFL according to the value of Cntl. By dividing the ACT signal into a plurality, the circuit shown in FIG. 10 is not modified, and only a part of the capacitive elements is connected to the first reference potential VREFH or the second reference potential VREFL, and the rest is controlled to be open. realizable.

FIG. 11 is a timing chart for explaining the operation of each switch SW _n of the AD converter 1B. In this figure, RST is a signal for setting on / off of the switch 40.

After ACTp changes from high level to low level, ASWp changes from low level to high level, and RST also changes from low level to high level. After RST changes from high level to low level, ASWp changes from high level to low level. In the initialization step, the duration RST and ASWp is at a high level, the switch 40 is turned on, CTOP is initialized to VCM, the input analog data Ain each capacitive element C _n is held.

Each successive comparison step begins after ASWp goes from high to low. In the step in which the capacitive element C _n corresponding to the switch SW _n is connected to the first reference potential VREFH or the second reference potential VREFL, ACTP applied to the switch SW _n becomes high level. In the step in which the capacitive element C _n corresponding to the switch SW _n is in an open state, ACTP applied to the switch SW _n remains at a low level.

By such a switching operation, it is possible to avoid a through current from flowing between the line to which the input analog data Ain is input and the reference potential supply line, and the capacitance elements C _n are held. It is possible to prevent the input analog data Ain from leaking.

(Third configuration example)
FIG. 12 is a diagram illustrating a configuration of the AD converter 1C. The AD converter 1C of the third configuration example shown in this figure includes a first DA converter 11, a second DA converter 12, a comparator 20, a controller 30C, a switch 41, and a switch 42. The AD converter 1C receives differential analog data (Ain1, Ain2), and outputs digital data corresponding to the difference between the first input analog data Ain1 and the second input analog data Ain2 from the control unit 30C.

  The first DA converter 11 and the second DA converter 12 in the third configuration example have the same configuration as the DA converter 10B in the second configuration example described above. The first DA converter 11 receives the first input analog data Ain1. The second DA converter 12 receives the second input analog data Ain2.

The N switches SW _{0 to} SW _N−1 of the _first DA converter 11 are set based on the first control signal output from the controller 30C. The first DA converter 11 holds the first input analog data Ain1 by the N capacitive elements C _{0 to} C _{N-1 and then} sets the first input corresponding to the setting of each of the _N switches SW _{0 to} SW _N-1 . The data CTOP1 is output to the comparison unit 20.

The N switches SW _{0 to} SW _N−1 of the second DA converter 12 are set based on the second control signal output from the controller 30C. The second DA converter 12 holds the second input analog data Ain2 by the N capacitive elements C _{0 to} C _N−1 , and then the second DA corresponding to the setting of each of the _N switches SW _{0 to} SW _N−1 . The data CTOP2 is output to the comparison unit 20.

N is an integer of 2 or more, and n is an integer of 0 or more and (N-1) or less. Further, in each of the first DA converter 11 and the second DA converter 12, the first end of any _one of the _N capacitors C _{0 to} C _N-1 may be set to a constant potential, In some cases, a switch corresponding to the capacitive element is not necessary.

  The comparison unit 20 compares the data input to each of the two input terminals, and outputs a comparison signal representing the comparison result to the control unit 30C. In the third configuration example, the comparison unit 20 inputs the first data CTOP1 output from the first DA conversion unit 11 to one input terminal and the second data CTOP2 output from the second DA conversion unit 12 to the other input. Enter at the end. The switch 41 is provided between one input terminal of the comparison unit 20 and the reference level VCM supply line. The switch 42 is provided between the other input terminal of the comparison unit 20 and the reference level VCM supply line. The reference level VCM is, for example, an average value of the first reference potential VREFH and the second reference potential VREFL. Alternatively, the reference level VCM may be set to a value at which the comparison unit 20 can operate with the highest performance (for example, high sensitivity and high SN ratio).

  Based on the comparison signal output from the comparison unit 20, the control unit 30C performs the first control signal and the second control so that the difference between the first data CTOP1 and the second data CTOP2 is reduced at each successive comparison step. A signal is generated, the first control signal is output to the first DA converter 11, and the second control signal is output to the second DA converter 12.

In the AD converter 1C, in the initialization step, with both both turned on CTOP1, CTOP2 the switches 41 and 42 are initialized to VCM, setting of the switches SW _n In a 1DA converter 11 the first input analog data Ain1 each capacitive element C _n is held, the second input analog data Ain2 is held in the capacitors C _n by the setting of the switches SW _n in a 2DA converter 12 by. The AD converter 1C operates as follows, for example, in each successive comparison step after the initialization step.

FIG. 13 is a table for explaining a first operation example of the AD converter 1C. FIG. 13A shows the operation of the first DA converter 11 of the AD converter 1C. FIG. 13B shows the operation of the second DA converter 12 of the AD converter 1C. In this first operation example, N = 8, and the capacitance values of the eight capacitive elements C _{0 to} C ₇ are C. In the first operation example, the connection of each capacitive element is determined based on a thermometer code obtained by decoding Ccode [c2, c1, c0]. Ccode2 given from the control unit 30C to the second DA conversion unit 12 is obtained by inverting the polarity of each bit of Ccode1 given from the control unit 30C to the first DA conversion unit 11.

In the first operation example, in each step of the successive approximation, any of the eight capacitive elements C _{0 to} C ₇ is connected to the first reference potential VREFH or the second reference potential VREFL. The operation of the first DA converter 11 is the same as the sixth operation example of the AD converter 1A described with reference to FIG. The second data CTOP2 output from the second DA converter 12 is a two's complement with respect to the second data CTOP1 output from the first DA converter 11.

FIG. 14 is a table for explaining a second operation example of the AD converter 1C. FIG. 14A shows the operation of the first DA converter 11 of the AD converter 1C. FIG. 14B shows the operation of the second DA converter 12 of the AD converter 1C. Similarly to the case of the first operation example described above, in this second operation example, N = 8 and the capacitance values of the eight capacitive elements C _{0 to} C ₇ are C. Similarly to the case of the first operation example described above, also in the second operation example, the connection of each capacitive element is determined based on the thermometer code obtained by decoding Ccode [c2, c1, c0]. Ccode2 given from the control unit 30C to the second DA conversion unit 12 is obtained by inverting the polarity of each bit of Ccode1 given from the control unit 30C to the first DA conversion unit 11.

In the second operation example, in each successive comparison step, the eight capacitive elements C _{0 to} C ₇ are set to one of the first reference potential VREFH, the second reference potential VREFL, and the open state. The operation of the first DA converter 11 is the same as the seventh operation example of the AD converter 1A described with reference to FIG. The second data CTOP2 output from the second DA converter 12 is a two's complement with respect to the second data CTOP1 output from the first DA converter 11.

  As described above, when the control unit 30C controls the setting of each switch of the first DA conversion unit 11 and the second DA conversion unit 12 for each step of the successive comparison, the first DA conversion unit is provided in any step of the successive comparison. The first control signal and the second control signal instructing to open the first end of any one of the capacitive elements of the 11 and the second DA converter 12 are output. By doing in this way, since the sum total of the capacitance values of the capacitive elements used in the successive comparison can be reduced, the kickback can be reduced. In addition, the period of each step of successive approximation can be shortened, and the AD converter can be speeded up.

  The kickback is large in the first step of the successive approximation and decreases as the step proceeds. Therefore, when the control unit 30C controls the setting of each switch of the first DA conversion unit 11 and the second DA conversion unit 12, the first DA conversion unit 11 and the second DA conversion unit in at least the first step 1 of the successive comparison. It is preferable to output a first control signal and a second control signal instructing to open the first end of any one of the 12 capacitive elements. When the control unit 30C controls the setting of each switch of the first DA conversion unit 11 and the second DA conversion unit 12, each of the first DA conversion unit 11 and the second DA conversion unit 12 increases as the successive comparison step proceeds. The first control signal and the second control signal for instructing to gradually increase the sum of the capacitance values of the capacitive elements having the first end as the first reference potential VREFH or the second reference potential VREFL are output. Is preferred. Further, the control unit 30C sets the first ends of all the capacitive elements of the first DA conversion unit 11 and the second DA conversion unit 12 to the first reference potential VREFH in the last step of the successive approximation or until the last step. Alternatively, it is preferable to output the first control signal and the second control signal instructing to set the second reference potential VREFL.

(Modification)
The present invention is not limited to the above embodiment, and various modifications can be made. The concept of the present invention can be applied to all successive approximation AD converters. For example, a redundant step may be inserted during or at the end of the successive approximation step.

  In the AD converters of the second and third configuration examples described above, the second end of each capacitive element of the DA conversion unit is connected to the input end of the comparison unit, and is connected to the first end of each capacitive element of the DA conversion unit. It was a configuration of bottom plate sampling in which input analog data Ain was input. The AD converter may have a configuration of top plate sampling in which input analog data is input to the second end of each capacitive element of the DA conversion unit connected to the input end of the comparison unit.

1A-1C ... AD converter, 10A, 10B ... DA conversion section, 11 ... first 1DA conversion unit, 12 ... first 2DA conversion unit, 20 ... comparing unit, 30A through 30C ... control unit, 40 to 42 ... switch, _{C 0} ~ C _N-1 ... Capacitance element, SW _{0 to} SW _N-1 ... Switch.

Claims (7)

A successive approximation AD converter that outputs digital data corresponding to input analog data,
It includes a plurality of capacitive elements and a plurality of switches set based on a control signal, and corresponds to the switches of the plurality of capacitive elements by setting all or a part of the plurality of switches. The first end of the capacitive element to be used is any one of the first reference potential, the second reference potential, and the open, and data corresponding to the setting of each of the plurality of switches is shared by the second ends of the plurality of capacitive elements. A DA converter that outputs from the connected output end;
A comparison unit that compares the data output from the DA conversion unit with the input analog data and outputs a comparison signal representing the comparison result;
Based on the comparison signal, a control unit that generates and outputs the control signal so that the difference between the data output from the DA conversion unit and the input analog data is reduced at each successive comparison step;
With
When the control unit controls the setting of each of the plurality of switches of the DA conversion unit, any one of the plurality of capacitance elements of the DA conversion unit in any step of the successive comparison is performed. Outputting a control signal instructing to open the first end;
AD converter. A successive approximation AD converter that outputs digital data corresponding to input analog data,
Including a plurality of capacitive elements and a plurality of switches set based on a control signal, and after holding the input analog data by the plurality of capacitive elements, all or some of the plurality of switches By setting, the first end of the capacitive element corresponding to the switch among the plurality of capacitive elements is set to one of the first reference potential, the second reference potential, and the open, and data corresponding to the setting of each of the plurality of switches A DA converter that outputs a second output of each of the plurality of capacitive elements connected in common, and
A comparison unit that compares the data output from the DA conversion unit with a reference level and outputs a comparison signal representing the comparison result;
Based on the comparison signal, a control unit that generates and outputs the control signal so that a difference between the data output from the DA conversion unit and the reference level is reduced at each successive comparison step;
With
When the control unit controls the setting of each of the plurality of switches of the DA conversion unit, any one of the plurality of capacitance elements of the DA conversion unit in any step of the successive comparison is performed. Outputting a control signal instructing to open the first end;
AD converter. When the control unit controls the setting of each of the plurality of switches of the DA conversion unit, at least the first step of the successive comparison, the capacitance element of any of the plurality of capacitance elements of the DA conversion unit Output a control signal instructing to open the first end of
The AD converter according to claim 1 or 2. When the control unit controls the setting of each of the plurality of switches of the DA conversion unit, the first end of the plurality of capacitive elements of the DA conversion unit is set to a first reference as the successive comparison step proceeds. Outputting a control signal instructing to gradually increase the sum of the capacitance values of the capacitive elements to be the potential or the second reference potential;
The AD converter of any one of Claims 1-3. A successive approximation AD converter that outputs digital data corresponding to a difference between first input analog data and second input analog data,
A plurality of capacitive elements and a plurality of switches set based on a first control signal, and after holding the first input analog data by the plurality of capacitive elements, all or one of the plurality of switches. Setting each of the plurality of switches by setting the first end of the capacitive element corresponding to the switch among the plurality of capacitive elements as one of the first reference potential, the second reference potential, and the open. A first DA converter that outputs first data corresponding to the first data from an output terminal formed by commonly connecting the second terminals of the plurality of capacitive elements;
A plurality of capacitive elements and a plurality of switches set based on a second control signal, and after holding the second input analog data by the plurality of capacitive elements, all or one of the plurality of switches. Setting each of the plurality of switches by setting the first end of the capacitive element corresponding to the switch among the plurality of capacitive elements as one of the first reference potential, the second reference potential, and the open. A second DA converter that outputs second data corresponding to the second data from an output terminal formed by commonly connecting the second terminals of the plurality of capacitive elements;
A comparison unit that compares the first data with the second data and outputs a comparison signal representing the comparison result;
A control unit that generates and outputs the first control signal and the second control signal based on the comparison signal so that the difference between the first data and the second data is reduced at each successive comparison step. When,
With
The control unit controls the setting of each of the plurality of switches of the first DA conversion unit and the second DA conversion unit, and the first DA conversion unit and the second DA conversion unit in any step of the successive comparison. Outputting a first control signal and a second control signal instructing to open a first end of any one of the plurality of capacitive elements;
AD converter. The control unit controls the setting of each of the plurality of switches of each of the first DA conversion unit and the second DA conversion unit, at least in the first step of the successive comparison, the first DA conversion unit and the second DA conversion unit Outputting a first control signal and a second control signal instructing to open a first end of any one of the plurality of capacitive elements of each of the units;
The AD converter according to claim 5. When the control unit controls the setting of each of the plurality of switches of the first DA conversion unit and the second DA conversion unit, the first DA conversion unit and the second DA conversion unit progress as the successive comparison step proceeds. A first control signal and a second control signal instructing to gradually increase the sum of the capacitance values of the capacitive elements having the first end as the first reference potential or the second reference potential among the plurality of capacitive elements are output. ,
The AD converter according to claim 5 or 6.

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