JP2012244521A - Comparator and ad converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a comparator and an ADC that operate at high speed and with high accuracy.SOLUTION: An existing comparator takes longer time to produce a stable comparison result with decreasing difference between two input voltages input into the comparator, and can only produce a two-valued output. A state to the stable comparison result is normally called a metastable state. The present invention positively utilizes the metastable state. Specifically, detecting the metastable state leads to an intermediate determination between high and low levels. This can readily implement a comparator adapted to output three or more values. The comparator of the present invention can reduce the number of comparators used and can complete a comparison operation in a normally incomplete state of determination to help a speed improvement, and applications include a high speed and high accuracy apparatus such as an ADC (analog-digital converter).

Description

  The present invention relates to a comparator and an AD converter having the same.

  Conventionally, various comparators (comparators) used for analog-digital (AD) converters (hereinafter referred to as “ADC”) have been developed and proposed. Patent Document 1 discloses a technique for shortening and speeding up the time in the metastable state (undecided state) with a two-stage comparator in order to improve the judgment time of the comparator. Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique that includes two comparators having different comparison values, and adopts a comparator determination signal output earlier among the two comparators.

  As is clear from these prior arts, in general, a comparator requires a certain delay time depending on accuracy until a reliable comparison result is output after a signal to be compared is input. At present, comparators are used in many devices that are required to operate at high speed, such as AD converters, and therefore it is desired to improve the operation speed of the comparators.

  Here, the operation of the conventional clock synchronous comparator 100 will be described with reference to FIG. (A clock-synchronized comparator is a comparator that performs a comparison operation when the clock signal is high (low), and resets the initial value of either high or low when low (high). The comparator 100 has input terminals clk and Vin and Vip, and has output terminals C + and C−. When clk is low, a reset is applied, and the comparator 100 shifts to an initial state, and at the same time holds the previous comparison result. When clk goes high, a comparison operation is started and the polarities of Vin and Vip are determined. For example, if the voltage of Vin is lower than the voltage of Vip, a high level signal is output from the output terminal C +. If the voltage of Vin is higher than the voltage of Vip, a low level signal is output to the output terminal C +. The output terminal C- outputs an inverted signal of the output terminal C +.

  When clk goes high, the input signals Vin and Vip are input to the differential amplifier circuit 110, and the corresponding output signals cp and cn are output. cp and cn become digital signals IP and IN via NOT circuits 121 and 122, respectively. The signals IP and IN are latched by an SR (Set Reset) latch circuit composed of NOR circuits 131 and 132 connected to each other. The latched signals are taken out as output signals C + and C− of the comparator 100, and hold the previous comparison result while clk is low. In this specification, Vin is treated as a negative input and Vip is treated as a positive input, so that the comparator output outputs a high level when Vin <Vip. However, the reverse is also possible.

  FIG. 2 is a diagram showing an example of a specific circuit of the differential amplifier circuit 110 in FIG. VDD indicates a power supply line, and GND indicates a ground. As shown in FIG. 2, the transistors 210 to 220 are connected, and the operation starts at the rising timing of the clock signal clk and is reset at the falling timing. A clock signal is input to each of the gate terminals of the transistors 210, 211, 218, and 219, and when it goes low, the differential amplifier circuit is reset. The clock signal is also input to the gate terminal of the transistor 220, and the differential amplifier circuit 110 starts operating at the rising timing of the clock. In this embodiment, the transistors 210, 211, 218 and 219 are pMOS transistors, and the transistor 220 is an nMOS transistor. Therefore, even when the same clock signal is input, the on / off operations of the transistors 210, 211, 218, and 219 and the transistor 220 are reversed. That is, when clk is low (L), the nMOS transistor 220 is turned off and the operation of the differential amplifier circuit 110 is stopped. At this time, the transistors 210, 211, 218 and 219 are turned on and the differential amplifier circuit 110 is turned on. Is reset. When clk is high (H), the transistors 210, 211, 218 and 219 are turned off, and the differential amplifier circuit 110 is released from the reset state and accepts an input signal. At this time, the nMOS transistor 220 Is turned on and the differential amplifier circuit 110 starts operating.

  Input signals Vin and Vip are input to the gate terminals of the transistors 217 and 216, respectively. The transistors 212 to 215 differentially amplify the input signals Vin and Vip and output them as cp and cn.

  This operation is an example, and the present invention can be applied to any comparator that is synchronized with the clock signal input (the above-mentioned clock synchronous comparator).

  3A to 3C are diagrams showing the behavior of the outputs cp and cn of the differential amplifier circuit 110 in FIG. FIGS. 3D to 3F show the waveforms of the corresponding clock signals clk.

  FIG. 3A shows the behavior of the outputs cp and cn when the absolute value | ΔVin | of the difference between the input signals Vin and Vip is relatively large. The outputs cp and cn are both connected to VDD at the time of rising of the clock signal (d) because they are both connected to VDD by the immediately preceding reset operation. However, the difference is gradually amplified and the clock signal (d) At the time of falling, a sufficiently large difference is generated to output the comparison result. In this way, when the difference between cp and cn is sufficiently large, the latch circuit 131 shown in FIG. 1 outputs a reliable comparison result.

  FIG. 3B shows the behavior of the outputs cp and cn when the absolute value | ΔVin | of the difference between the input signals Vin and Vip is smaller than that in FIG. In this case, the time required for the voltage difference between the outputs cp and cn to be amplified to a sufficient value is relatively longer than in the case of FIG. Therefore, the difference between the outputs cp and cn is small even when the clock (e) falls, so that the comparison result cannot be reflected in the latch circuit 131 at the subsequent stage, and the previous determination result is used as it is. For this reason, the comparator 100 outputs an erroneous determination result with a relatively high probability.

  FIG. 3 (c) shows an example in which the comparison time is set longer by slowing down the clock signal (f) or increasing the duty ratio of the clock in order to avoid the malfunction in FIG. 3 (b). Yes. In this case, when the clock signal (f) falls, the voltage difference between the outputs cp and cn is sufficiently large, so that the latch circuit 131 in the subsequent stage is normally rewritten and the occurrence of malfunction can be prevented. .

  In this way, as can be understood from the example shown in FIG. 3, when the absolute value | ΔVin | of the difference between the input signals Vin and Vip is small, it takes a long time to obtain a comparison result in the comparator. . In other words, this means that the state in which the comparison result is not determined becomes longer. A state in which this comparison is not determined is referred to as a metastable state.

  In order to avoid such an increase in comparison time, in Patent Document 1, the comparator has a two-stage configuration of a first-stage comparison circuit section and a second-stage comparison circuit section connected in series. The first-stage comparison circuit unit operates at the first clock timing, and outputs a high-level or low-level output voltage as a comparison output according to a comparison determination result between the level of the input signal and the reference level, and compares While the determination is not finished, the signal being amplified is output as it is and input to the second-stage comparison circuit unit. The second stage comparison circuit unit operates at a second clock timing delayed from the first clock timing, and the comparison output of the first stage comparison circuit unit is used for comparison with a value different from the intermediate level output voltage. Compared with the voltage, a comparison output is output according to the comparison determination result, and the comparison output of the determination result is held by itself.

  In Patent Document 2, the comparator circuit compares the input signal with a first comparison value and generates a first determination signal having a determination result, an input signal, A second differential amplifier circuit section that compares the first comparison value with a second comparison value different from the first comparison value and generates a second determination signal having a determination result; An output selection circuit unit that detects which of the first and second determination signals is generated first, selects the previously generated signal, and outputs the selected signal as a determination signal.

  Non-Patent Document 1 discloses ADC technology using a comparator. This non-patent document 1 discloses an asynchronous AD conversion technique using a signal indicating that a comparator has completed determination of an input signal and a comparison result has been obtained. As described above, since the comparison operation time in the comparator varies depending on the magnitude of | ΔVin | which is the absolute value of the difference between the input signals, an appropriate comparison according to the input signal is performed using the signal that the determination is completed. By allocating time to each comparison operation, the reliability of the comparison result is improved while reducing the total comparison time required for one AD conversion.

  However, in the techniques disclosed in Patent Document 1 and Patent Document 2 described above, a plurality of comparators must be provided in order to reduce the time required for comparison, and the circuit configuration of the entire comparator is complicated. .

  Further, in the technique disclosed in Non-Patent Document 1, the reduction in the time required for the determination by the comparator is merely a reduction in the average value of the comparison determination time in the ADC, and a plurality of times required for AD conversion multiple times. It does not shorten the time of each comparison operation. Further, when the determination time is long, it is necessary to abort the comparison when a certain value is exceeded. When the comparison is terminated, the previous output result is used as it is as the output result at this time, and the output accuracy of the AD conversion itself may be lowered.

  Therefore, it is desired to realize a highly accurate comparator that operates at high speed.

JP 2010-288111 A JP 2010-45579 A

Shuo-Wei Michael Chen and Rohert W. Brodersen “A 6-bit 600-MS / s 5.3-mW Asynchronous ADC in 0.13 μm CMOS”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 12, DECEMBER 2006

  An object of the present invention is to solve the above-described problems of the prior art. That is, an object of the present invention is to realize a highly accurate comparator that operates at high speed. Another object of the present invention is to realize an applied device such as an ADC that operates at high speed and with high accuracy by using the comparator. In addition, the subject of this invention is not limited to said point.

  A comparator according to an embodiment is a comparator (400) that compares a first input signal (Vin) and a second input signal (Vip) in synchronization with a clock signal, and that is an internal state of the comparator. A high level state (Z1), a low level state (Z5), and N middle level states representing N (N is a natural number) levels (Z2 to Z4) between the high level state and the low level state. The comparator (400) receives the first input signal (Vin) and the second input signal (Vip), and the first input signal (Vin) and the second input signal. A differential amplifier circuit section (110, 121, 122) corresponding to (Vip) and outputting the amplified first differential amplified signal (IP) and second differential amplified signal (IN), A first clock counter of the clock signal; Differential amplifier circuit section (110, 121, 122) that starts operation at the timing (rise of clk1) and finishes operation at the second clock timing (fall of clk1) of the clock signal, and the first Operates based on the differential amplification signal (IP) and the second differential amplification signal (IN), and compares the first differential amplification signal (IP) and the second differential amplification signal (IN). The first latch portion (Latch) that latches and outputs the value as the first comparison value (C), and the first differential amplification signal (IP) and the second differential amplification signal (IN). N values (delay variable units 413 and 1713) obtained by delaying a value (417) obtained by comparing the first differential amplification signal (IP) and the second differential amplification signal (IN). 1714) at the third clock timing. The second latch unit (1 bit TDC, 2 bit TDC) including N latch circuits (415, 1715, 1716) that latch at the rise of clk2 and output as the second N comparison values (Mout, M1, M2) And based on the first comparison value (C) and the second N comparison values (Mout, M1, M2), the high level state, the low level state, and the N number of comparison values Provided by the comparator (400, 1700), where the middle level condition is determined. It should be noted that the above “delay” includes a delay amount = 0 (for example, when there is no delay variable unit 413 in the embodiment).

  The present invention is also provided by an ADC using the comparator of the present invention. Note that the above description in parentheses is added for reference to one embodiment of the present invention described in detail below, and does not limit the present invention.

  The application field of the comparator of the present invention is not limited to ADC.

  According to the present invention, a high-speed and high-precision comparator can be realized. Also, a device using the comparator of the present invention (for example, ADC) can be realized at high speed and with high accuracy. The effect of the present invention is not limited to this description.

It is a figure which shows the comparator of a prior art. It is a figure which shows the differential amplifier circuit in the comparator of a prior art. It is a figure which shows the behavior of the response of the differential amplifier circuit in the comparator of a prior art. It is a figure which shows one Example of the comparator of this invention. It is the figure which showed the method of calibrating the ternary output comparator which outputs a middle level. It is a figure which shows a capacitive load delay circuit as an example which changes delay amount. It is a figure which shows the relationship between the setting of a reference voltage, and the speed of a differential amplifier circuit. It is the figure which showed the example which provided the variable type load capacity in the inside of a comparator. It is a figure explaining the Example which correct | amends the offset value of a comparator. It is a figure which shows the method of performing the feedback control for performing offset adjustment automatically. It is the figure which showed the example which implement | achieves a hysteresis comparator using a middle level. It is a figure which shows the Example which mounted the hysteresis comparator. It is the figure which showed one Example of the successive approximation type ADC which employ | adopted the comparator of this invention. It is a figure which shows the example of the state change of 2 step sequential ADC. It is a figure which shows the flash type ADC using the comparator of this invention. It is a figure which shows the pipeline type ADC using the comparator of this invention. It is a figure which shows one Example of the comparator whose output exceeds 3 values. It is a figure which shows operation | movement in one Example of the comparator whose output exceeds 3 values.

  FIG. 4 is a diagram showing an embodiment of the comparator 400 of the present invention. The comparator 400 of one embodiment is roughly divided into two parts. That is, the comparator 400 has the input signals Vin and Vip and the clock signal clk1 as input terminals and operates by the comparison unit 100 that outputs the comparison output C, the signal IP and the signal IN of the comparison unit 100, and the clock signal clk2. A metastable detector 410 that outputs the states of the signal IP and the signal IN as metastable output (Mout). Although clk1 and clk2 are assumed to be synchronized, different clock timings may be used. For this reason, it should be noted that different notations are used as clk1 and clk2.

  The configuration of the comparison unit 100 may be the same as the configuration illustrated in FIG.

  The configuration of the metastable detector 410 is as follows. The determination detection unit 411 includes an exclusive NOR circuit that receives the signals IP and IN of the comparison unit 100 as inputs. Those skilled in the art will understand that a circuit using this exclusive NOR can be replaced by EXOR, NOR, NAND, or the like depending on the circuit configuration. The output 417 of the determination detection unit 411 is input to the delay variable unit 413. The output 418 of the delay variable unit 413 is input to the latch 415. The latch 415 inputs the clock signal clk2 to the clock input terminal. Therefore, the latch 415 latches the signal of the delay variable unit 413 at the rising timing of the clock signal clk2, and outputs it as a metastable output (Mout).

  FIG. 4B shows a truth table including the state of the signal 417 immediately before the delay variable unit 413 of the embodiment shown in FIG. That is, when both the signals IP and IN are L or both are H, it is determined that the outputs cp and cn of the differential amplifier circuit 110 remain close to each other. In this case, the output 417 of the determination detection unit 411 is H (“1”) in any state. In addition, when the signals IP and IN are L and H, respectively, or when the signals IP and IN are H and L, respectively, the signal 417 is L (“0”). This state represents a state in which the voltage difference between the outputs cp and cn of the differential amplifier circuit 110 has become sufficiently large, and the comparison output C correctly reflects the comparison result of the input signals Vin and Vip. It can be judged that it is in a state.

  5 uses the metastable output (Mout) as the output of the comparator in the embodiment shown in FIG. 4, and outputs an intermediate value M in addition to H and L as the output of the comparator 3 It is the Example which showed the method of calibrating a value output comparator.

  In FIG. 5, (a) shows an ideal operating state of the comparator. That is, two values of H or L are output according to the voltage difference input to the comparator.

  On the other hand, as shown in FIG. 5B, in the case of an input voltage in the vicinity where the polarity to be determined is switched (in the case where there is no offset, the voltage difference is near zero), as shown in FIG. There is a region where the output is not stable. This is indicated as M501. The reason why such an unstable input region occurs is as already described with reference to FIG. That is, when the input voltage difference is small, it takes a long time until the voltage difference between the outputs cp and cn of the differential amplifier circuit is sufficiently amplified, so that an accurate comparison result cannot be obtained at the end of the comparison time. This is because the metastable state continues.

  This metastable state can be extracted as a signal 417 in FIG. Then, when the clock signal clk2 rises via the delay variable unit 413, the delayed signal 417 is latched by the latch 415, and this is taken out as a metastable output (Mout). The delay variable unit 413 and the latch 415 constitute a 1-bit TDC (Time to Digital Converter). When this metastable output (Mout) is taken out as H (“1”), it indicates a metastable state, and therefore, an intermediate value between the low level (L) and the high level (H) of the comparison output C, that is, the middle What is necessary is just to employ | adopt as an output of the comparator 400 as a level (M).

  If the delay amount of the delay variable unit 413 is increased, the value of the earlier signal 417 is latched in the latch 415 and output as a metastable output (Mout). This means that the input range in which the metastable output (Mout) indicates the metastable state is widened. Therefore, by increasing the delay amount, as shown in FIG. 5D, the range that the middle level can take is increased.

  The above means that the output range of the middle level with respect to the input voltage difference can be adjusted without changing the comparator operation by adjusting the delay amount of the delay variable unit 413. If the delay amount is adjusted and an input signal in which the input voltage difference is evenly distributed within the input range is given, for example, if the output becomes a middle level with a probability (ratio) of 1/3, With respect to the input voltage difference, the output of the comparator, H, M, and L can be equally output by 1/3. This state is shown in FIG. In this way, it is understood that the comparator can be easily calibrated to the state shown in FIG. 5C (a favorite state) by manipulating the delay amount. Thus, a comparator that outputs three values of H, M, and L can be realized. Alternatively, the possible range of the middle level is increased by reducing the delay time of clk2 with respect to clk1. That is, those skilled in the art will understand that reducing the delay time of clk2 relative to clk1 has the same effect as increasing the delay amount.

  Therefore, the delay amount of the delay variable unit 413 may be zero (that is, the delay variable unit 413 may not be provided).

In the above description, the embodiment in which the ratio at which the middle level M is output is performed by adjusting the delay amount of the delay variable unit 413 (or adjusting the delay time of clk2 with respect to clk1) has been described. In addition to this, there are the following methods for increasing the rate at which the middle level M is output, including the case of increasing the delay amount.
(A) Increase the delay amount Δt of the delay variable unit 413 inside the metastable detection circuit unit (or decrease the delay time of clk2 relative to clk1).
(Ii) Shorten the comparison time (iii) Decrease the operation speed of the comparator Note that the methods (a) to (iii) can be used alternatively or in combination with respect to all the embodiments. It should be noted that the present invention is not limited to a specific embodiment. Hereinafter, these methods will be described.

[(A) Increase the delay amount Δt of the delay variable unit 413 inside the metastable detection circuit unit (or decrease the delay time of clk2 relative to clk1)]
This point has already been explained. Therefore, here, a method of changing the delay amount will be supplementarily described.

  FIG. 6 shows a variable load delay circuit as an example of changing the delay amount. The NOT circuits 601 and 602 are connected in series, the variable capacitance element 603 is connected to the connection point, and the other end is connected to a fixed potential such as ground. By changing the capacitance of the variable capacitance element 603, the operation speed of the connection circuit between the NOT circuits 601 and 602 can be adjusted. Therefore, the signal delay amount between the terminals A and B can be changed by changing the capacitance of the variable capacitance element 603. Another method is to change the number of delay elements connected in series by using a selector with a plurality of delay elements connected in series with a delay element connected with two NOT circuits as one unit. (Not shown). Other variable delay elements can be used as appropriate.

[(I) Shorten comparison time]
Next, a method for changing the ratio of the middle level M in FIG. 5 by changing the comparison time will be described. This method uses the principle described in FIG. That is, by making the comparison time longer as shown in FIG. 3C, the comparison determination operation is normally terminated even for a small input voltage difference ΔVin, and L or H is set as the comparison result of the comparator. It is possible to obtain. This means that if the comparison time is shortened, the input range in which the metastable output signal (Mout) indicates the metastable state becomes wider with respect to the input signal. Therefore, the middle level ratio in FIG. 5 may be adjusted by adjusting the comparison time. The comparison time can be adjusted by changing the clock frequency or changing the duty ratio of the clock clk1. In particular, when changing the duty ratio of the clock clk1, the width of the middle level can be adjusted without changing the overall operation speed. These comparison times can be changed by appropriately adjusting the clock circuit (not shown).

[(U) Reduce the operation speed of the comparator]
A method of changing the ratio of the middle level M in FIG. 5 by reducing the operation speed of the comparator will be described. This method also uses the principle described in FIG. 3, and corresponds to equivalently shortening the comparison time by slowing down the operation speed of the comparator. The middle level width may be controlled using this. Note that the operation speed of the comparator can be reduced by changing the bias condition of the comparator or increasing the number of load elements. This point will be described in the following (u-1) and (u-2).

[(U-1) Change bias conditions]
The bias condition is a condition relating to the voltage of the DC component applied to the differential amplifier circuit. When the voltage level at which the polarities of the input voltage 1 and the input voltage 2 measured by the comparator are switched is defined as the reference voltage of the differential amplifier circuit, the current flowing through the transistors in the differential amplifier circuit is changed by changing the reference voltage. And the operation speed of the differential amplifier circuit can be controlled. The reference voltage is generally adjusted by a circuit preceding the differential amplifier circuit, but the reference voltage may be changed on the comparator side (immediately before the differential amplifier circuit).

  FIG. 7 is a diagram illustrating the relationship between the setting of the reference voltage and the speed of the differential amplifier circuit. Vcm indicates a reference voltage of the input signal, and Va indicates a voltage difference between the voltage of the input signal Vin and the voltage of Vip at a certain timing.

  FIG. 7A1 shows the voltage of the input signal Vin and the voltage of Vip when the reference voltage Vcm1 = 250 mV. FIG. 7A2 shows the behavior of the outputs cp1 and cn1 of the differential amplifier circuit 110a when the reference voltage Vcm1 = 250 mV.

  On the other hand, FIG. 7B1 shows the voltage of the input signal Vin and the voltage of Vip when the reference voltage is Vcm2 = 250 mV + Δ. FIG. 7B2 shows the behavior of the outputs cp2 and cn2 of the differential amplifier circuit 110b in this case. Comparing FIG. 7 (b1) and FIG. 7 (b2), it can be seen that increasing the reference voltage increases the speed of the differential amplifier circuit. If the speed of the differential amplifier circuit is reduced, the input range in which the metastable output (Mout) in FIG. 4 indicates the metastable state becomes wider. Therefore, the ratio of the middle level M in FIG. 5 may be changed by manipulating the reference voltage.

  Note that the method for controlling the reference voltage may be adjusted by a circuit preceding the differential amplifier circuit as described above. Alternatively, it may be applied to the input of the differential amplifier circuit via a level shifter circuit (not shown) so that the bias voltage of the input of the differential amplifier circuit can be controlled.

  Note that since the operation parameter of the transistor is also changed by changing the well voltage of the transistor in the differential amplifier circuit, the operation of the differential amplifier circuit may be controlled by changing the well voltage. Since the method of controlling the well voltage is a general matter, a detailed description is omitted here and is not shown.

[(U-2) Increase the load capacity inside the comparator]
By adjusting the load capacity inside the comparator, the middle level ratio in FIG. 5 can be adjusted.

  FIG. 8A shows an example in which load capacitors 801 and 802 are added to the outputs cp and cn of the differential amplifier circuit 110. As a method of adjusting the load capacity, as shown in FIG. 8B, a plurality of capacitors are connected in parallel, and a plurality of switches SW1 to SW3 are operated to change the number of capacitors connected in parallel. be able to. Further, the capacitance can be varied by changing the bias voltage applied (to the voltage control capacitor) using the voltage control capacitor (not shown). Other variable capacitors can be used as appropriate.

  By adding a capacitor in the comparator, the operation speed of the differential amplifier circuit 110 changes. FIG. 8C shows the behavior of the outputs cp and cn of the differential amplifier circuit 110 when the load capacitance is small. FIG. 8D shows the behavior of the outputs cp and cn of the differential amplifier circuit 110 when the load capacitance is large. It can be seen that the larger the load capacitance, the slower the operation of the differential amplifier circuit. If the speed of the differential amplifier circuit changes, the probability that the metastable output (Mout) in FIG. 4 indicates the metastable state will change. Therefore, the ratio of the middle level M in FIG. 5 may be changed by adjusting the load capacity of the comparator.

[Example of comparator offset adjustment]
Hereinafter, an embodiment in which the offset amount of the comparator is corrected using the middle level will be described.

  FIG. 9A shows ideal comparator characteristics. An output of H or L is obtained with the polarity of the input signal as a boundary. On the other hand, the actual comparator has a constant offset as shown in FIG. 9B, and the voltage whose polarity fluctuates is shifted to the (H or) L side (in this example). , It is shifted to the L side, but the same applies to the case where it is shifted to the H side). In this example, the middle level is adjusted, and the middle level is adjusted so that the upper limit value of the middle level is exactly at the center level (FIGS. 9C and 9D). As shown in the truth table of FIG. 9, when the output C of the comparator is L or the output of the metastable output (Mout) is H (“1”), a new signal is generated according to the truth table. L is output. When the output C of the comparator is H and the output of the metastable output (Mout) is L (“0”), a new signal H is output according to the truth table. By linking the logic circuit realizing such a truth table to the output C and metastable output (Mout) of the comparator, a calibrated comparator output as shown in FIG. 9E is obtained.

  In order to set the middle level as described above, any one of the above-described methods (a) to (u) may be used.

  FIG. 10 is a diagram illustrating a feedback control method for automatically performing offset adjustment. The control block 1060 is an example of a logic circuit that implements the truth table 901 in FIG. 9 and is a control block that outputs a binary comparison output 1050 that is finally offset adjusted. The control signal 1065 is used as one or more of a delay amount control signal 1010, a clk2 control signal 1011, a load control signal 1020, a clock control signal 1030, or a reference voltage (bias condition) control signal 1040. May be. The method for adjusting the middle level is as already described with reference to FIG. In the case of the example shown in FIG. 9, the control block 1060 has an output C of L or an output C of H with respect to an input signal that is evenly distributed using the above-described methods (a) to (u). In addition, the feedback amount may be adjusted so that the probability that the output Mout is H (“1”) is 50%. Alternatively, the feedback amount may be adjusted so that the probability that the output signal C is H and the output signal Mout is L (“0”) is 50%.

  Note that control may be performed based on the same concept as described above even when the offset in FIG. 9 is shifted to the H side. One skilled in the art will understand this point.

[Example of realization of hysteresis comparator]
FIG. 11 is a diagram illustrating an example of realizing a hysteresis comparator using the middle level. As shown in FIG. 11C, a middle level width having a required hysteresis width is obtained. Then, depending on the transition state immediately before the comparator, it is determined whether the middle level is combined with the H level or the L level. As a result, a hysteresis comparator can be realized.

  FIG. 12 shows an embodiment in which this hysteresis comparator 1200 is mounted. The output C + of the comparator is input to the first terminal of the OR circuit 1201, and the output Mout is input to the second input of the OR circuit 1201 and the first terminal of the NOR circuit 1202. Further, the output C− of the comparator is input to the second terminal of the NOR circuit 1202.

  The output of the OR circuit 1201 is input to the first terminal of the multiplexer 1210. The output of the NOR circuit 1202 is input to the second terminal of the multiplexer 1210. The output of the multiplexer circuit 1210 becomes the output 1211 of this hysteresis comparator. This output 1211 is latched at the rising timing of the clock by the latch circuit 1230 and input to the selector terminal of the multiplexer 1210 as the signal 1231. As a result, the multiplexer reflects the transition of the previous comparator output 1211, and the operation of the hysteresis comparator indicated by 1250 and 1251 is realized.

[Example of ADC]
There are various ADCs such as a successive approximation ADC, a flash ADC, and a pipeline ADC. Examples in which these ADCs are constructed using a comparator according to the present invention will be described below. Note that the comparator of the present invention is not limited to use in the ADC exemplified in this specification.

[Successive ADC]
FIG. 13 is a diagram showing an embodiment of a successive approximation ADC 1300 employing the comparator of the present invention. The comparator 400 indicates the comparator of the present invention described with reference to FIG. A sample hold circuit 1310 is connected to the input Vin of the comparator 400, and has a function of sampling the analog input at an appropriate timing and supplying the held value to Vin. The output C of the comparator 400 is connected to the SAR logic 1320 including a successive approximation register that sequentially holds the value of the output C (Successive Application Register Logic). The SAR logic 1320 outputs a digital signal 1321 corresponding to the value of the output C that is sequentially taken in, and provides the digital signal to the digital-analog converter DAC 1330. The DAC 1330 outputs an analog signal 1331 converted from the digital signal and supplies the analog signal 1331 to the Vip of the comparator 400. By repeating the above operations sequentially. A digital value asymptotic to Vin appears at output 1321.

  Further, the output Mout of the comparator 400 is supplied to the middle level controller 1340. The middle level controller functions to control the middle level width shown in FIG. 5 to an appropriate value. As a method for adjusting the width of the middle level, the above-described methods (a) to (u) are included. The middle level controller can control the width of the middle level by using at least one of the above (a) to (u). The operating principles (a) to (u) and the middle level adjustment method described above have already been described.

  Here, SARADC in the case of a single phase has been described for the sake of simplification, but the present invention can be similarly applied to a differential configuration. One skilled in the art will understand this point. Various types of SAR logic can be used by those skilled in the art and will not be described in detail herein.

  FIG. 14 is a diagram illustrating an example of a state change of a two-step successive approximation ADC.

  In performing AD conversion, the analog input is sampled and held by the sample and hold circuit 1310. This value is held at the input Vin until AD conversion is completed. Normally, in the bit notation, each time the digit increases, the weight is doubled, but here the first bit (D0) and the second bit (D1) are the same value, and the value is doubled from the third bit (D2). To go. That is, when “D2 D1 D0” is set, the size indicated when each bit is high is D2 = 2 × D1 = 2 × D0. Here, the lowest bit is a fixed value, and by changing the upper 2 bits, a voltage necessary for the DAC is generated. Further, although “011” is used as an initial value here because of superiority in signal processing later, an inverted signal “100” may be used. (Both show the same value.) This will be understood by those skilled in the art.

  First, the operation of Step 1 will be described with reference to FIGS. In FIG. 13, “011” is set as an initial output value in the SAR logic. This value is provided to the DAC 1330 via 1321. The DAC 1330 outputs an analog voltage corresponding to “011” to 1331, and an analog voltage corresponding to the digital value “011” is applied to the input Vip of the comparator 400. This analog voltage value is shown as a voltage value 1450 in FIG. The comparison operation in Step 1 of FIG. 14 is executed with reference to the comparison voltage 1450.

  In the following, since the output C of the same comparator 400 is handled separately according to the operation step, the comparison result of the first step is referred to as C1 and the comparison result of the first step is referred to as C0 for convenience.

  The comparator 400 processes the difference between the voltage of the input Vin and the voltage of the input Vip. When the voltage of (Vip−Vin) is in the range of 1411, 1412, and 1413, respectively, H (C = “1”) Mout = “0”), M (Mout = “1”), and L (C = “0” and Mout = “0”) are output. When it is determined that the voltage of Vin is at the level of 1412, since it is at the middle level, the Mout signal “1” is output and is supplied to the switching circuit 1323, and is included in the current value “011” of the SAR logic circuit. The Mout output “1” added to the end of the first two bits “01” plus “011” is taken out as an AD output. In this case, since it is not necessary to perform subsequent AD conversion, the operation may be terminated.

  When the input Vin is at the level (H) of 1411, the output C1 inputs the level H to the SAR logic 1320, and proceeds to the next step 2. In response to the input of the level H, the SAR logic fetches the current comparison result C1 = "1" into the third bit (D2) of the initial value "011" and the second bit (D1) which is the lower bit thereof ) Is overwritten with “0”, the internal state is set to “101”, and “101” is output to the DAC 1330. This corresponds to the addition of a half value (“010”) of the current DAC generation level (“011”). For this reason, the comparator 400 operates with a value indicated by a reference voltage 1460. When the value of the input Vin is in the range of 1421, 1422, and 1423, the comparator 400 outputs H, M, and L, respectively, in the next comparison operation. In this embodiment, since step 2 is the last step, “110”, “101”, “100” correspond to the case where the value of the input Vin is in the range of 1421, 1422, 1423. Is output. The operation in the SAR logic is that if Mout = “0”, the comparison result C0 of the second step is applied to the second bit (D1), and the output “0” of the current Mout is set to the first bit (D0). Apply. If Mout = “1”, the current value “0” is used as it is for the second bit (D1), the output “1” of the current Mout is applied to the first bit (D0), and “101” is set. The output is SARADC. That is, if C0 = “1”, “1” is applied to the second bit (D1), and the output Mout of Mout is applied to the first bit (D0). The output is SARADC. If C0 = “0”, “0” is applied to the second bit, and Mout output M = “0” is applied to the end, so that “100” is the output of SARADC. When Vin is in the range of 1422, Mout = “1” is output, and the output of SARADC uses the first two digits of the current DAC generation level as it is, and adds Mout output “1” at the end. And "101" is used.

  In step 1, even when the voltage of Vin is 1413 (L), the same processing as described above may be performed with the reference voltage set to 1470.

  As described above, when the first comparison result is C1, the second comparison result is C0, and the determination result of Mout is M, the output “D2 D1 D0” of SARADC can be expressed as “C1 C0 M”. When Mout = “1”, a signal obtained by adding Mout = “1” to the end of the first two digits of the DAC input signal is output as it is using the switching circuit 1323.

  As shown in FIG. 14, the input Vin is converted into a digital value of seven levels by the above processing. When a two-step successive approximation ADC is configured using a normal binary output comparator, four levels of output are obtained. Therefore, by using the three-level comparator of the present invention, a successive approximation ADC with the same accuracy can be realized with a small number of stages. This leads to higher speed and lower power consumption.

  Although the switching circuit is not illustrated, various logic circuits can be appropriately configured by those skilled in the art.

Next, calibration will be described. In order to operate in the most effective range, calibration for appropriately setting the middle level width is necessary. As indicated by the hatched lines in FIG. 14, in the case of two steps, middle level output is used as three AD outputs “101”, “011”, and “001” as AD output. As an example of calibration, an input signal in which “000” to “110” are evenly distributed is given, and one of the seven digital outputs “101”, “011”, or “001” is output. The probability may be set to 3/7. Alternatively, calibration may be performed so that an ideal probability that “101”, “011”, and “001” appear from an input signal having a known probability distribution. Although the present embodiment has been described with two steps, it can be similarly applied to an N-step operation that is an integer of 1 or more. At this time, the most efficient middle level width is the middle level of the entire area width. The area occupied by is represented by (2 ^N −1) / (2 ^{N + 1} −1), and the value gradually approaches 1/2 as the number of steps increases. The middle level width calibration method is not limited to the above example.

In FIG. 14, the width of 1421 and the width of 1433 are wider than the widths of other levels. However, in a normal ADC usage form, the ADC input signal is within the dynamic range of the ADC. Therefore, in practice, all the determination levels are used with the same width, and the influence on the accuracy of the ADC is small. In consideration of this point, when using a signal having an amplitude corresponding to the original full level (in the case where the present invention is not used), the middle level calibration is performed by using 3 / It may be 8. In addition, when a specific input signal cannot be generated, an appearance probability that Mout becomes “1” using a random signal approaches (2 ^N −1) / (2 ^{N + 1} −1) shown above. By performing correction as described above, rough correction may be performed.

[Flash type ADC]
FIG. 15 shows a flash type ADC 1500 using the comparators 400a to 400d of the present invention. In each comparator, an analog input Vana to be measured is connected to one input terminal of the comparator. In order to create a reference voltage, resistors 1521 to 1525 are connected in series, and reference voltages Vref + and Vref− are connected to both ends. In the embodiment, reference voltages of 150 mV, 350 mV, 550 mV, and 750 mV are obtained with an input range of 0 to 900 mV. These reference voltages are connected to the other input terminal of each comparator.

  Each of the comparators 400 a to 400 d provides ternary information to the encoder 1510. (+50 mV or more, within ± 50 mV, -50 mV or less) As a result, from the above four levels of reference voltage and comparator, 0 to 100 mV, 100 mV to 200 mV, 200 mV to 300 mV, 300 mV to 400 mV, 400 mV to 500 mV, 500 mV to 600 mV, 600 mV to Nine determination levels of 700 mV, 700 mV to 800 mV, and 800 mV to 900 mV are obtained. When this is done with a normal comparator, eight reference voltages and comparators are required, so that the required number can be reduced by half.

  The encoder outputs a digital value Vdig from each input information. Any encoder may be used as long as the output of each of the comparators 400a to 400d can be converted into a digital value. A method for mounting the encoder can be appropriately implemented by those skilled in the art, and thus a detailed description thereof will be omitted in this specification.

[Pipeline ADC]
FIG. 16 shows a pipeline type ADC 1600 using the comparator 400 of the present invention. FIG. 16A is an overall view of the pipeline type ADC 1600 of the present invention. The analog input Vin is input to the pipeline circuit 1611 including the 1.5-bit sub ADC. In this embodiment, pipeline circuits 1611 to 1618 are connected in series. Note that 1.5 bits means that there are three possible digital values obtained from the comparator. The output of each pipeline circuit is input to the encoder 1620 and output as a digital output Vdig. Various implementations of the encoder 1620 are available to those skilled in the art and will not be described in detail herein.

  FIG. 16B is a diagram showing a more detailed configuration of the pipeline circuit 1612. That is, the input signal Vin is held by the sample hold circuit 1631. The held signal 1637 is converted to digital by the 1.5-bit ADC 1633 and input to the encoder 1620. Then, the 1.5-bit digital output 1632 is further input to the 1.5-bit DAC and converted again to the analog voltage 1636. The analog voltage 1636 is subtracted from the held signal 1637 by the subtracting element 1638 to obtain a differential voltage 1639. This is doubled by the amplifier circuit 1640 and sent to the pipeline circuit at the next stage. In this way, an error caused by digital conversion in each stage is transmitted as a difference value to the next stage, and AD conversion is repeated in order, so that AD conversion can be performed with accuracy according to the number of stages of the pipeline circuit. FIG. 16C is a specific circuit of a 1.5-bit ADC. As shown in the figure, each pipeline circuit may use one comparator 400 of the present invention. When a normal binary comparator is used, two comparators and a reference voltage generation circuit are separately required (not shown). Therefore, the pipeline type ADC of the present invention can drastically reduce the number of comparators, and improve the operation speed of the comparators and increase the speed as shown in FIG.

[Example of comparator with comparison result exceeding 3 values]
FIG. 17A shows an embodiment of a comparator 1700 that can obtain a 5-level comparison output. Since the embodiment of FIG. 17 is an extension of the embodiment of FIG. 4, the description of the same components as those in FIG. 4 is omitted. In the metastable detection unit 1710 in FIG. 17A, the output 417 of the determination detection unit 411 is input to the 2-bit TDC. The configuration of 2-bit TDC is shown below. The signal 417 is first input to the delay variable unit 1713. The output of the delay variable unit 1713 is input to the latch 1715 and to the delay variable unit 1714. The output of the delay variable unit 1714 is input to the latch 1716. The latches 1715 and 1716 latch the respective input signals at the rising timing of the clock signal clk2, and output them as M1 and M2, respectively. FIG. 17B shows a timing chart of the two clock signals clk1 and clk2. The comparison unit 100 starts the operation at the rising timing t1 of clk1, and ends the operation at the falling timing t2 of clk1. The latches 1715 and 1716 perform a latch operation at t3 which is the rising timing of the clock signal clk2. Here, the delay amount of the variable delay unit 1713 is τ13, and the delay amount of the variable delay unit 1714 is τ14. Output M1 of the latch 1715 would represent the state of the signal 417 in only τ13 from t3 temporally previous time _{t M1.} Then, the output M2 of the latch 1716 would represent the state of the signal 417 at time _{t M2} before from t3 τ13 + τ14 only temporally.

  FIG. 18A shows the relationship between the states of the comparison outputs C, M1, and M2 and the output of the comparator 1700. FIG. 18B shows a truth table for outputting Z1 to Z5 as outputs from the internal state of the comparator 1700 at timing t3. In FIG. 18A, (a1) shows the output of the comparison output C. (A2) shows the output of M1. (A3) shows the output of M2. (A4) shows the outputs Z1 to Z5 as the comparator 1700. A truth table for obtaining these outputs Z1 to Z5 is shown in FIG. By using a logic circuit (not shown) for obtaining Z1 to Z5 in this truth table, Z1 to Z5 can be obtained. Although a logic circuit is not illustrated, those skilled in the art can appropriately configure various logic circuits for realizing the truth table.

  In the embodiment of FIG. 18, Z3 uses the output of M1 as it is, but Z3 can be further divided into two states using the output of M1 and the output of C. In this case, it is possible to finally obtain a 6-level comparison output.

  In addition, if the 2-bit TDC in FIG. 17 is expanded to 3 bits or more, more levels of comparators can be configured. Although this expansion method will not be described in detail, it should be noted that those skilled in the art can appropriately configure the method by referring to FIGS. In addition, it goes without saying that the embodiment of the comparator whose comparison result exceeds three values can be implemented in combination with other embodiments as appropriate.

  As mentioned above, although the Example of this invention was described, the technical scope of this invention which concerns on a claim is not limited to the Example of this specification. In addition, it goes without saying that the present invention includes equivalents thereof. In addition, each embodiment is not exclusive, and the components of each embodiment may be replaced with the components of other embodiments, or may be added to other embodiments.

110 differential amplifier circuit 400 comparator 410 metastable detector

Claims (10)

A comparator for comparing a first input signal and a second input signal in synchronization with a clock signal, wherein an internal state of the comparator is a high level state, a low level state, the high level state, and the low level. N middle level states representing N levels (N is a natural number) in the middle of the state,
The comparator is
The first differential signal and the second differential signal that are inputted with the first input signal and the second input signal and that correspond to the first input signal and the second input signal and are amplified. A differential amplifier circuit unit that outputs an amplified signal, the differential amplifier circuit unit starting operation at a first clock timing of the clock signal and ending operation at a second clock timing of the clock signal;
A value obtained by operating based on the first differential amplification signal and the second differential amplification signal and comparing the first differential amplification signal and the second differential amplification signal is a first comparison value. A first latch unit that latches and outputs as:
The N differential signals are operated based on the first differential amplification signal and the second differential amplification signal, and N values obtained by delaying a value obtained by comparing the first differential amplification signal and the second differential amplification signal A second latch unit including N latch circuits that latch the value of N at a third clock timing and output as a second N comparison values;
Have
Based on the first comparison value and the second N comparison values, the high level state, the low level state, and the N middle level states are determined.
Comparator.   The third N clock timings are determined based on N delay times of N delay variable units connected in series, and outputs of the N delay variable units correspond to the corresponding delay times. The comparator of claim 1, connected to the input of each of the N latch circuits. Controlling an operation time of the differential amplifier circuit by changing a time between the first clock timing and the second clock timing;
The comparator according to claim 1 or 2. By controlling the load capacity of the differential amplifier circuit, the operation speed of the differential amplifier circuit is controlled.
The comparator according to any one of claims 1 to 3.   The comparator according to claim 1, wherein an operation speed of the differential amplifier circuit is controlled by changing a bias condition of the differential amplifier circuit.   By changing at least one of the N delay times, the third clock timing, the operation time, the load capacity, and the bias condition, the N middle level outputs are output. The comparator according to claim 5, further comprising a control unit that adjusts a voltage range of a difference between the first input signal and the second input signal to a predetermined range. N is 1,
A first process in which a logical sum of the middle level state and the low level state is a low level output as a comparison result, and the high level state is a high level output as a comparison result; the middle level state and the high level state; One of the second processing is performed in which the logical sum of the above is a high level output as a comparison result and the low level state is a low level output as a comparison result.
The comparator according to any one of claims 1 to 6.   In the first process, when the output is switched to a high level output, the second process is executed. In the second process, when the output is switched to a low level, the first process is performed. The comparator according to claim 7.   An analog-digital converter using the comparator according to claim 1. The analog-to-digital converter according to claim 9, wherein the analog-to-digital converter is one of a successive approximation type analog-to-digital converter, a flash-type analog-to-digital converter, and a pipeline-type analog-to-digital converter.

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