JP2019008153A - Video display device - Google Patents

Abstract

To provide a video display device in which patterns in a frame rate control table are more inconspicuous.SOLUTION: A signal processing unit is configured to convert a signal A and a signal B having a video signal to be input thinned into signals having the signal A and signal B alternately re-arranged in a time-wise. A driving device comprises a frame rate control unit that allocates an individual frame number in the frame control table to respective data on the signal A and the signal B, and thereby conducts frame rate control. A liquid crystal display element is driven by the driving device, an illumination optical system makes illumination light incident upon the liquid crystal display element, and a projection lens projects modulation light emitted from the liquid crystal display element. When a low order two-bit of the signal A and the signal B stands both 01 or 11, the frame rate control table has the frame rate control pattern different in the continuous signal A and the signal B in the time-wise.SELECTED DRAWING: Figure 13

Description

  The present invention relates to a frame control process in an apparatus that displays a video signal by shifting pixels.

  Japanese Patent Application Laid-Open No. H10-260260 describes that in a device that displays video signals by shifting pixels, frame numbers in the frame control table are separately assigned to respective data of two video signals displayed at different positions. It also describes that the order of the frame rate control tables applied to the two video signals may be interchanged, and different types of patterns may be assigned to the two video signals.

Japanese Patent Laid-Open No. 2015-194596

  However, depending on the pattern of the frame rate control table, the pattern itself may be conspicuous, and further improvement has been desired.

  The present invention provides an image display device in which a pattern in a frame rate control table is less noticeable.

  The present invention thins the input video signal in half horizontally and vertically, generates signals A and B composed of pixels that are deviated from each other by a predetermined number of pixels in the vertical direction and the horizontal direction. A signal processing unit that converts signals that are alternately arranged in time, and a frame rate control that performs frame rate control by separately assigning frame numbers in the frame rate control table to the data of the signals A and B, respectively. A driving device including a unit, a liquid crystal display element driven by the driving device, an illumination optical system that makes illumination light incident on the liquid crystal display element, and a projection lens that projects the modulated light emitted from the liquid crystal display element In the frame rate control table, when the lower 2 bits of the signal A and the signal B are both 01 or 11, In addition, the video display device is characterized in that the same frame rate control pattern is not a continuous pattern between the temporally continuous signal A and the signal B.

  According to the present invention, it is possible to provide a video display device in which the pattern in the frame rate control table is less noticeable.

It is a figure explaining a video display device. It is a schematic block diagram which shows the liquid crystal display device using a reflection type liquid crystal display element. It is a figure for demonstrating the signal processing regarding a video signal. It is a block diagram which shows a drive circuit (drive device). It is a figure for demonstrating gradation expression. It is a figure which shows a frame rate control flow. It is a figure which shows the frame rate control table in 1st Embodiment. It is the figure which showed an example of a response | compatibility with the frame number in an input video frame number and frame rate control. FIG. 5 is a diagram showing an example of a frame rate control table when signal A and signal B are assigned frame numbers in separate frame rate control tables. FIG. 10 is a diagram illustrating an example in which the order of frame rate control patterns is changed between signal A and signal B in FIG. 9. It is the figure which showed an example of a response | compatibility of the input video frame number and frame number in frame rate control in 1st Embodiment. It is the figure which showed an example of a response | compatibility of the input video frame number and frame number in frame rate control in 1st Embodiment. It is the figure which showed an example of the frame rate control table in 1st Embodiment. It is the figure which showed an example of the frame rate control table in 2nd Embodiment. It is the figure which showed an example of the frame rate control table in 2nd Embodiment.

  Hereinafter, a video display device according to the present invention will be described with reference to the accompanying drawings. Hereinafter, a video display device using the liquid crystal display device 100 including the active matrix reflective liquid crystal display element 6 as a display panel will be described as an example.

  FIG. 1 is a diagram for explaining display by a video display device using the liquid crystal display device 100. A video signal is sent from the video signal source 104 to the liquid crystal display device 100. In the liquid crystal display device 100, the video signal is thinned out by a predetermined circuit, converted into time-sequential signals A and B, and then the signals A and B are alternately shifted by a predetermined distance and projected onto the screen 13.

  Next, schematic configurations of the liquid crystal display device 100 and the reflective liquid crystal display element 6 will be described. FIG. 2 is a schematic configuration diagram showing a liquid crystal display device 100 using a reflective liquid crystal display element. The liquid crystal display device 100 generally includes a reflective liquid crystal display element 6, a polarization beam splitter 5 (hereinafter referred to as PBS), and a projection lens 11. The reflective liquid crystal display element 6 has a structure in which a liquid crystal 9 is sealed between a counter electrode (also referred to as a transparent electrode) 10 and a pixel electrode 8.

  Light 2 including S-polarized light 3 and P-polarized light 4 emitted from the illumination optical system 1 enters the PBS 5. Polarized light is separated by PBS5. The S-polarized light 3 is reflected by the polarization separation surface of the PBS 5 and proceeds to the reflective liquid crystal display element 6 side. P-polarized light is transmitted through the polarization separation surface of PBS. The liquid crystal 9 of the reflective liquid crystal display element 6 modulates incident S-polarized light according to the voltage applied between the pixel electrode 8 and the counter electrode 10 by the pixel circuit 7. The S-polarized light incident on the counter electrode 10 is modulated in the process from being reflected by the pixel electrode 8 and being emitted from the counter electrode 10, and is emitted from the counter electrode 10 as light composed of P-polarized light and S-polarized light. In the light emitted from the counter electrode 10, only the P-polarized component, which is modulated light, passes through the PBS 5, and the S-polarized component is reflected by the PBS 5. The P-polarized light that has passed through the PBS 5 is emitted by the projection lens 11, and the emitted light 12 is projected on the screen 13 to display an image.

  FIG. 3 is a diagram showing a flow of signal processing relating to a video signal. A video signal transmitted from the video signal source 104 is input to a signal processing circuit 101 as a signal processing unit. FIG. 3 shows an example in which the video signal has a pixel count of 3840 × 2160 and a synchronization signal frequency of 60 Hz. In the signal processing circuit 101 serving as a signal processing unit, the input video signal is separated into a signal A and a signal B each composed of pixels thinned out in half horizontally and vertically. Here, the pixels constituting the signal A and the pixels constituting the signal B are composed of pixels that are shifted by one pixel both horizontally and vertically on the input video signal. The separated signals A and B are rearranged alternately in time, and the display speed is doubled. The video signal decoded in this way is input to the drive circuit 102. The drive circuit 102 drives the reflective liquid crystal display element 6 based on the decoded video signal.

  Although FIG. 3 shows a state in which the video signal is input at 60 Hz, the frequency is not limited to 60 Hz, and other frequencies (for example, 50 Hz and 24 Hz) may be used. The signal processing circuit 101 converts the video signal into a signal having a double frequency, but the frequency conversion is not limited to double and may be more than that. Also, it may be 1 (same size). The screen resolution may also be other than the number of pixels 3840 × 2160.

  FIG. 4 is a block diagram showing the drive circuit (drive device) 102. FIG. 5 is a diagram for explaining gradation expression. FIG. 5 shows an example of gradation expression in each process unit when the number of bits of input video signal data is 8 bits.

  In FIG. 4, video signal data with N bits input is converted into (M + F + D) bit data larger than N by the look-up table unit 21. Here, M is the number of bits when the number of subframes is expressed in binary, D is the number of bits to be interpolated by the error diffusion processing unit 23, and F is the number of bits to be interpolated by the frame rate control unit 24. . N, M, F, and D are integers.

  In the example of FIG. 5, the number of bits of the input video signal data is 8 bits (N = 8), the number of bits to be interpolated by the error diffusion processing unit 23 is 4 bits (D = 4), and the frame rate control unit 24 The number of bits to be interpolated is set to 2 bits (F = 2). When the number of subframes is expressed in binary, the number of bits is 4 bits (M = 4), and the drive gradation is 12 (not including black).

  Returning to FIG. 4, the video signal data converted into (M + F + D) bits by the look-up table unit 21 is (M + F) bit data by diffusing the lower D bits of information to surrounding pixels by the error diffusion unit 23. Is converted to In the example of FIG. 5, the converted 10-bit data is output by the error diffusion unit 23 by diffusing the lower 4 bits of information to surrounding pixels, quantizing the data into upper 6 bits.

  The video signal data converted into (M + F) bits by the error diffusion unit 23 is input to the frame rate control unit 24. Here, the frame rate control means that m (m: m ≧ 2, natural number) frame is one period for display of one pixel of the display element, and n (n: n> 0, m> n, In this technique, pseudo gradation is displayed by performing on display in a (natural number) frame and performing off display in the remaining (mn) frames. In other words, the frame rate control is a technique for artificially creating an intermediate gradation using rewriting of the screen and the afterimage effect of the retina. For example, when a certain pixel is alternately rewritten to 0 gradation and 1 gradation every frame, it appears to human eyes as an intermediate gradation between 0 gradation and 1 gradation. Then, for example, by controlling such rewriting of 0 gradation and 1 gradation for 4 frames as one set, three levels of gradation are expressed in a pseudo manner between 0 gradation and 1 gradation. become able to.

  FIG. 6 is a diagram showing a frame rate control flow. FIG. 7 is a diagram showing a frame rate control table. The frame rate control unit 24 shown in FIG. 4 includes a frame rate control table. The frame rate control unit 24 specifies the position in the frame rate control table from the lower F bit value, the pixel position information, and the frame count information, and the value (1 or 0, hereinafter 0/1) Are added to the upper M bits and converted to M bit data.

  In the example of FIG. 5, the 6-bit data output from the error diffusion unit 23 is input to the frame rate control unit 24. The frame rate control unit 24 derives a value of 0/1 from the frame rate control table from the lower 2 bits information, the position information in the display area, and the frame counter information, and the upper 4 bits separated from the input 6 bits. Add to the value of the bit.

  The 4-bit data output from the frame rate control unit 24 is limited to 12 which is the maximum value of the drive gradation by the limiter unit 25 shown in FIG. Is converted to 12-bit data to be transferred to the liquid crystal display element 6. The drive gradation table 27 is used for conversion to 12-bit data.

  The 12-bit data output from the subframe data creation unit 26 is stored in the frame buffer 29 divided for each subframe by the memory control unit 28. The frame buffer 29 has a double buffer structure. While data is being stored in the frame buffer 0, the data in the frame buffer 1 is transferred to the reflective liquid crystal display element 6 via the data transfer unit. In the next frame, the data in the frame buffer 0 stored during the previous frame period is transferred to the liquid crystal display element 6 via the data transfer unit 30, and the subframe data of the video signal data input to the frame buffer 1. Output data from the creation unit 26 is stored.

  The drive control unit 31 controls processing timing for each subframe, and performs a transfer instruction to the data transfer unit 30 and control of the gate driver 34. The data transfer unit 30 instructs the memory control unit 28 in accordance with an instruction from the drive control unit 31, receives the designated subframe data from the memory control unit 28, and transfers the data to the source driver 33. Each time the source driver 33 receives data for one line from the data transfer unit 30, it simultaneously transfers the data to the corresponding pixel circuit 7 of the reflective liquid crystal display element 6 using the column data lines D0-Dn. At this time, the gate driver 34 activates the row selection line Wy of the row designated by the vertical start signal (VST) / vertical shift clock signal (VCK) from the drive control unit 31, and all the designated rows y are activated. Data is transferred to the pixels in the column.

  The operation of the frame rate control unit 24 will be specifically described with reference to FIG. The input 6-bit data is divided into upper 4 bits and lower 2 bits. The lower 2 bits of the input 6-bit data, the position information in the pixel display area (that is, the lower 2 bits of the X coordinate and the lower 2 bits of the Y coordinate as coordinate data), the lower 2 bits of the frame counter, The value of “0” or “1” shown in the frame rate control table of FIG. The specified value “0” or “1” is added to the upper 4 bits of data and output as 4 bits of data.

  In order to perform the gradation display assumed for each of the signals A and B, different frame numbers in the frame rate control table are assigned to the signals A and B as shown in FIG. As the video signal, an alternating signal of signal A and signal B is considered. FIG. 9 is a diagram showing a frame rate control table at this time. In FIG. 9 and subsequent figures, the notation “0, 1, 2, 3 of the lower 2 bits of the X coordinate” in FIG. 7 is referred to as “Hscan1, Hscan2, Hscan3, Hscan4”. In addition, the notation “0, 1, 2, 3 in the lower 2 bits of the Y coordinate” is expressed as “Vscan1, Vscan2, Vscan3, Vscan4”.

  As shown in FIG. 9, normal values of 0, 0.25, 0.5, and 0.75 are obtained for all cases where the low-order 2 bit signals are 00, 01, 10, and 11, respectively. That is, since the frame rate control is separately applied to the signal A and the signal B as described above, the correct gradation can be displayed.

  The shift amount of the display positions of the signals A and B is close to 0.5 pixels. For this reason, when the temporally continuous signal A and signal B have the same pattern as in the case of Frame 0 and Frame 1 of the lower bits 01, 10, and 11 in FIG. 9, the pattern continues twice. Therefore, depending on the image to be displayed, the pattern itself may be noticeable.

  FIG. 10 is a diagram when the order of the frame rate control patterns is changed between signal A and signal B. FIG. In the table of FIG. 10, the signal A and the signal B that are temporally continuous are less likely to have the same pattern than the table of FIG. 9. However, for example, when the lower 2 bits are 01, the pattern of the B image of Frame 7 and the pattern of the A image of Frame 0 are the same pattern. In this table, Frame 7 is followed by Frame 0, so that the same pattern continues in temporally continuous signal A and signal B, and the pattern may stand out.

It is desirable that the signals A and B that are temporally continuous do not have the same pattern.
<First Embodiment>
In the first embodiment, in the frame rate control process, the signal A and the signal B that are temporally continuous as much as possible do not have the same pattern in the frame control table of FIG. 7 as shown in FIG. 11 or FIG. To A and B are assigned frame numbers in the frame control table. FIG. 13 is a diagram showing a frame control table when frame numbers are assigned to the signals A and B in the order shown in FIG. According to the first embodiment, when the lower 2 bits are 01 and 11, the temporally continuous signal A and signal B do not have the same pattern. The same applies to the order shown in FIG.

  According to the frame rate control table of the first embodiment, when the lower 2 bits are 01 and 11, the temporally continuous signal A and signal B do not have the same pattern, so the frame rate control pattern is not noticeable. .

<Second Embodiment>
In the second embodiment, the pattern of the frame rate control table when the lower 2 bits are 10 is changed with respect to the first embodiment.

  In the frame control table of the first embodiment, when the lower 2 bits are 10, since two types of patterns are repeated, when the same frame rate control table pattern is used for signal A and signal B, the frame number Even if the order of allocation is shifted, the signal A and the signal B that are temporally continuous may always have the same pattern, and the pattern may stand out. In the second embodiment, the pattern of the frame rate control table when the lower 2 bits are 10 is different for the signal A and the signal B.

  FIG. 14 shows an example of the frame control table when the lower 2 bits are 10. By making the pattern of the frame rate control table different between the signal A and the signal B, the same pattern does not continue between the temporally continuous signal A and the signal B. FIG. 15 shows another example of the frame control table when the lower 2 bits are 10.

  The pattern of the frame rate control table when the lower 2 bits are 10 is not limited to the examples of FIGS. 14 and 15 and can be variously set. It is desirable that the same pixel data be in a black and white reversal pattern. By making the same pixel data in black and white in the temporally adjacent patterns, a gradation of 0.5 can be displayed in two consecutive frames, and the flicker can be made less noticeable. .

  According to the frame rate control table of the second embodiment, when the lower 2 bits are 01, 10, and 11, the temporally continuous signal A and signal B do not have the same pattern, so the frame rate control pattern is Inconspicuous.

  In the first and second embodiments, the number of bits of the input video signal data is N, the number of bits when the number of gradations that can be driven by the display element is expressed in binary, and the number of bits as an error by error diffusion processing. The case where N = 8, M = 4, D = 4, and F = 2 has been described, where D is the number of bits to be diffused and F is the number of bits expressed as a pseudo gradation by frame rate control. . However, the values of N, M, D, and F are not limited to the above values, and various values can be used. Among them, it is more preferable that N = 8 to 12, M = 4 to 6, D = 4 to 8, and F = 2 to 3.

DESCRIPTION OF SYMBOLS 1 Illumination optical system, 6 Reflective type liquid crystal display element, 9 Liquid crystal, 11 Projection lens,
13 screen, 21 lookup table, 22 signal converter,
23 error diffusion unit, 24 frame rate control unit,
100 projection type liquid crystal display device, 101 signal processing circuit (signal processing unit),
102, 1020 Drive circuit (drive device), 104 Video signal source

Claims (3)

The input video signal is thinned out in half horizontally and vertically, and signals A and B composed of pixels that are shifted by a predetermined number of pixels in the vertical and horizontal directions are generated. A signal processing unit for converting the signal into a rearranged signal;
A drive device comprising a frame rate control unit for performing frame rate control by separately assigning frame numbers in a frame rate control table to the data of each of the signals A and B;
A liquid crystal display element driven by the driving device;
An illumination optical system for making illumination light incident on the liquid crystal display element;
A projection lens that projects the modulated light emitted from the liquid crystal display element. The frame rate control table is a temporally continuous signal when the lower 2 bits of the signal A and the signal B are both 01 or 11. A video display device characterized in that A and signal B have different frame rate control patterns. 2. The video display apparatus according to claim 1, wherein the frame rate control table has different frame rate control patterns for the signal A and the signal B when the lower two bits of the signals A and B are both 10. . In the frame rate control table, when both of the lower 2 bits of the signal A and the signal B are 10, the pattern in which the same pixel data is reversed in black and white between the patterns applied to the signals A and B that are temporally adjacent to each other The video display device according to claim 2, wherein: