JP2007033522A - Image output device and image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image output device for embodying a low-priced image display device which is free of a flicker etc., and has high resolution and high display quality without requiring a high-speed data transmission means. <P>SOLUTION: The image output device of the present invention includes subframe generating means (5, 6, and 1 to 4) of dividing pixel data for one frame into a plurality of subframes and outputting the subframes, one by one, in sequence, and field data generating means (1 to 4, 7, 8, 9, and 10) of dividing an output period of each subframe with time into a plurality of fields and generating and outputting output pixel data in sequence, field by field. The field data generating means divide output of pixel data for one frame into a plurality of divided frame periods and a plurality of sub-frames are output in sequence in each divided frame period, each subframe being output while the field data are dispersed to divided frame period so that the output of all field data is completed in an output period of one frame. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention divides pixel data for one frame into a plurality of subframes, and includes an image output device including subframe generation means for sequentially outputting each subframe, and the image output device, and a plurality of images. The present invention relates to an image display device that performs time-division display by dividing into sub-frames.

  In recent years, the resolution of a display image has been increased more and more due to a dramatic increase in the processing capacity of a computer, and accordingly, there is an increasing demand for higher resolution in an image display apparatus such as a projector. However, for example, in projectors and the like, the resolution of the spatial light modulation element for displaying an image has not kept up with the demand, and various techniques for realizing high resolution have been proposed. As an example, Patent Document 1 discloses a projector having optical path shifting means (herein, “shift” is synonymous with “deflection” (hereinafter the same)).

In this prior art, an optical path modulation element as an optical path shift means comprising a polarization direction control panel and a crystal plate is provided in a projection optical path from a display liquid crystal panel as a spatial light modulation element, and the polarization direction control panel is operated. This changes the polarization direction of the light incident on the quartz plate. The crystal plate is arranged with its crystal axis tilted with respect to the optical axis of the projection light, and the optical path shifts for polarized light that vibrates in the tilt direction, and no shift occurs for orthogonal polarized light. .
In this prior art, one frame image is composed of two or four fields (here, “field” is synonymous with “subframe” (hereinafter the same)), and each field is displayed on the liquid crystal panel. In addition to the time-division display, the polarization direction control panel is operated in synchronization with the display, and the optical path is shifted by one pitch or less of the pixels, thereby displaying an image with a resolution higher than that of the liquid crystal panel.

  In many projectors including the above-described conventional technology, a liquid crystal display panel is used as a spatial light modulation element for forming a projection image. In general, a liquid crystal display panel forms an image by applying a voltage corresponding to pixel data to be displayed on each pixel. FIG. 23 shows a configuration example of a conventional liquid crystal display panel.

  In FIG. 23, (P1, 1) to (Py, x) represent each pixel. Each pixel has a pixel driving transistor and a storage capacitor, and constitutes an active matrix circuit as a whole. The gate driver sequentially selects pixels in units of one line in the horizontal (x) direction. The source driver outputs video data of an analog voltage input in synchronization with the selected line to each corresponding pixel. The gates of the pixel driving transistors in the selected line are turned on, and video data output from the source driver is written into the storage capacitor. A liquid crystal is sandwiched between a counter substrate on which an active matrix circuit, a source driver, and a gate driver are formed, and a counter substrate. The optical state of each pixel is controlled based on the written video data, and an image as a whole is displayed. It is formed.

  In many cases, pixel data is generated as digital data, and a voltage applied to each pixel is generated by converting digital pixel data into an analog signal by a digital / analog converter (D / A converter). . On the other hand, with the recent increase in image resolution, pixel data transfer has been further accelerated. As an effective means for that purpose, there is a method in which pixel data is transferred to a display panel as digital data and converted into an analog signal by incorporating a D / A converter in a source driver, for example, on a circuit board. However, the D / A converter has a dramatically complicated circuit configuration as the number of bits of digital data increases, and the display panel is increased in size and cost due to a decrease in yield and an increase in circuit area. There's a problem. In recent years, pixel data of 8 bits or more has become mainstream in order to obtain a high-quality image with high gradation of a display image.

As a method for maintaining the gradation performance while suppressing the complexity of the D / A converter, a gradation display method combining voltage gradation and time gradation is disclosed in Patent Document 2.
In this prior art, among the m-bit digital pixel data inputted from the outside, the upper n bits are used as information for generating an analog voltage to be applied to the pixel, and the lower (mn) bits are used for time gradation. Use as information. Specifically, one frame is composed of 2 ^mn subframes for time gradation, and the voltage supplied to each pixel in each subframe is generated by converting from the upper n bits.

Japanese Patent No. 2939826 JP 2000-310980 A

  The present inventor (the applicant) first maintains a high-gradation and high-quality image display in an image display device that divides an image of one frame into a plurality of subframes and sequentially performs time-division display for each subframe. On the other hand, an image output apparatus has been proposed for further reducing the cost by suppressing an increase in the scale of the drive circuit. In this image output apparatus, specific means for generating and outputting output pixel data has been proposed. In addition, an image display device provided with the above-described image output device, which divides an image of one frame into a plurality of subframes and sequentially time-divides each subframe, and displays high-quality images with low cost and high gradation. Has been proposed (Japanese Patent Application No. 2004-15918).

  More specifically, this prior application technique is related to an image display element that displays an image according to output pixel data from the image output device, a light source and an illumination device that illuminate the image display element, and an output light from the image display element. An optical path deflecting means for deflecting the optical path and an optical device for expanding the light emitted from the optical path deflecting means and projecting the projected light onto the projection surface, and aligning one frame of pixel data from the image output device with the number of pixels of the image display element The sub-frame is divided into a plurality of sub-frames, sequentially output and time-divisionally displayed on the image display element, and the optical path deflecting unit deflects the optical path of the emitted light corresponding to the sub-frame image display, An image display device that displays a frame image having an apparently larger number of pixels than the number of pixels of the image display element by synthesizing the frame display images by shifting the display positions on the projection surface. And an image display device having a gray scale display means combining Makaicho. A specific example will be briefly described with reference to FIGS.

  FIG. 24 shows a state in which a display image by an arbitrary pixel of the image display element is multiplied by four times by the optical path deflecting element and projected onto the screen, and FIG. A one-frame image projected and displayed on top is shown as an example. FIG. 26 shows a display operation example of each pixel of the image display element. In FIG. 26, Tf is a one-frame display period, Tsf1 to Tsf4 are display periods of subframes 1 to 4, Tfd1 to Tfd4 are display periods of respective fields, and Trst is a period for setting the display to a predetermined gradation level when subframes are switched. Is shown. This figure shows a case where the minimum gradation level, that is, black display is used as the predetermined gradation level.

  In the case of the above example, assuming that the frame frequency is 60 Hz (Tf = 16.7 ms) as a general value, the subframe frequency is 240 times (Tsf = 4.2 ms), and the field frequency is further four times that value. It becomes extremely high at 960 Hz (Tfd = 1.05 ms). Therefore, in order to transmit the pixel data so as to follow such a high-speed field frequency, there is a problem that an extremely expensive data transmission means is required or the power consumption increases for high-speed operation. Depending on the number of pixels of the image to be displayed, it may be difficult to realize.

  In order to solve such a problem, a method of reducing the frame frequency to, for example, a half of 30 Hz is conceivable. In that case, the apparent subframe frequency is also reduced to a half or less. Therefore, another problem arises that the flickering of the screen is noticeable depending on the display image. For example, when an alternate repeating pattern of white lines and black lines as shown in FIG. 27 is to be displayed by the pixel multiplication method as shown in FIG. 24, the corresponding pixels are displayed as one sub-display of black and white. The display is alternately repeated at a frequency that is a half of the frame period, and a flicker is conspicuous due to a synergistic effect with the display luminance (gradation) difference. FIG. 28 shows a display operation example of each pixel of the image display element in this case.

The present invention solves the above-described problems in the image display device described in the prior application, does not require a high-speed data transmission means, and does not cause flickering or the like. It is a first object (problem) to provide a low-cost image display device and an image output device for realizing the image display device.
Moreover, this invention makes it the 2nd objective (issue) to provide the means which prevent generation | occurrence | production of said flicker etc. more reliably.

In addition, in the case of displaying one frame image by combining the subframe display images that are time-divisionally projected for each subframe using the optical path shift means by shifting the display positions on the projection surface, the optical path shift is performed. When the image switching speed of the image display element is not sufficient with respect to the speed of the image, the so-called image crosstalk in which the sub-frame image before the optical path shift is displayed in the sub-frame image after the optical path shift occurs, and the image quality deteriorates. May cause.
Accordingly, the third object (problem) of the present invention is to provide means for preventing image quality deterioration due to image crosstalk and obtaining a higher quality image in the above image display apparatus. is there.

In general, an image display element using a TN (Twisted Nematic) liquid crystal has a characteristic that when a display image is updated, the larger the gradation difference between the images before and after the update, the faster the response. However, in the image display device described in the prior application, since the display gradation difference between the fields is small, a sufficient response speed cannot be obtained depending on the display element, and a desired gradation display performance cannot be obtained. Problems may arise.
Therefore, the present invention has a fourth object (problem) to solve the above-described problems, and a drive voltage that has a gradation difference larger than the gradation that should be originally displayed when the field is switched. By applying and overdriving, the response speed of the image display element is increased to obtain a desired gradation display performance.

  Furthermore, in addition to the above object, the present invention is newly added to an image display apparatus provided with initialization means for providing a display period of the predetermined gradation level between the display of the subframes. The fifth object (problem) is to minimize the number of constituent means and prevent the cost from increasing.

As means for solving the problems, the present invention employs the following technical means.
The first means of the present invention comprises subframe generation means for dividing pixel data for one frame into a plurality of subframes and sequentially outputting each subframe, and a plurality of output periods for each subframe. In the image output device having field data generating means for time-dividing the field into fields, generating output pixel data for each field, and sequentially outputting the output pixel data, the field data generating means outputs a plurality of pixel data for one frame. The frame is divided into divided frame periods, and the plurality of subframes are sequentially output within each divided frame period, and each subframe is configured to output each field data so that output of all field data is completed in the output period of the one frame. The output is performed while being distributed over the divided frame period (claim 1).
According to a second means of the present invention, in the image output apparatus of the first means, the field data generation means comprises means for enabling the generation order of the plurality of field data to be set for each subframe. (Claim 2).

According to a third means of the present invention, the image output device of the first or second means, an image display element that displays an image according to output pixel data from the image output device, and illuminating the image display element A light source and an illuminating device; an optical path deflecting unit that deflects an optical path of light emitted from the image display element; and an optical device that magnifies and projects the emitted light from the optical path deflecting unit onto a projection surface, The display time is divided into the plurality of divided frame times, and the subframe display images time-divisionally projected within each divided frame time are combined with the display position shifted on the projection plane, and each subframe is The plurality of fields are distributed and displayed so that a desired image corresponding to the pixel data is displayed in the display period of the one frame.
According to a fourth means of the present invention, in the image display device of the third means, the field data generating means of the image output device is provided in an image region formed by a plurality of pixels adjacent to each other on the projection surface. When the same image is displayed, the field data display order of each subframe is set so that the temporal change amount of the spatially averaged display gradation level of the area becomes small. It is characterized (claim 4).

  According to a fifth means of the present invention, the image output device of the first or second means, an image display element for displaying an image in accordance with output pixel data from the image output device, and illuminating the image display element A light source and an illuminating device; an optical path deflecting unit that deflects an optical path of light emitted from the image display element; and an optical device that magnifies and projects the emitted light from the optical path deflecting unit onto a projection surface, The subframe display image that is time-divisionally projected for each frame is synthesized by shifting the display position on the projection plane to display the one-frame image, and each subframe is further divided into a plurality of fields, A desired gradation display is performed in one sub-frame period by performing time-division projection with predetermined gradations, respectively (claim 5).

According to a sixth means of the present invention, in the image display device of the fifth means, each pixel data of the one-frame image is m-bit pixel data, and the upper n bits (m>) of the m-bit pixel data n) and lower (mn) bits, each of the subframes is divided into 2 ^mn fields, and each field is the upper n bits based on the value of the lower (mn) bits. By displaying gray scales using output pixel data generated from the values of the values, a desired gray scale display is performed by averaging over the display period of the one subframe.
According to a seventh means of the present invention, in the image display device of the sixth means, the output pixel data is n-bit data which is either the upper n-bit value as it is or a value obtained by adding 1. A desired gradation display is performed by averaging over the display period of the one subframe.

According to an eighth means of the present invention, in the image display device according to any one of the third to seventh means, an initial period is provided so as to provide a display period of a predetermined gradation level between the display of the subframes. (8).
According to a ninth means of the present invention, in the image display device according to any one of the third to eighth means, the image display element includes a liquid crystal layer and an electrode for driving the liquid crystal layer on a silicon backplane. It is LCOS (Liquid Crystal On Silicon) in which a portion is formed (claim 9).

According to a tenth means of the present invention, in the image display device of any one of the third to ninth means, an overdrive driving means is provided to increase the response speed of the image display element at the time of switching of the field. (Claim 10).
According to an eleventh means of the present invention, in the image display apparatus of the tenth means, an initialization means is provided so as to provide a display period of the predetermined gradation level between the display of the subframes. The initialization means also serves as the overdrive driving means (claim 11).

According to a twelfth means of the present invention, in the image display device according to the eighth or eleventh means, the predetermined gradation level is a minimum gradation level.
According to a thirteenth means of the present invention, in the image display device of the eighth or eleventh means, the predetermined gradation level is a maximum gradation level.

In the image output device of the first means of the present invention, the pixel data for one frame is divided into a plurality of subframes, the subframe generating means for sequentially outputting each subframe, and the output period of each subframe. Field data generating means for time-dividing into a plurality of fields, generating output pixel data for each field, and sequentially outputting the output data is provided. The field data generating means outputs pixel data for one frame into a plurality of divided frame periods. Dividing and sequentially outputting the plurality of subframes within each divided frame period, and each subframe outputs each field data in the divided frame period so that output of all field data is completed in the output period of the one frame. Therefore, it is necessary to provide high-speed data transmission means by using this image output device. Not, moreover it never occur flickering, it is possible to realize a high display quality and low price image display device with high resolution.
In the image output apparatus of the second means of the present invention, in addition to the configuration of the first means, the field data generation means can set the generation order of the plurality of field data for each subframe. By providing such a means, the temporal change in display gradation due to field switching can be spatially averaged between adjacent pixels to cancel, and high-quality image display with less noticeable flickering can be realized. It becomes possible.

  In the image display device of the third means of the present invention, the image output device of the first or second means, an image display element for displaying an image in accordance with output pixel data from the image output device, and the image display A light source and an illuminating device that illuminate the element; an optical path deflecting unit that deflects an optical path of the outgoing light from the image display element; and an optical device that enlarges the outgoing light from the optical path deflecting unit and projects the light onto a projection surface. , The display time of the one frame is divided into the plurality of divided frame times, and the sub-frame display images time-divisionally projected within each divided frame time are combined with the display positions being shifted from each other on the projection plane, The sub-frame is characterized in that the plurality of fields are distributed and displayed so that a desired image corresponding to the pixel data is displayed in the display period of the one frame. Each sub-frame is displayed in a plurality of times, and each field can be displayed in a distributed frame display time so that a series of field display is completed over the entire display time of one frame. Even if the display time of the frame becomes long, that is, even if the frame frequency is lowered, the sub-frame frequency is apparently maintained. Therefore, by reducing the frame frequency, the transmission rate of the pixel data can be reduced, thereby reducing the cost of the device. In addition, it is possible to realize an image display device with high display quality in which flickering is not noticeable while maintaining an apparent subframe frequency.

  In the image display device of the fourth means of the present invention, in addition to the configuration of the third means, the field data generating means of the image output device is formed by a plurality of pixels adjacent to each other on the projection plane. When the same image is displayed in the image area, the field data display order of the subframes is set so that the temporal variation of the spatially averaged display gradation level of the area is reduced. When displaying each subframe divided into a plurality of times, for example, when all the subframes display the same gradation image, the spatial average value of the display gradation levels is The field output order in a series of sub-frame displays is set for each sub-frame so that it is uniform in time. The change in tone can be canceled by spatial averaging between adjacent pixels, is inconspicuous even more flicker, it is possible to achieve very high quality image display apparatus.

In the image display device of the fifth means of the present invention, the image output device of the first or second means, an image display element for displaying an image according to output pixel data from the image output device, and the image display A light source and an illuminating device that illuminate the element; an optical path deflecting unit that deflects an optical path of the outgoing light from the image display element; and an optical device that enlarges the outgoing light from the optical path deflecting unit and projects the light onto a projection surface. The sub-frame display image that is time-divisionally projected for each sub-frame is synthesized by shifting the display position on the projection plane to display the one-frame image, and each sub-frame further includes a plurality of fields. The desired gradation display is performed in one sub-frame period by time-division projection with predetermined gradations, so that high-quality images with high gradation and high-quality flicker are not noticeable. An image display device capable of image display can be realized at low cost.
In the image display devices of the sixth and seventh means of the present invention, in addition to the configuration of the fifth means, the output pixel data is n bits (n <m) with respect to m-bit pixel data. As a result, the circuit scale of the D / A converter is reduced, and a specific cost reduction is achieved.

Furthermore, in the image display device according to the eighth means of the present invention, in addition to the configuration of any one of the third to seventh means, a display period of a predetermined gradation level between subframes is displayed. In order to prevent the occurrence of crosstalk between subframes, it is possible to prevent the occurrence of image crosstalk between subframes. High quality images can be obtained.
Furthermore, in the image display device of the ninth means of the present invention, in addition to the configuration of any one of the third to eighth means, a liquid crystal layer and an electrode for driving the liquid crystal layer on a single crystal silicon backplane as an image display element LCOS with a display portion including a high-speed driving circuit can be formed on the silicon backplane, and the liquid crystal layer can be formed very thin to achieve a high optical response speed. High-speed image switching every time is easily realized.

Further, in the image display device of the tenth means of the present invention, in addition to the configuration of any one of the third to ninth means, at the time of switching of the field, a gradation larger than the gradation to be originally displayed. Since the driving means for overdriving by applying the driving voltage as a difference is provided, the response of the image display element is speeded up and an image display device with excellent gradation display performance is realized.
Furthermore, in the image display apparatus according to the eleventh means of the present invention, in addition to the structure of the tenth means, an initial period for providing a display period of the predetermined gradation level between the subframes is displayed. Since the initialization means also serves as the overdrive driving means, a low-cost and high-quality image display apparatus can be realized without adding a new configuration.

In the image display apparatus of the twelfth means of the present invention, in addition to the configuration of the eighth or eleventh means, the display image is shifted to the lowest gradation level, that is, black display, especially when the subframe display is switched, and the optical path is shifted. As a result, a clear display image with high contrast can be obtained.
In the image display apparatus of the thirteenth means of the present invention, in addition to the configuration of the eighth or eleventh means, the display image is set to the maximum gradation level, that is, white display, particularly when the display of the subframe is switched, and the optical path. Since the shift is made, the light utilization efficiency is increased, and the luminance is reduced and the power consumption is reduced.

  Hereinafter, the configuration, operation, and operation of the image output apparatus and the image display apparatus according to the present invention will be described in detail based on the illustrated embodiments.

[Example 1]
First, an embodiment of an image output apparatus according to the present invention will be described.
FIG. 1 is a block diagram schematically showing a configuration example of an image output apparatus according to the present invention. The image output device divides pixel data for one frame into a plurality of subframes, and outputs subframes sequentially for each subframe (decoder 5, write control circuit 6, subframe memories 1-4). Field data generation means (subframe memories 1 to 4, readout control circuit 7, +1 circuit) that time-divides the output period of each subframe into a plurality of fields, generates output pixel data for each field, and sequentially outputs the output pixel data 8, determination circuit 9 and selection circuit 10).

In FIG. 1, a signal DVI is an input image signal formatted in the DVI standard, which is one of digital image data transmission standards. The decoder 5 decodes the input image signal DVI and outputs m-bit pixel data Di (m), its synchronization clock WCK, and horizontal / vertical synchronization signal HDi / VDi.
The input image is, for example, an image having the number of pixels N in the horizontal direction M and the vertical direction as shown in FIG. 2, and (x, y) represents the xth pixel in the yth line in the vertical direction. Pixel data is sequentially input from one line to N lines in order, and in each line, from the top (1, y) to (M, y) in order, one pixel or a plurality of pixels.

  The write control circuit 6 generates and outputs the write address WA and the selection signals CS1 to CS4 of the subframe memories 1 to 4 from the synchronization clock WCK and the horizontal / vertical synchronization signal HDi / VDi output from the decoder 5, respectively. FIG. 3 is a timing chart of input / output signals for explaining the operation of the write control circuit 6. Here, the write address WA is composed of a horizontal address portion WA (x) and a vertical address portion WA (y).

  FIG. 3A shows the relationship between the horizontal / vertical synchronization signal HDi / VDi and the vertical address portion WA (y). The vertical synchronization signal VDi is a signal that becomes “H” level for a predetermined time at the start timing of pixel data input for one frame, and the horizontal synchronization signal HDi is “H” for a predetermined time at the start timing of pixel data input for one line. It is a signal that goes to “level”. The value of the vertical address portion WA (y) of the write address WA increases by 1 every two cycles of the horizontal synchronization signal.

  FIG. 3B shows the relationship among the horizontal synchronization signal HDi, the horizontal address portion WA (x) of the write address WA, the synchronization clock WCK, and the selection signals CS1 to CS4. The synchronization signal WCK transitions to the “H” level in synchronization with each input pixel data Di (m). The value of the horizontal address part WA (x) of the write address WA increases by 1 every two cycles of the synchronization signal WCK. The selection signal CS1 of the sub-frame memory 1 becomes “H” level with respect to the odd-numbered pixel data from the beginning of the odd-numbered line of the input image. The selection signal CS2 of the sub-frame memory 2 becomes “H” level with respect to even-numbered pixel data from the beginning of the odd-numbered line of the input image. The selection signal CS3 of the sub-frame memory 3 becomes “H” level for the odd-numbered pixel data from the top of the even-numbered line of the input image. Then, the selection signal CS4 of the subframe memory 4 becomes “H” level with respect to the even-numbered pixel data from the top of the even-numbered line of the input image.

  The sub-frame memories 1 to 4 are memories for storing four sub-frames 1 to 4 for dividing and displaying one frame of the input image, and each of the sub-frame memories 1 to 4 is “H”. The input pixel data Di (m) is stored based on the write address WA. The subframe 1 belongs to an odd-numbered line of the input image and includes odd-numbered pixels from the top of each line. The subframe 2 belongs to an odd-numbered line of the input image and includes even-numbered pixels from the top of each line. The subframe 3 belongs to the even-numbered lines of the input image and is composed of odd-numbered pixels from the top of each line. The subframe 4 belongs to even-numbered lines of the input image and is composed of even-numbered pixels from the top of each line. FIG. 4 shows a pixel array of each subframe image. In this embodiment, the number of subframes is four, but it is not limited to this. The same applies to the pixel arrangement of the subframe.

  The read control circuit 7 generates a read address RA from the synchronization clock WCK and the horizontal / vertical synchronization signal HDi / VDi output from the decoder 5, and OE1 to OE4 which are output enable signals of the subframe memories 1 to 4, respectively. It generates and outputs a signal SFC whose value changes when the count value FC of the field constituting each subframe and the reading of pixel data from the subframe memories 1 to 4 make a round. Here, the read address RA is also composed of a horizontal address portion RA (x) and a vertical address portion RA (y), like the write address WA.

  5, FIG. 7 and FIG. 8 show timing charts of respective signals for explaining the operation until pixel data is read from the subframe memories 1 to 4 and outputted. In these figures, Tf is a pixel data output period for one frame, Tsf is a pixel data output period for one subframe, and Tfd is a pixel data output period for one field for time gradation display of one subframe. (The same applies to the subsequent figures).

  First, in FIG. 5, OE1 to OE4 sequentially become “H” level with a time width of Tsf / 2. In the subframe memories 1 to 4, when the output enable signals OE1 to OE4 are at “L” level, the outputs Di1 (m) to Di4 (m) are in a high impedance state, and OE1 to OE4 are at “H” level. The pixel data written at this time is read out sequentially based on the read address RA. Here, the subframe memories 1 to 4 are preferably a memory having a dual port function capable of reading asynchronously with writing, but a single port memory can also be used. The corresponding subframe pixel data is repeatedly read twice during a period in which one output enable signal is “H”, and the value of the field count value FC changes each time.

  The upper n bits Di (n) of the pixel data read from any one of the subframe memories 1 to 4 are either left as they are, or 1 is added by the +1 circuit 8 (Di (n) +1), respectively. 10 is input. On the other hand, the lower (mn) bits of the pixel data read from any of the subframe memories 1 to 4 are input to the determination circuit 9. The determination circuit 9 controls the state of the output signal S based on the lower (mn) bits of the pixel data, the field count value FC, and the divided frame count value SFC. The selection circuit 10 selects either input data Di (n) or Di (n) +1 based on the value of the signal S and outputs it as output pixel data Do (n). FIG. 6 shows an output example of pixel data for each field when the lower order (mn) is 2 bits.

  FIG. 7 shows the relationship between the vertical synchronizing signal VDo of the output pixel data Do (n), the vertical address portion RA (y) of the read address RA, and the enable signal. The vertical synchronization signal VDo is a signal that becomes “H” level for a predetermined time at the start timing of pixel data output for one field. When VDo becomes “H”, it corresponds to the enable signal that is “H” at that time. The pixel data is sequentially output from the first line from the subframe memory. In the drawing, only OE1 and OE2 are shown as corresponding enable signals, but the same applies to OE3 and OE4.

  FIG. 8 shows horizontal / vertical synchronization signals HDo / VDo of the output pixel data Do (n), horizontal / vertical address portions RA (x) / RA (y) of the read address RA, and read data from the subframe memory. The relationship of Di (n) is shown. The horizontal synchronization signal HDo is a signal that is at the “H” level for a predetermined time at the start timing of pixel data input for one line. Each time HDo becomes “H”, the pixel data corresponding to each line is sequentially transferred to the subframe memory. Read out.

[Example 2]
Next, another embodiment of the image output apparatus according to the present invention will be described.
FIG. 9 is a timing chart showing another operation example in the configuration example of the image output apparatus according to the present invention shown in FIG. In this figure, the readout of the corresponding subframe pixel data is performed once during the period when one output enable signal is “H”, and the series of readouts of subframes 1 to 4 is performed four times during one frame period. repeat. In this case, the value of the signal FC changes every time a series of reading of the subframes 1 to 4 is finished once, and the value of the signal SFC changes every time a series of reading of the subframes 1 to 4 is finished twice. . The pixel data output for each field when the lower order (mn) of the pixel data is 2 bits may be the same as or different from that in FIG. That is, in the first embodiment, a case where one frame period is divided into two divided frame periods is shown, whereas in this embodiment, a case where one frame period is divided into four divided frame periods is shown.

[Example 3]
FIG. 10 is a block diagram schematically showing another configuration example of the image output apparatus according to the present invention. The basic configuration is the same as the configuration of FIG. 1 described in the first embodiment. The difference between the configuration of FIG. 10 and the configuration of FIG. 1 is that enable signals OE 1 to OE 4 are input to the determination circuit 9. Further, the determination circuit 9 determines whether the data Di (n) read from the subframe memories 1 to 4 is output as it is or is added by 1 by the +1 circuit 8 (Di (n) +1) and output. It has a function to set for each frame. The operation may be the example shown in FIG. 5 or the example shown in FIG. Moreover, it is not restricted to these.

  FIG. 11 and FIG. 12 show an example of pixel data output for each field when the lower order (mn) of the pixel data is the same as FIG. In each of these examples, when the sub-frames 1 to 4 display the same gradation image, the average of the series of sub-frame pixel data is always set to be constant. 5 corresponds to the operation example shown in FIG. 5, and the case of FIG. 12 corresponds to the operation example shown in FIG.

[Example 4]
Next, an embodiment of the image display device according to the present invention will be described.
FIG. 13 schematically shows a configuration example of a projection type image display apparatus as an embodiment of the image display apparatus according to the present invention. In FIG. 13, reference numerals 21 to 23 denote illumination devices including a light source. An integrator optical system 22 of the illumination device includes, for example, a fly-eye lens array, and uniformizes light from the light source 21. The condenser lens 23 is for condensing the illumination light on the spatial light modulation element 25 which is an image display element for illumination. Here, the spatial light modulator 25 is a reflective liquid crystal panel. The drive device 27 includes the image output device having the configuration shown in FIG. 1 or FIG. 10, and divides one frame of display image data into a plurality of subframes (for example, four subframes) and sequentially outputs them. Here, the output of a series of subframe pixel data is repeated a plurality of times within the display time of one frame. At that time, the pixel data of each sub-frame is converted into field data and output so as to obtain a desired gradation display in a display time of one frame.

  The spatial light modulator 25 modulates illumination light incident on each pixel based on pixel data from the driving device 27. The modulated illumination light enters the optical path deflecting element 26 as image light, and is deflected so that the image light is shifted by an amount set in the pixel arrangement direction. The optical path deflecting operation by the optical path deflecting element 26 is controlled by a driving device 28. The polarization beam splitter 24 is for separating illumination light and image light. Further, the outgoing light from the optical path deflecting element 26 is enlarged by the projection lens 29 and projected onto the screen 30.

Here, it is preferable that the optical path deflection amount by the optical path deflecting element 26 is 1 / integer of the pixel pitch. It is preferable to set the pixel pitch to ½ when performing image multiplication twice as much as the pixel arrangement direction, and to ¼ the pixel pitch when performing pixel multiplication four times. In any case, the optical path deflecting element 26 is operated in synchronization with the display image of each subframe generated according to the number of deflecting directions to be switched and displayed on the image display element (spatial light modulation element) 25 to thereby deflect the optical path. By forming a projected image at a display position on the screen corresponding to the operating state of the element 26, an apparently high-definition image can be displayed.
In this embodiment, the configuration example using the reflective spatial light modulator (reflective liquid crystal panel) 25 as the image display device has been described. However, a configuration example using a transmissive image display device is also possible.

FIG. 14 shows a configuration example of LCOS (Liquid Crystal On Silicon) in which a display unit including a liquid crystal layer and an electrode for driving the liquid crystal layer is formed on a silicon backplane as an example of an image display element in the image display device according to the present invention. It is shown schematically. That is, the LCOS uses a silicon substrate (Si substrate) 41 as one of upper and lower substrates enclosing liquid crystal.
More specifically, on the Si substrate 41, a circuit composed of pixel transistors 42 and the like, a light shielding layer 43, and a mirror electrode 44 are formed. A glass substrate 48 on which an ITO counter electrode 47 is formed is disposed opposite to the Si substrate 41, and a predetermined gap (gap) is provided between both substrates by a columnar spacer 45. A liquid crystal layer is formed in the gap. 46 is enclosed.

  FIG. 15 shows a circuit configuration example of a backplane suitable for the image display device based on the present invention. Each pixel driving circuit has a holding capacitor C as a memory for holding analog pixel data, a transistor Q1 as a first switch for controlling the storage of image data in the memory, and the image data stored in the memory. It comprises a transistor Q2 as a second switch for controlling the output to the corresponding pixel P, and a transistor Q3 as means for setting the voltage applied to the liquid crystal pixel to a voltage value of a predetermined gradation. The source driver performs D / A conversion on the pixel data Do (n) output from the image output device, converts the pixel data Do (n) into analog pixel data, and outputs the analog data from corresponding outputs Video_1, Video_2,. The gate driver sequentially drives the line drive signals PV1, PV2,..., PVN, turns on the gate of the transistor Q1 of the corresponding line, and stores the analog pixel data output from the source driver in the storage capacitor C. When data is written in all the pixels, the signal TD is set to the “H” level to drive the transistors Q2 all at once, and the analog pixel data stored in the storage capacitor C is applied to the liquid crystal pixel P. When the subframe is switched, the signal REST is set to the “H” level to drive the transistors Q3 all at once, and the voltage applied to the liquid crystal pixel P is rewritten to a voltage value of a predetermined gradation level. In this embodiment, the ground level is set to zero volts (0 [V]), but other voltage values may be used.

  In this embodiment, the image display element is an LCOS in which a display unit including a liquid crystal layer and an electrode for driving the liquid crystal layer is formed on a silicon backplane. Since the silicon substrate 41 is used for the substrate, A similar microfabrication process can be used, and the above driving circuit can be formed on the same substrate, so that a small and low cost driving circuit can be realized.

  16 to 19, display of each pixel of the spatial light modulator 25 when one frame is divided into four subframes and a frame image is displayed on the screen as shown in FIGS. 24 and 25 by optical path shift. An operation example is shown. In these drawings, Trst indicates a period during which the display is set to a predetermined gradation level when subframes are switched, and FIGS. 16 to 18 show a case where the minimum gradation level is set as the predetermined gradation level, that is, black display is performed. Indicates the maximum gradation level as the predetermined gradation level, that is, the state of white display. [1-0] and [2-1] indicate the display operation corresponding to the value of the lower 2 bits of the pixel data of each subframe. The left number should be the subframe and the right number should be displayed. The lower 2 bits of the image data are indicated (for example, [1-0] is a display operation in which the lower 2 bits of the pixel data in the subframe 1 is “0”).

FIG. 16 is a display operation example of each pixel of the spatial light modulator 25 corresponding to the pixel data output example shown in FIG. 6 of the first embodiment. Shows a case where different images are displayed.
FIG. 17 shows an example of the display operation of each pixel of the spatial light modulator 25 corresponding to the output example of the pixel data shown in FIG. 11 of the third embodiment. FIGS. 18 and 19 show the display operation of FIG. As an example of display operation of each pixel of the spatial light modulator 25 corresponding to the output example of pixel data, a case where an image having the same gradation (lower 2 bits of pixel data is “1”) is displayed in four subframes. Show. These are set so that the average of a series of sub-frame pixel data is always constant when displaying the same gradation image, and FIG. 20 is displayed on the screen corresponding to FIG. FIG. 21 shows a state of an image, and FIG. 21 shows a state of an image displayed on the screen corresponding to FIG. 18 or FIG. That is, in FIG. 20, the display state is repeated between (a) and (b) every half period Tf / 2 of one frame, and in FIG. 21, a quarter period of one frame. The display states of (a) to (d) in the figure are repeated in the order shown in the figure every Tf / 4.

[Example 5]
FIG. 22 is a timing chart based on FIG. 16 showing another operation example of the projection type image display apparatus having the configuration of FIG. 13 shown in the fourth embodiment. In this embodiment, the signal REST is set to the “H” level for the Tod time when the field is switched during the subframe period, and a drive voltage that has a larger gradation difference than the gradation to be originally displayed is applied. It shows a state where the drive is driven to increase the response speed of the image display element. In this embodiment, it is assumed that the initialization means for setting the image display to a predetermined gradation level when the subframe is switched also serves as the overdrive driving means for speeding up the response of the image display element when the field is switched. However, it is not limited to this.

In the image display apparatus of the present embodiment described above, the display image is shifted to the predetermined gradation level when the display of the subframe is switched, so that the crosstalk of the image occurs between the subframes. Can be prevented, and a high-quality image can be obtained.
Further, in the image display device of this embodiment, the display image is shifted to the lowest gradation level, that is, black display, especially when the display of the sub-frame is switched, and the optical path is shifted, so that a clear display image with high contrast can be obtained. It is done.
Further, in the image display device of this embodiment, the display image is shifted to the highest gradation level, that is, white display, especially when the display of the sub-frame is switched, so that the light use efficiency is increased and the luminance is increased. And low power consumption.
Further, in the image display device of this embodiment, since the LCOS in which the display portion including the liquid crystal layer and the electrode for driving the liquid crystal layer is formed on the single crystal silicon backplane is used as the image display element, high speed operation is performed on the silicon backplane. The liquid crystal layer can be formed extremely thin to realize a high optical response speed, and high-speed image switching for each field can be easily realized.

  As described above, according to the present invention, it is possible to realize an image display device capable of displaying a high-quality image with high gradation and high-quality flicker without conspicuous at low cost. It can utilize for various image display apparatuses, such as a display.

1 is a block diagram schematically showing a configuration example of an image output apparatus according to the present invention. It is a figure which shows an example of an input image. 4 is a timing chart of input / output signals for explaining the operation of the write control circuit. It is a figure which shows the pixel arrangement | sequence of each sub-frame image. 3 is a timing chart of each signal for explaining an operation example until pixel data is read from the subframe memory of the image output device shown in FIG. 1 and output. It is a figure which shows the example of an output of the pixel data for each field and subfield when the lower order (mn) of pixel data is 2 bits. 3 is a timing chart of each signal for explaining an operation example until pixel data is read from the subframe memory of the image output device shown in FIG. 1 and output. 3 is a timing chart of each signal for explaining an operation example until pixel data is read from the subframe memory of the image output device shown in FIG. 1 and output. 6 is a timing chart of each signal for explaining another example of operation from when pixel data is read out from the subframe memory of the image output device shown in FIG. 1 to when it is output. It is a block diagram which shows schematically the example of another structure of the image output device which concerns on this invention. It is a figure which shows another output example of the pixel data for each field and subfield when the lower order (mn) of the pixel data is 2 bits. It is a figure which shows another output example of the pixel data for each field and subfield when the lower order (mn) of the pixel data is 2 bits. It is a figure which shows one Example of the image display apparatus which concerns on this invention, Comprising: It is a schematic block diagram which shows the structural example of a projection type image display apparatus. It is a schematic sectional drawing which shows an example of the image display element in the image display apparatus which concerns on this invention. It is a figure which shows the circuit structural example of the backplane suitable for the image display apparatus which concerns on this invention. It is a figure which shows an example of the display operation | movement of each pixel of the spatial light modulation element of the image display apparatus shown in FIG. It is a figure which shows another example of the display operation of each pixel of the spatial light modulation element of the image display apparatus shown in FIG. It is a figure which shows another example of the display operation of each pixel of the spatial light modulation element of the image display apparatus shown in FIG. It is a figure which shows another example of the display operation of each pixel of the spatial light modulation element of the image display apparatus shown in FIG. It is the figure which showed the mode of the image displayed on a screen corresponding to FIG. It is the figure which showed the mode of the image displayed on a screen corresponding to FIG. 18 or FIG. It is a figure which shows another example of the display operation of each pixel of the spatial light modulation element of the image display apparatus shown in FIG. It is a figure which shows the structural example of the conventional liquid crystal display panel. It is a figure which shows a mode that the display image by arbitrary 1 pixels of a spatial light modulation element is multiplied by a 4 times pixel with an optical path deflection element, and is projected on a screen. It is a figure which shows an example of the 1 frame image projected and displayed on a screen. It is a figure which shows an example of the display operation | movement of each pixel of the spatial light modulation element in the image display apparatus of a prior application. It is a figure which shows the example of the alternating repeated pattern of a white line and a black line. It is a figure which shows the example of a display operation of each pixel of an image display element in the case of displaying the pattern of FIG. 27 in the image display apparatus of a prior application.

Explanation of symbols

1-4: Subframe memory 5: Decoder 6: Write control circuit 7: Read control circuit 8: +1 circuit 9: Determination circuit 10: Selection circuit 21: Light source 22: Integrator optical system 23: Condenser lens 24: Polarization beam splitter 25 : Spatial light modulation element (image display element)
26: Optical path deflecting element 27: Driving device 28: Driving device 29: Projection lens 30: Screen 41: Si substrate 42: Pixel transistor 43: Light shielding layer 44: Mirror electrode 45: Columnar spacer 46: Liquid crystal layer 47: ITO counter electrode 48: Glass substrate

Claims (13)

Sub-frame generation means for dividing pixel data for one frame into a plurality of sub-frames and sequentially outputting each sub-frame, and dividing the output period of each sub-frame into a plurality of fields, In an image output device provided with field data generating means for generating output pixel data for each output and sequentially outputting them,
The field data generation unit divides an output of pixel data for one frame into a plurality of divided frame periods, and sequentially outputs the plurality of subframes within each divided frame period. An image output apparatus, wherein each field data is distributed and outputted in the divided frame period so that output of all field data is completed in an output period. The image output apparatus according to claim 1,
The image data output apparatus according to claim 1, wherein the field data generation means includes means for enabling the generation order of the plurality of field data to be set for each subframe.   The image output apparatus according to claim 1, an image display element that displays an image according to output pixel data from the image output apparatus, a light source and an illumination device that illuminate the image display element, and the image display element Optical path deflecting means for deflecting the optical path of the light emitted from the optical path, and an optical device for enlarging and projecting the light emitted from the optical path deflecting means onto the projection surface, and the display time of the one frame is set to the plurality of divided frame times. Sub-frame display images that are time-divisionally projected within each divided frame time and are combined with the display positions shifted on the projection plane, and each sub-frame is the pixel data in the display period of the one frame. An image display device characterized in that the plurality of fields are distributed and displayed so as to display a desired image according to the display. The image display device according to claim 3.
The field data generating means of the image output device, when displaying the same image in an image area formed by a plurality of pixels adjacent to each other on the projection plane, displays a spatially averaged display floor of the area. An image display device, wherein the field data display order of each of the subframes is set so that the temporal change amount of the tone level is small.   The image output apparatus according to claim 1, an image display element that displays an image according to output pixel data from the image output apparatus, a light source and an illumination device that illuminate the image display element, and the image display element Sub-frame which is provided with an optical path deflecting means for deflecting the optical path of the outgoing light from the optical path and an optical device for projecting the outgoing light from the optical path deflecting means on the projection surface in a time-division manner for each sub-frame The display image is synthesized by shifting the display position on the projection surface to display the one-frame image, and each sub-frame is further divided into a plurality of fields, each of which is time-divisionally projected with a predetermined gradation. Accordingly, a desired gradation display is performed in one subframe period. The image display device according to claim 5,
Each pixel data of the one-frame image is m-bit pixel data, and the sub-frames are assigned to upper n bits (m> n) and lower (mn) bits of the m-bit pixel data. 2 fields are divided into ^mn fields, and each field is displayed in grayscale with output pixel data generated from the upper n bits based on the lower (mn) bits. An image display device that performs a desired gradation display on average during a frame display period. The image display device according to claim 6.
The output pixel data is n-bit data which is either the value of the upper n bits as it is or a value obtained by adding 1, and performing desired gradation display on average during the display period of the one subframe. A characteristic image display device. In the image display device according to any one of claims 3 to 7,
An image display apparatus comprising: an initialization unit for providing a display period of a predetermined gradation level between display of the subframes. In the image display device according to any one of claims 3 to 8,
The image display device is an LCOS (Liquid Crystal On Silicon) in which a display unit including a liquid crystal layer and an electrode for driving the liquid crystal layer is formed on a silicon backplane. In the image display device according to any one of claims 3 to 9,
An image display device comprising overdrive driving means for increasing the response speed of the image display element when the field is switched. The image display device according to claim 10.
An image display apparatus comprising: an initialization unit for providing a display period of the predetermined gradation level between the display of the subframes, and the initialization unit also serves as the overdrive driving unit . The image display device according to claim 8 or 11,
The image display apparatus according to claim 1, wherein the predetermined gradation level is a minimum gradation level. The image display device according to claim 8 or 11,
The image display apparatus according to claim 1, wherein the predetermined gradation level is a maximum gradation level.

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