JP2019062125A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a semiconductor element having a MOS structure capable of more accurately obtaining a short circuit withstand capability. A strongly correlated material layer 9 is provided between a gate electrode 8 and a source electrode 11 of a vertical MOSFET. Thereby, when the element heat is generated at the time of short circuit, the strongly correlated material layer 9 functions as a conductor, and the gate and the source of the vertical MOSFET can be electrically connected. Therefore, the voltage of the gate electrode 8 can be reduced, and the short-circuit current flowing in the vertical MOSFET can be cut off, so that the electric power in the vertical MOSFET can be suppressed. Therefore, it is possible to provide a semiconductor device having a vertical MOSFET capable of suppressing the temperature of the vertical MOSFET from increasing in temperature, suppressing the element breakdown of the vertical MOSFET, and obtaining the short-circuit resistance more accurately. it can. [Selection diagram] Figure 1

Description

  The present invention relates to a semiconductor device having a semiconductor element of a MOS structure made of a semiconductor material such as silicon carbide.

In recent years, attempts have been made to improve the on-resistance Ron of power devices, and the on-resistance Ron per unit area has been developed up to 1 mΩcm ² or less.

  On the other hand, when the power device is in a short circuit state, specifically, when the high power supply voltage is applied while the gate of the power device MOSFET is turned on, the MOSFET has a high breakdown voltage, The power of the MOSFET is increased due to the low resistance element. For this reason, in many cases, the time until the element breakdown occurs in a short circuit is shorter than 10 μsec.

  Specifically, in the Vds-Ids characteristic showing the relationship between the drain-source voltage (hereinafter referred to as Vds) and the drain-source current (hereinafter referred to as Ids), Ids in the saturation region is a short circuit in the Vds-Ids characteristic. The value multiplied by Vds is the power. At the time of short circuit, for example, a voltage of 600 to 1200 V or more is applied to the drain as Vds, and the power in the MOSFET becomes very large. In the case of a silicon device, Ids in the saturation region is substantially constant even if Ids increases according to the gate voltage Vg, but in the case of a SiC device, Ids increases with a predetermined gradient even in the saturation region. Power will be even greater. Therefore, the temperature of the MOSFET instantaneously rises, making it difficult to obtain a high short circuit withstand voltage.

  On the other hand, Patent Document 1 proposes a semiconductor device having a structure capable of reducing the power of the MOSFET. In this semiconductor device, the source electrode is made of a material whose resistance value increases under a predetermined high temperature condition, and when an overcurrent flows through the current path formed in the SiC epitaxial layer, the current density is made less than the predetermined value. A limiting variable resistance layer is provided.

  In addition, as a measure for raising the temperature of the MOSFET, the application of the gate voltage Vg can be turned off at the time of occurrence of an overcurrent by a drive circuit using current sensing or the like to suppress element breakdown.

Patent No. 6065303

  However, as in Patent Document 1, the provision of the variable resistance layer can not prevent generation of a large power only by limiting the current density, and a sufficient short circuit resistance can not be obtained.

  Further, even when the application of the gate voltage Vg is turned off by the drive circuit using a current sense or the like, as described above, the time until the element is broken at the time of a short circuit is too short and the application of the gate voltage Vg is properly turned off. There is a problem that it is impossible to prevent the element destruction.

  In addition, although the case where especially high voltage was used as a semiconductor material was used as a semiconductor material was demonstrated here, the same may be said of the other semiconductor materials, especially compound semiconductors, such as GaN, not only SiC.

  An object of the present invention is to provide a semiconductor device having a semiconductor element of a MOS structure capable of obtaining a short circuit withstand voltage more accurately.

  In order to achieve the above object, according to the invention as set forth in claim 1, a substrate (1) of the first or second conductivity type made of silicon carbide, formed on the substrate and having a lower impurity concentration than the substrate A drift layer (2) made of the semiconductor of the first conductivity type, a base region (3) made of silicon carbide of the second conductivity type formed on the drift layer, and a drift region formed on the base region A source region (4) made of silicon carbide of the first conductivity type in which the first conductivity type impurity concentration is higher than that of the layer, and a gate insulating film formed on the surface of the base region between the drift layer and the source region 7), a gate electrode (8) disposed on the gate insulating film, an interlayer insulating film (10) covering the gate electrode and the gate insulating film and in which the contact hole (10a) is formed, and the contact hole Source territory Has a electrically connected to the source electrode (11), a drain electrode formed on the back surface side of the substrate (12), a semiconductor device including the. Further, in such a configuration, a strongly correlated material layer made of a strongly correlated electron material which is conducted between the gate electrode and the source electrode in response to the temperature rise of the semiconductor element to conduct between the gate electrode and the source electrode. (9) is provided.

  Thus, when heat is generated at the time of short circuit, the strongly correlated material layer functions as a conductor, and the gate-source of the semiconductor element of the MOS structure can be conducted. Therefore, the voltage of the gate electrode can be reduced, and the short circuit current flowing to the semiconductor element can be cut off, so that the power in the semiconductor element can be suppressed. Therefore, it is possible to suppress the semiconductor element from becoming high temperature, to suppress the semiconductor element from reaching the element breakdown, and to provide a semiconductor device having the semiconductor element of the MOS structure which can obtain the short circuit withstand capacity more accurately. it can.

  In addition, the code | symbol in the parenthesis of each said means shows an example of the correspondence with the specific means as described in embodiment mentioned later.

1 is a cross-sectional view of a semiconductor device according to a first embodiment. It is the figure which showed the relationship of the temperature T and resistivity rho in a strong correlation material layer. Figure showing the relationship between the ratio of the resistivity と insulator when the strongly correlated electronic material functions as an insulator to the resistivity metalmetal when it functions as a metal (hereinafter referred to as ρinsulator / ρmetal) and the temperature T at which a phase transition occurs It is. It is a circuit diagram of a semiconductor device at the time of temperature rising. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device shown in FIG. 1; FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 5 (a); FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 5 (b); FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 5 (c); FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 5 (d); It is sectional drawing of the semiconductor device concerning 2nd Embodiment.

  Hereinafter, an embodiment of the present invention will be described based on the drawings. In the following embodiments, parts that are the same as or equivalent to each other will be described with the same reference numerals.

First Embodiment
The first embodiment will be described. In the semiconductor device according to the present embodiment, as shown in FIG. 1, a vertical MOSFET is formed as a semiconductor element having a MOS structure. The vertical MOSFET is formed in the cell region of the semiconductor device, and the outer peripheral breakdown voltage structure is formed so as to surround the cell region, but the semiconductor device is configured here, but only the vertical MOSFET is shown here. It is shown. In the following description, the horizontal direction in FIG. 1 is taken as the width direction, and the vertical direction is taken as the thickness direction or the depth direction.

In the semiconductor device, an n ⁺ -type substrate 1 made of SiC is used as a semiconductor substrate. In the case of the present embodiment, the normal direction of the sheet of FIG. 1 is made to coincide with the off direction. As the n ⁺ -type substrate 1, an off substrate having a (0001) Si surface and a predetermined off angle is used, and for example, the off direction is <11-20>. The n-type impurity concentration of the n ⁺ -type substrate 1 is, eg, 1.0 × 10 ¹⁹ / cm ³ .

On the main surface of the n ⁺ -type substrate 1, an n ⁻ -type drift layer 2 made of SiC, a p-type base region 3 and an n ⁺ -type source region 4 are sequentially formed by epitaxial growth or the like.

The n ⁻ -type drift layer 2 has, for example, an n-type impurity concentration of 0.5 to 2.0 × 10 ¹⁶ / cm ³ and a thickness of 5 to 14 μm. Incidentally, n ^- the boundary between the n ⁺ -type substrate 1 of the type drift layer 2, optionally n ^- even each other by the type drift layer 2 to form a partially high concentration and buffer layer 2a good.

The p-type base region 3 is a portion where the channel region is formed, and the p-type impurity concentration is, for example, about 2.0 × 10 ¹⁷ / cm ³ and the thickness is 0.5 to 2 μm. Further, in the case of the present embodiment, the surface layer portion of the p-type base region 3 is a contact region in which the p-type impurity concentration is increased.

The n ⁺ -type source region 4 has a higher impurity concentration than the n ⁻ -type drift layer 2 and has an n-type impurity concentration of, for example, 2.5 × 10 ^{18 to} 1.0 × 10 ¹⁹ / cm ³ in the surface layer portion. It is comprised by about 0.5-2 micrometers.

Further, a p-type deep layer 5 is formed in the surface layer portion of the n ⁻ -type drift layer 2, that is, below the p-type base region 3. The p-type deep layer 5 has a p-type impurity concentration higher than that of the p-type base region 3, and a plurality of the p-type deep layers 5 are arranged at equal intervals and separated from each other without intersecting each other. It is done. For example, each p-type deep layer 5 has a p-type impurity concentration of 1.0 × 10 ^{17 to} 1.0 × 10 ¹⁹ cm ³ and a width of 0.7 μm. Each p-type deep layer 5 has a depth of 0.4 μm or more, and is formed to a position deeper than the trench gate structure described later, thereby suppressing entry of an electric field into the trench gate structure.

In this embodiment, the p-type deep layer 5 is formed only in the surface layer portion of the n ⁻ -type drift layer 2, but the n ⁻ -type source region 4 and the p-type base region 3 are penetrated to form the n ⁻ -type. It may be formed to reach the drift layer 2. For example, a trench can be formed from the surface of the n ⁺ -type source region 4 and the p-type deep layer 5 can be formed to be embedded in the trench.

Also, for example, the width is 0.8 μm and the depth is p-type base region 3 and n ⁺ -type source region so as to penetrate n-type base region 3 and n ⁺ -type source region 4 to reach n ⁻ -type drift layer 2. The gate trench 6 is formed 0.2 to 0.4 μm deeper than the total film thickness of 4. The p-type base region 3 and the n ⁺ -type source region 4 described above are arranged in contact with the side surfaces of the gate trench 6. The gate trench 6 is formed in a linear layout in which the lateral direction in the drawing of FIG. 1 is the width direction, the normal direction in the drawing is the longitudinal direction, and the vertical direction in the drawing is the depth direction. Further, although only one is shown in FIG. 1, a plurality of gate trenches 6 are arranged at equal intervals in the lateral direction of the drawing and are arranged so as to be sandwiched between the p-type deep layers 5 respectively. It is in the form of

A portion of the p-type base region 3 located on the side surface of the gate trench 6 is a channel region connecting the n ⁺ -type source region 4 and the n ⁻ -type drift layer 2 when the vertical MOSFET operates. A gate insulating film 7 is formed on the inner wall surface of the gate trench 6 including the channel region. Further, on the surface of gate insulating film 7, gate electrode 8 made of doped polysilicon is formed. In the present embodiment, the gate electrode 8 is n-type doped, but may be p-type doped. The gate trench 6 is filled with the gate insulating film 7 and the gate electrode 8. Thus, the trench gate structure is configured.

A strong correlation material layer 9 is formed on the gate insulating film 7 and the gate electrode 8. The strong correlation material layer 9 is made of a strong correlation electron material that changes the resistivity [[Ω · cm] according to the temperature of the vertical MOSFET. As the strongly correlated electronic material, for example, a VO-based material is used, and in this case, VO ₂ is used.

  A strongly correlated electron material generally refers to a substance having a strong effective Coulomb interaction among electrons. In the case of this embodiment, among the strongly correlated electron materials, the resistivity ρ [Ω · cm] is changed according to the temperature, and the one in which the resistivity ρ [Ω · cm] becomes lower as the temperature becomes higher is the strongly correlated material layer 9 Used as a material for Such a material functions as an insulator in the normal use environment of the vertical MOSFET, and as the temperature of the vertical MOSFET rises, the resistivity ρ [Ω · cm] decreases and the conductor Act as.

For example, when VO ₂ is applied as a strongly correlated electronic material, the temperature-resistivity characteristic as shown in FIG. 2 is obtained, for example, a temperature range of 100 ° C. or less, a temperature range of 373 K or less in absolute temperature, and a temperature range exceeding that The resistivity ρ [Ω · cm] changes greatly. Specifically, as shown in FIG. 2, when the temperature T is 373 K or less, the resistivity ρ is approximately 10 ⁻¹ to 10 [Ω · cm] and works as an insulator. On the other hand, when the temperature T exceeds 373 K, the phase transition lowers to a resistivity of 10 ⁻³ [Ω · cm] or less, and works as a conductor metal.

  As such a strongly correlated electronic material, a VO-based material can be mentioned, but materials other than the VO-based material can also be used. FIG. 3 shows the relationship between the ratio of the resistivity insinsulator when functioning as an insulator to the resistivity metalmetal when functioning as a metal (hereinafter referred to as ρinsulator / ρmetal) and the temperature [K] at which a phase transition occurs. There is. In this figure, the larger the insinsulator / ρmetal, the stronger the correlation material layer 9 becomes an insulating film with high insulation performance when the strongly correlated electronic material works as an insulator, and it functions as a conductor with a lower resistance value when it works as a metal. Further, the temperature [K] of the phase transition may be higher than the temperature range in normal use of the semiconductor device and lower than the temperature at which the temperature of the vertical MOSFET is raised at the short circuit and element breakdown occurs.

The temperature range in normal use of the semiconductor device differs depending on the use form of the semiconductor device, but for example, when applied to a vehicle etc., it is necessary that the temperature of phase transition be at room temperature (eg 0 K) or more, The temperature of phase transition is preferably 373 K or more. In the case of a VO type strongly correlated electronic material, the temperature of phase transition of V ₄ O ₇ , VO ₂ or the like is equal to or higher than room temperature. In particular, the temperature of phase transition of VO ₂ exceeds 373 K, and in the use environment applied to a vehicle, the strongly correlated material layer 9 functions as an insulator, and when it becomes higher than that, it functions as a metal, that is, a conductor. Can. In addition, depending on the usage of the semiconductor device, the phase transition temperature may be lower than room temperature, and in this case, more kinds of strongly correlated electron materials can be applied as the material of the strongly correlated material layer 9. If it is a VO type strongly correlated electronic material, V ₆ O or the like can also be applied as the material of the strongly correlated material layer 9.

  The gate electrode 8 is formed of polysilicon, and the strong correlation material layer 9 is in contact with the gate electrode 8. Therefore, the strongly correlated material layer 9 functions as a part of the insulating film covering the gate electrode 8 at the normal use temperature of the vertical MOSFET, and is electrically connected to the gate electrode 8 when the temperature of the vertical MOSFET rises. It functions as a conductor.

  In the case of this embodiment, the strong correlation material layer 9 is formed so as to cover the entire gate electrode 8 and extends from the gate electrode 8 onto the gate insulating film 7. It may be formed so as to cover at least a part.

In addition, an interlayer insulating film 10 is formed on the surfaces of the gate insulating film 7, the gate electrode 8, the strongly correlated material layer 9 and the like. A contact hole 10a is formed in interlayer insulating film 10, and the contact region of n ⁺ -type source region 4 and p-type base region 3 is exposed through contact hole 10a. Further, the strongly correlated material layer 9 is partially exposed from the side surface of the portion of the interlayer insulating film 10 which is made to be the contact hole 10 a. The interlayer insulating film 10 is made of an insulating material such as BPSG, and in the case of this embodiment, round processing is performed by heat treatment.

Further, on the interlayer insulating film 10, a source electrode 11, a gate wiring layer (not shown) and the like are formed. Source electrode 11 is in contact with the contact regions of n ⁺ -type source region 4 and p-type base region 3 through contact hole 10 a, and is also in contact with strongly correlated material layer 9. The gate wiring layer is in contact with the gate electrode 8 in a cross section different from that of FIG.

The source electrode 11 and the gate wiring layer are made of a plurality of metals such as Ni / Al. Then, at least a portion of the plurality of metals in contact with the n-type SiC, specifically the n ⁺ -type source region 4 is made of a metal that can make an ohmic contact with the n-type SiC. Further, at least a portion of the plurality of metals in contact with the p-type SiC, specifically the p-type deep layer 5 is made of a metal capable of being in ohmic contact with the p-type SiC. The source electrode 11 and the gate wiring layer are electrically isolated by being separated from each other on the interlayer insulating film 10.

Further, on the back side of the n ⁺ -type substrate 1 n ⁺ -type substrate 1 and electrically connected to the drain electrode 12 are formed. Such a structure constitutes an n-channel type inverted trench gate vertical MOSFET. A cell region is configured by arranging a plurality of such vertical MOSFETs in a plurality of cells. Then, a semiconductor device is configured by configuring an outer peripheral withstand voltage structure such as a guard ring (not shown) so as to surround a cell region in which such a vertical MOSFET is formed.

  In the semiconductor device having the vertical MOSFET configured in this manner, for example, a gate voltage Vg of 20 V is applied to the gate electrode 8 in a state where the source voltage Vs is 0 V and the drain voltage Vd is 1 to 1.5 V It is made to operate by doing. That is, in the vertical MOSFET, a channel region is formed in the p-type base region 3 in a portion in contact with the gate trench 6 by applying the gate voltage Vg, and a current flows between the drain and the source.

  Then, the strong correlation material layer 9 is provided to the vertical MOSFET performing such operation. For this reason, the vertical MOSFET performs different operations in a temperature range of normal use, for example, a temperature range below room temperature or 373 K or less and a temperature range exceeding that.

  First, in the temperature range of normal use, the strongly correlated material layer 9 acts as an insulating material. Therefore, the vertical MOSFET performs the normal operation as described above. Therefore, an operation of flowing a current between the drain and the source through the channel region is performed.

  On the other hand, when the temperature range for normal use is exceeded, the strongly correlated material layer 9 acts as a conductor, and the gate-source of the vertical MOSFET is conducted. That is, it becomes a structure represented by the equivalent circuit of FIG. 4, and it becomes a circuit structure where the gate-source of the vertical MOSFET 20 is conducted.

  As described above, the vertical MOSFET 20 senses the temperature of the strongly correlated material layer 9 and becomes a conductor when element heat generation occurs during a short circuit, thereby enabling instantaneous conduction between the gate and the source. Become. Therefore, the gate voltage Vg is lowered to the source potential, and the vertical MOSFET 20 can be turned off. That is, the vertical MOSFET 20 can be a self turn-off transistor that is automatically turned off at the time of short circuit. Therefore, the short circuit current flowing to the vertical MOSFET 20 can be cut off, the power in the vertical MOSFET 20 can be suppressed, and the temperature rise of the vertical MOSFET 20 can be suppressed. As a result, it is possible to suppress the vertical MOSFET 20 from reaching the element breakdown, and to obtain a semiconductor device having the vertical MOSFET 20 capable of obtaining the short circuit withstand capacity more accurately.

  The semiconductor device of the present embodiment is applied to, for example, an inverter circuit or the like in which the vertical MOSFET 20 is disposed in each of the upper arm and the lower arm.

  The inverter circuit or the like is used, for example, when supplying an alternating current to a load such as an AC motor while using a DC power supply. For example, in the inverter circuit etc., a plurality of bridge circuits in which upper and lower arms are connected in series are connected in parallel to a DC power supply, and the upper and lower arms of each bridge circuit are alternately turned on and off alternately. Supply alternating current.

  Specifically, in each bridge circuit such as an inverter circuit, current is supplied to the load by turning on the vertical MOSFET 20 of the upper arm and turning off the vertical MOSFET 20 of the lower arm. Thereafter, the vertical MOSFET 20 in the upper arm is turned off, and the vertical MOSFET 20 in the lower arm is turned on to stop the current supply. At the time of current supply, the drain voltage is approximately 5 V, but at the time of short circuit, the drain voltage is 600 to 1200 V or more. For this reason, if the vertical MOSFET 20 is in a conductive state at the time of short circuit, the power of the vertical MOSFET 20 becomes excessive and the temperature rises instantaneously, so that the short circuit withstand voltage can not be obtained.

  Further, in order to make the waveform of the alternating current at this time not a rectangular wave but a clear sine wave, it is necessary to switch the vertical MOSFET 20 at higher speed. And in order to enable high-speed switching, it is necessary to reduce the on resistance Ron, but the rise of the Ids becomes steep due to the reduction of the on resistance Ron, and it becomes more difficult to obtain the short circuit withstand capability. In particular, in a SiC device, a high voltage is used as compared to a silicon device, and the device is a device having a high withstand voltage. Therefore, the power of the vertical MOSFET 20 is further increased, and it is difficult to obtain short circuit withstand capability. That is, the short circuit tolerance is in a trade-off relationship with the on-resistance Ron of the vertical MOSFET 20 and the withstand voltage, and as the element performance is improved, the short circuit tolerance becomes difficult to obtain.

  On the other hand, in the semiconductor device of the present embodiment, as shown in FIG. 4, when the vertical MOSFET 20 generates heat at the time of short circuit, the gate-source is immediately conducted to reduce the gate voltage Vg, The short circuit current flowing to the vertical MOSFET 20 can be cut off. Therefore, even if the on-resistance Ron of the vertical MOSFET 20 is lowered or the breakdown voltage is high, it is possible to obtain the short circuit withstand voltage.

  Next, a method of manufacturing a semiconductor device provided with the vertical MOSFET according to the present embodiment will be described with reference to FIGS. 5 (a) to 5 (e).

[Step shown in FIG. 5 (a)]
First, a wafer-like n ⁺ -type substrate 1 is prepared as a semiconductor substrate. Then, an n ⁻ -type drift layer 2 made of SiC is formed on the main surface of the n ⁺ -type substrate 1 using a CVD (chemical vapor deposition) apparatus or the like. At this time, if necessary, a buffer layer 2a in which the n ⁻ -type drift layer 2 has a partially high concentration may be formed. Then, although not shown, after disposing a mask in which a region for forming the p-type deep layer 5 is opened, the p-type deep layer 5 is formed by ion-implanting p-type impurities.

Thereafter, the mask is removed, and the p-type base region 3 and the n ⁺ -type source region 4 are formed on the n ⁻ -type drift layer 2 on which the p-type deep layer 5 is formed. For example, after p-type base region 3 is epitaxially grown, n ⁺ -type impurity ions are implanted to form n ⁺ -type source region 4 or p-type base region 3 and n ⁺ -type source region 4 are epitaxially grown. The p-type base region 3 and the n ⁺ -type source region 4 can be formed by forming the contact region of the p-type base region 3 by ion implantation of a p-type impurity.

[Step shown in FIG. 5 (b)]
Next, a mask (not shown) is disposed on the surfaces of p type base region 3 and n ⁺ type source region 4 to open a region for forming a trench gate structure of the mask. Then, the gate trench 6 is formed by performing anisotropic etching such as RIE (Reactive Ion Etching) using a mask. For example, the etching is performed with a setting such that the depth of the gate trench 6 is deeper by 0.2 to 0.4 μm than the total film thickness of the p type base region 3 and the n ⁺ type source region 4. Thereby, the protrusion amount of the gate trench 6 from the bottom of the p-type base region 3 is made to be 0.2 to 0.4 μm.

[Step shown in FIG. 5 (c)]
After removing the mask, the gate insulating film 7 is formed, for example, by thermal oxidation, and the gate insulating film 7 covers the inner wall surface of the gate trench 6 and the surface of the n ⁺ -type source region 4. Then, for example, after depositing polysilicon doped with n-type impurities, it is etched back to leave at least polysilicon in the gate trench 6 to form the gate electrode 8.

[Step shown in FIG. 5 (d)]
The strongly correlated material layer 9 is formed on the surface of the gate insulating film 7 and the gate electrode 8 using a CVD apparatus or the like.

[Step shown in FIG. 5 (e)]
After the interlayer insulating film 10 is formed on the gate insulating film 7, the gate electrode 8 and the strongly correlated material layer 9, the strongly correlated material layer 9 and the gate insulating film 7 are patterned together with the interlayer insulating film 10 to remove unnecessary portions By doing this, the contact hole 10a is formed. Thereby, the surface of p type base region 3 and n ⁺ type source region 4 and strongly correlated material layer 9 can be exposed through contact hole 10 a.

Although the process after this is not illustrated, an electrode material composed of, for example, a laminated structure of a plurality of metals is formed on the surface of the interlayer insulating film 10. Then, the source material 11 is formed by patterning the electrode material. Furthermore, by performing steps such as forming the drain electrode 12 on the back surface side of the n ⁺ -type substrate 1, a semiconductor device having the vertical MOSFET according to the present embodiment shown in FIG. 1 is completed.

  As described above, in the semiconductor device of the present embodiment, the strong correlation material layer 9 is provided to the MOSFET 20, and the strong correlation material layer 9 functions as a conductor when the temperature of the vertical MOSFET 20 rises. Conduction is made between the sources. Therefore, when element heat generation occurs during a short circuit, the voltage of the gate electrode 8 can be reduced, and the short circuit current flowing to the vertical MOSFET 20 can be cut off, so that the power of the vertical MOSFET 20 can be suppressed. Become. Therefore, it is possible to suppress the temperature rise of the vertical MOSFET 20, to suppress the device breakdown of the vertical MOSFET 20, and to provide a semiconductor device having the vertical MOSFET 20 capable of obtaining a short circuit withstand capacity more accurately. it can.

Second Embodiment
The second embodiment will be described. The present embodiment is the same as the first embodiment except that the structure of the strongly correlated material layer 9 is modified from the first embodiment, and therefore, only different parts from the first embodiment will be described. .

  In the first embodiment, the strong correlation material layer 9 is formed on the gate insulating film 7, and the strong correlation material layer 9 is exposed through the contact hole 10a. On the other hand, in the present embodiment, as shown in FIG. 6, the through holes 10b are formed in the interlayer insulating film 10, and the strong correlation material layer 9 is provided in the through holes 10b.

  As described above, even when the strongly correlated material layer 9 is formed in the through hole 10b in the interlayer insulating film 10, the same effect as that of the first embodiment can be obtained. The semiconductor device having such a structure can be manufactured basically by the same manufacturing method as that of the first embodiment. However, the step of forming the strongly correlated material layer 9 is performed after the step of forming the interlayer insulating film 10. Specifically, after forming interlayer insulating film 10 to form contact hole 10a, or at the same time with the process of forming contact hole 10a, etching the position corresponding to gate electrode 8 in interlayer insulating film 10 Form the through holes 10b. Then, after forming a strongly correlated material including the inside of the through hole 10b using a CVD apparatus or the like, the strongly correlated material layer 9 is formed by etching back so that the p-type silicon layer remains only in the through hole 10b. Form. In this way, it is possible to manufacture a semiconductor device provided with the strongly correlated material layer 9 having the structure as in this embodiment.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and appropriate modifications can be made within the scope of the claims.

For example, in the above embodiments, the n-channel vertical MOSFET having the first conductivity type as n-type and the second conductivity type as p-type has been described as an example, but the conductivity type of each component is inverted. It may be a vertical p-channel type MOSFET. In the above description, the vertical MOSFET is described as an example of the semiconductor element having the MOS structure. However, the present invention can be applied to an IGBT having a similar MOS structure. In the case of an n-channel type IGBT, the conductivity type of the n ⁺ -type substrate 1 is merely changed from n-type to p-type in each of the above embodiments, and the other structure and manufacturing method are the same as in the above embodiments. It is. Furthermore, not only the trench gate type MOS structure but also a semiconductor element of a planar type MOS structure may be used. That is, gate insulating film 7 is formed on the surface of p type base region 3 between n ⁻ type drift layer 2 and n ⁺ type source region 4, and gate electrode 8 is arranged on gate insulating film 7. If it is a structure, it may be a trench gate type or a planar type.

  Further, in the above embodiment, the semiconductor device using SiC as the semiconductor material has been described as an example, but the present invention can be applied to a semiconductor device using a semiconductor material other than SiC. For example, it is preferable to apply the present invention to a semiconductor device using a compound semiconductor material such as GaN other than SiC.

  In addition, although a bar (-) should originally be added above the desired number when indicating the orientation of the crystal, since there is a limitation in expression based on the electronic application, it is desired in the present specification to be a desired one. A bar shall be put in front of the numbers.

2 n ⁻ type drift layer 3 p type base region 4 n ⁺ type source region 5 p type deep layer 7 gate insulating film 8 gate electrode 9 strong correlation material layer 10 interlayer insulating film 11 source electrode

Claims (6)

A semiconductor device having a semiconductor element of MOS structure,
A substrate (1) of a first or second conductivity type made of silicon carbide;
A drift layer (2) made of a semiconductor of a first conductivity type formed on the substrate and having an impurity concentration lower than that of the substrate;
A base region (3) made of silicon carbide of a second conductivity type formed on the drift layer;
A source region (4) made of silicon carbide of a first conductivity type formed on the base region and having a first conductivity type impurity concentration higher than that of the drift layer;
A gate insulating film (7) formed on the surface of the base region between the drift layer and the source region;
A gate electrode (8) disposed on the gate insulating film;
An interlayer insulating film (10) covering the gate electrode and the gate insulating film and in which a contact hole (10a) is formed;
A source electrode (11) electrically connected to the source region through the contact hole;
A drain electrode (12) formed on the back surface side of the substrate;
Furthermore, a strongly correlated material layer made of a strongly correlated electron material (in which the gate electrode and the source electrode are brought into conduction between the gate electrode and the source electrode in response to the temperature rise of the semiconductor element) 9) A semiconductor device provided. The semiconductor device is
In the gate trench (6) formed deeper than the base region from the surface of the source region, the gate insulating film (7) is disposed so as to cover the inner wall surface of the gate trench, and the gate insulation 2. The semiconductor device according to claim 1, wherein a trench gate MOS structure is formed by arranging the gate electrode on a film.   The semiconductor device according to claim 1, wherein the strongly correlated electronic material constituting the strongly correlated material layer is a VO-based material. The semiconductor device according to claim 1, wherein the strongly correlated electronic material constituting the strongly correlated material layer is VO ₂ . The strongly correlated material layer is formed on the gate insulating film and the gate electrode.
The interlayer insulating film is formed to cover the gate insulating film and the gate electrode including the strongly correlated material layer.
The semiconductor device according to any one of claims 1 to 4, wherein a part of the strongly correlated material layer is in contact with the source electrode from the contact hole. A through hole (10b) connected to the gate electrode is formed in the interlayer insulating film,
The semiconductor device according to any one of claims 1 to 4, wherein the strongly correlated material layer is provided in the through hole, and is in contact with the gate electrode and the source electrode through the through hole.

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