JP2017200177A - Pll circuit, reception device, and radio communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit that achieves both of acceleration of a lock time and low phase noise.SOLUTION: A PLL circuit includes: a phase comparison circuit; a first charge pump circuit; a second charge pump circuit; a filter for acceleration; a filter for low phase noise; a charging and discharging circuit; and a voltage-controlled oscillator for oscillating on the basis of output of the filter for low phase noise. If the phase comparison circuit does not detect a lock state, the PLL circuit charges or discharges the filter for low phase noise on the basis of output of the filter for acceleration. If the phase comparison circuit detects a lock state, the PLL circuit electrically separates output of the filter for acceleration from the filter for low phase noise.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a PLL circuit, and can be applied to, for example, a receiving device or a wireless communication device that performs frequency hopping.

  A communication device such as a wireless communication device uses a phase locked loop (PLL) circuit for a frequency synthesizer. The PLL circuit is required to achieve both high lock time and low phase noise, and it is proposed that one loop filter is switched by a switch so that it functions as two filters for high speed and low phase noise. (For example, JP-A-6-276090 (Patent Document 1)).

JP-A-6-276090

In the method of switching the function of one loop filter as described in Patent Document 1, when changing the frequency by changing the input reference signal or the like, the PLL is out of synchronization and resynchronized when the filter function is switched Speeding up is difficult because it takes time.
An object of the present disclosure is to provide a PLL circuit that achieves both high lock time and low phase noise.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

An outline of typical ones of the present disclosure will be briefly described as follows.
That is, the PLL circuit compares the phase of the reference signal and the comparison signal to generate a pulse signal based on the phase difference, the first charge pump circuit that generates a voltage based on the pulse signal, A second charge pump circuit for generating a voltage based on a pulse signal; a speed-up filter for removing unnecessary frequency components from the output voltage of the first charge pump circuit; and an unnecessary frequency component from the output voltage of the second charge pump circuit. A low-phase noise filter, a charge / discharge circuit that charges and discharges the low-phase noise filter based on the output of the speed-up filter, and a voltage-controlled oscillator that oscillates based on the output of the low-phase noise filter And comprising. A signal based on the output of the voltage controlled oscillator is used as the comparison signal. When the phase comparison circuit does not detect the lock state, the low phase noise filter is charged / discharged based on the output of the speed increase filter, and when the phase comparison circuit detects the lock state, the speed increase The output of the filter is electrically separated from the low phase noise filter.

  According to the PLL circuit, it is possible to achieve both a high lock time and a low phase noise.

Block diagram for explaining a PLL circuit according to the first embodiment. 1 is a circuit diagram showing the configuration of the high speed filter of FIG. 1 is a circuit diagram showing the configuration of the low phase noise filter of FIG. The circuit diagram which shows the structure of the charging / discharging circuit of FIG. Timing chart for explaining the operation of the phase comparison circuit of FIG. Timing chart for explaining the operation of the PLL circuit of FIG. Block diagram for explaining a receiver according to the first embodiment. Block diagram for explaining a general PLL circuit Block diagram for explaining a PLL circuit according to a second embodiment. FIG. 9 is a circuit diagram showing the configuration of the speed-up filter of FIG. The circuit diagram which shows the structure of the filter for low phase noises of FIG. The circuit diagram which shows the structure of the charging / discharging circuit of FIG.

  First, a general PLL circuit will be described with reference to FIG. FIG. 8 is a block diagram showing a general PLL circuit. In the PLL circuit 80, an input reference (reference) signal (IN) is given to the phase comparison circuit 81, and the phase comparison circuit 81 outputs an input reference signal (IN) and an output of a voltage-controlled oscillator (VCO) 84. The phase error is detected by comparing with the signal (OUT), and the phase error signal is supplied to the charge pump circuit 82. The charge pump circuit 82 feeds a current corresponding to the phase error signal to the loop filter 83, and the loop filter 83 removes unnecessary frequency components such as input noise and phase jitter and applies the same to the voltage controlled oscillator 84. The voltage controlled oscillator 84 oscillates a signal having a frequency corresponding to the output of the loop filter 83 and outputs it as an output signal (OUT) and feeds it back to the phase comparison circuit 81. The voltage controlled oscillator 84 is an oscillator that can control the output frequency according to the input voltage. For example, an input voltage is applied to the variable capacitance diode, and the oscillation frequency is controlled by a change in the capacitance.

  The operation of the PLL circuit 80 will be described in more detail. The phase comparison circuit 81 compares the phase of the input reference signal (IN) with a part of the output signal (OUT) of the voltage controlled oscillator 84 oscillating at the free-running frequency. A phase error signal is output. This phase error signal is converted into a current by the charge pump circuit 82 and applied to the loop filter 83, and noise and phase jitter components superimposed on the input reference signal (IN) are removed, and the voltage controlled oscillator 84 receives the control input. Given. Since the output signal (OUT) of the voltage controlled oscillator 84 is given to the phase comparison circuit 81, this circuit forms a loop and locks when the phase of the input reference signal (IN) and the output signal (OUT) coincide. It becomes a state. The bandwidth of the loop filter 83 is determined by the balance between the amount of residual noise during tracking in the locked state and the response speed.

  By the way, in the PLL circuit 80, when noise is superimposed on the input reference signal (IN) or phase jitter is superimposed, the loop follows these disturbances, so that frequency noise is generated. . In order to reduce this, it is necessary to narrow the bandwidth of the loop filter 83, but this causes a problem that the transient response becomes slow and the time required for the phase lock of the loop becomes long.

  In the PLL circuit, a description will be given of how to achieve both high lock time and low phase noise. In order to increase the lock time, it is necessary to widen the bandwidth of the PLL. Since the phase noise in the PLL band depends on the phase noise of the reference signal, it does not depend on the phase noise of the voltage controlled oscillator that is the target of the PLL. In order to reduce the phase noise within the PLL band, it is necessary to reduce the phase of the reference signal. Generally, however, the phase noise should be lower than the phase noise of the voltage controlled oscillator as the PLL band becomes wider. Can not be.

  As a method of achieving both high lock time and low phase noise, the PLL circuit according to the embodiment reduces the phase noise by the configuration of the PLL filter (loop filter). First, a PLL filter for low phase noise and a PLL filter for increasing the lock time are provided. In the technique disclosed in Patent Document 1, when the frequency is changed by changing the input reference signal, the frequency is changed by switching two filters with a switch, but the PLL is out of synchronization at the time of switching the filter. Speeding up is difficult because it takes time to resynchronize. On the other hand, in the PLL circuit according to the embodiment, the PLL filter is not switched by a switch, but the PLL filter for low phase noise is charged / discharged by the PLL filter for speeding up. The PLL filter for speeding up and the PLL filter for low phase noise operate in parallel. When charging / discharging is completed, there is no potential difference between the output of the two PLL filters for speeding up and the output of the PLL filter for low phase noise, and the PLL filters can be switched without being out of synchronization.

  As a result, the PLL circuit according to the embodiment can achieve both a high lock time and a low phase noise. Also, according to radio equipment regulations, a communication method with a narrower occupied bandwidth requires lower phase noise, but by using the PLL circuit according to the embodiment, the frequency change time in a communication method with a narrower occupied bandwidth can be shortened. Is possible.

  Examples will be described below with reference to the drawings. However, in the following description, the same components may be denoted by the same reference numerals and repeated description may be omitted.

  First, the configuration of the PLL circuit according to the first embodiment will be described with reference to FIGS. FIG. 1 is a block diagram illustrating a PLL circuit according to the first embodiment. FIG. 2 is a circuit diagram showing the configuration of the speed-up filter of FIG. FIG. 3 is a circuit diagram showing the configuration of the low phase noise filter of FIG. FIG. 4 is a circuit diagram showing a configuration of the charge / discharge circuit of FIG.

  The PLL circuit 10 according to the first embodiment includes a phase comparison circuit 11, a first charge pump circuit 12a, a second charge pump circuit 12b, an acceleration filter 13a, a low phase noise filter 13b, and a voltage controlled oscillator. (VCO) 14, programmable frequency dividing circuit 15, and charging / discharging circuit 16.

  As shown in FIG. 2, the speed-up filter 13a includes a resistor R1a having one end connected to the node N1a and the other end connected to the node N2a, a capacitor C1a having one end connected to the node N2a, and one end having a capacitor C1a. The other end of the capacitor C2a is connected to the reference potential, and the other end is connected to the other end of the capacitor C1a and the other end is connected to the reference potential. As shown in FIG. 3, the low-phase noise filter 13b has a resistor R1b having one end connected to the node N1b and the other end connected to the node N2b, a capacitor C1b having one end connected to the node N2b, and one end having a capacitor. R2b is connected to the other end of C1b, the other end is connected to the reference potential, and a capacitor C2b having one end connected to the other end of the capacitor C1b and the other end connected to the reference potential.

  As shown in FIG. 4, the charging / discharging circuit 16 is configured by connecting a charging circuit 16c and a discharging circuit 16d in parallel. The discharge circuit 16d includes an operational amplifier 161d whose input terminal (+) is connected to the output (node N2a) of the speed-up filter 13a, and a resistor 162d whose one end is connected to the output of the operational amplifier 161c and the other end is connected to the node Nd. A switch 163d having one end connected to the power supply and the other end connected to the node Nd, an operational amplifier 164d having the input terminal (+) connected to the node Nd, an anode connected to the output of the operational amplifier 164d, and a cathode connected to the operational amplifier 164d. And a diode 165d connected to the inverting input terminal (−). The output of the operational amplifier 161d is input to the inverting input terminal (−) to constitute a voltage follower. Opening and closing of the switch 163d is controlled by a lock detection signal (LDS) output from the phase comparison circuit 11. The switch 163d is formed of, for example, an N channel MOS transistor.

  The charging circuit 16c includes an operational amplifier 161c whose input terminal (+) is connected to the output (node N2b) of the low phase noise filter 13b, and a resistor whose one end is connected to the output of the operational amplifier 161c and whose other end is connected to the node Nc. 162c, a switch 163c having one end connected to the reference power supply and the other end connected to the node Nc, an operational amplifier 164c having the input terminal (+) connected to the node Nc, a cathode connected to the output of the operational amplifier 164c, and an anode connected And a diode 165c connected to the inverting input terminal (−) of the operational amplifier 164c. The output of the operational amplifier 161c is input to the inverting input terminal (−) to constitute a voltage follower. Opening and closing of the switch 163c is controlled by a lock detection signal (LDS) output from the phase comparison circuit 11. The switch 163c is formed of, for example, an N channel MOS transistor.

  Next, the operation of the PLL circuit 10 will be described with reference to FIGS. FIG. 5 is a timing chart for explaining the operation of the phase comparison circuit of FIG. FIG. 6 is a timing chart for explaining the operation of the PLL circuit of FIG.

  As shown in FIG. 5, a reference signal (RER) is given to the phase comparison circuit 11, and the phase comparison circuit 11 compares the reference signal (REF) with the output signal (OPD) of the programmable frequency dividing circuit 15. A phase error is detected, a pulse signal (phase error signal (PDS)) corresponding to the phase error is generated, and applied to the first charge pump circuit 12a and the second charge pump circuit 12b. The charge pump circuit 12a and the second charge pump circuit 12b apply voltages corresponding to the phase error signal (PDS) to the high speed filter 13a and the low phase noise filter 13b, respectively.

  When the PLL circuit 10 is synchronized (locked), the low-phase noise filter 13b removes unnecessary frequency components such as input noise and phase jitter from the output voltage of the second charge pump circuit 12b, and applies them to the voltage-controlled oscillator 14. . The voltage controlled oscillator 14 oscillates a signal having a frequency corresponding to the output of the low phase noise filter 13b, outputs the signal as an output signal (OUT), and feeds it back to the phase comparison circuit 11 via the programmable frequency dividing circuit 15. When the PLL circuit 10 is locked, the lock detection signal is activated (for example, becomes High), the charging circuit 16c and the discharging circuit 16d do not operate, and the output of the speed-up filter 13a is low phase noise. The filter 13b is not affected. Thereby, the phase noise can be reduced.

  When the frequency of the PLL circuit is changed, the reference signal (REF) changes, or the frequency dividing signal (OPD) changes due to the change of the frequency dividing ratio of the programmable frequency dividing circuit. When locked, the lock detection signal is deactivated (for example, becomes Low), and the charging circuit 16c and the discharging circuit 16d become operable. The speed-up filter 13a removes unnecessary frequency components such as input noise and phase jitter from the output voltage of the first charge pump circuit 12a. The speed-up filter 13a uses the speed-up filter 13a to remove low-frequency noise. The filter 13b is charged and discharged. FIG. 6 shows a case where charging is performed by the charging circuit 16c. When the high-speed filter 13a charges through the charging circuit 16c, the charging of the node N2b becomes fast, and high-speed locking can be achieved. Note that a broken line A in FIG. 6 indicates a case where no speed-up filter is used.

  As described above, the low-phase noise filter 13b is charged and discharged by the high-speed filter 13a. When charging / discharging is completed, the potential difference between the output of the high speed filter 13a (node N2a) and the output of the low phase noise filter 13b (node N2b) disappears, and the PLL is synchronized. When the PLL is synchronized, the diode 165c, 165d of the charge / discharge circuit 16 is reverse-biased by the lock detection signal (LDS), so that the output (node N2a) of the speed-up filter 13a is reduced to the low phase noise filter 13b. And the output of the low-phase noise filter 13b only is connected to the voltage controlled oscillator 14 (node N2b). Therefore, the PLL circuit according to the embodiment can switch between the high speed filter and the low phase noise filter while the PLL is synchronized.

  Next, a receiver using the PLL circuit according to the first embodiment will be described with reference to FIG. FIG. 7 is a block diagram illustrating a configuration of a receiver using the PLL circuit according to the first embodiment. In the receiver 70 according to the first embodiment, the signal input from the antenna 71 is input to the mixer 74 via the prefilter 72 and the preamplifier 73, and the output of the PLL circuit 10 is input to the mixer 74 via the amplifier 7B for frequency conversion. To do. Further, the output of the mixer 74 is input to the mixer 77 via the intermediate filter (IF filter) 75 and the post amplifier 76, and the output of the oscillator 7C is input to the mixer 77 for frequency conversion to baseband. Further, the output of the mixer 77 is output via an amplifier 78.

  The PLL circuit 10 inputs the output of the oscillator 79 as a reference signal (REF). The control circuit 7A controls the setting of the programmable frequency divider 15 of the PLL circuit 10 and the setting of the reference (when a DDS (Direct Digital Synthesizer) or PLL is used as a reference instead of the oscillator 79). The oscillation frequency can be changed by changing the frequency of the oscillator 79 or the frequency dividing ratio of the programmable frequency dividing circuit 15.

  Since the PLL circuit 10 can increase the lock time and reduce the phase noise, the PLL circuit 10 can be used for a wireless device that performs transmission / reception by switching a plurality of frequencies (frequency hopping).

  The configuration of the PLL circuit according to the second embodiment will be described with reference to FIGS. FIG. 9 is a block diagram illustrating a PLL circuit according to the second embodiment. FIG. 10 is a circuit diagram showing the configuration of the speed-up filter of FIG. FIG. 11 is a circuit diagram showing the configuration of the low phase noise filter of FIG. FIG. 12 is a circuit diagram showing a configuration of the charge / discharge circuit of FIG.

  The PLL circuit 20 according to the second embodiment includes a phase comparison circuit 11, a first charge pump circuit 12a, a second charge pump circuit 12b, a high speed filter 23a, a low phase noise filter 23b, and a voltage controlled oscillator. (VCO) 14, programmable frequency divider 15, and charge / discharge circuit 26.

  As shown in FIG. 10, the high-speed filter 23a has a capacitor C11a having one end connected to the node N1a and the other end connected to the reference potential, a resistor R11a having one end connected to the node N1a, and one end a resistor R11a. The other end of the C12a is connected to the reference potential, the other end is connected to the node N1a, the other end is connected to the node N2a, the other end is connected to the node N2a, and the other end is connected to the node N2a. And a capacitor C13a connected to the. As shown in FIG. 11, the low phase noise filter 23b has a capacitor C11b having one end connected to the node N1b and the other end connected to the reference potential, a resistor R11b having one end connected to the node N1b, and one end a resistor. C12b connected to the other end (node N3b) of R11b and connected to the reference potential at the other end, resistor R12b connected at one end to node N1b and connected at the other end to node N2b, and connected at one end to node N2b. The other end is composed of a capacitor C13b connected to a reference potential.

  As shown in FIG. 12, the charging / discharging circuit 26 is configured by connecting a charging circuit 16c and a discharging circuit 26d in parallel. The discharge circuit 26d has an operational amplifier 161d whose input terminal (+) is connected to the output (node N2a) of the speed-up filter 23a, one end connected to the output of the operational amplifier 161d, and the other end connected to the input terminal (+) of the operational amplifier 164d. A resistor 262d connected to, a diode 165d whose anode is connected to the output of the operational amplifier 164d and cathode is connected to the inverting input terminal (−) of the operational amplifier 164d, one end connected to the resistor 266d and the other end connected to the reference potential Switch 263d, the other end connected to the inverting input terminal (−) of the operational amplifier 161d, one end connected to the inverting input terminal (−) of the operational amplifier 161d, and the other end connected to the output of the operational amplifier 161c. The resistor 267d is used. The opening and closing of the switch 263d is controlled by a lock detection signal (LDS) output from the phase comparison circuit 11. The switch 263d is formed of, for example, an N channel MOS transistor.

  The charging circuit 16c includes an operational amplifier 161c whose input terminal (+) is connected to the output (node N2b) of the low phase noise filter 13b, and a resistor whose one end is connected to the output of the operational amplifier 161c and whose other end is connected to the node Nc. 162c, a switch 163c having one end connected to the reference power supply and the other end connected to the node Nc, an operational amplifier 164c having the input terminal (+) connected to the node Nc, a cathode connected to the output of the operational amplifier 164c, and an anode connected And a diode 165c connected to the inverting input terminal (−) of the operational amplifier 164c. The output of the operational amplifier 161c is input to the inverting input terminal (−) to constitute a voltage follower. Opening and closing of the switch 163c is controlled by a lock detection signal (LDS) output from the phase comparison circuit 11. The switch 163c is formed of, for example, an N channel MOS transistor.

  The charge / discharge circuit 26 is prepared for each capacitor constituting the low phase noise filter 23b, and the output of the charge / discharge circuit 26 is connected to the other end (node N1b) not connected to the reference potential of the capacitor constituting the low phase noise filter 23b. , N2b, N3b). In the present embodiment, the low phase noise filter 13b includes three capacitors (C11b, C12b, C13b), and thus includes three charge / discharge circuits.

  The PLL circuit 20 performs the same operation as the PLL circuit 10 of the first embodiment. The operation of the PLL circuit 20 will be described with reference to FIGS.

  As shown in FIG. 5, a reference signal (RER) is given to the phase comparison circuit 11, and the phase comparison circuit 11 compares the reference signal (REF) with the output signal (OPD) of the programmable frequency dividing circuit 15. A phase error is detected, a pulse signal (phase error signal (PDS)) corresponding to the phase error is generated, and applied to the first charge pump circuit 12a and the second charge pump circuit 12b. The charge pump circuit 12a and the second charge pump circuit 12b apply voltages corresponding to the phase error signal (PDS) to the high speed filter 23a and the low phase noise filter 23b, respectively.

  When the PLL circuit 20 is synchronized (locked), the low phase noise filter 23b removes unnecessary frequency components such as input noise and phase jitter from the output voltage of the second charge pump circuit 12b, and supplies the result to the voltage controlled oscillator 14. . The voltage controlled oscillator 14 oscillates a signal having a frequency corresponding to the output of the low phase noise filter 23 b and outputs it as an output signal (OUT), and feeds it back to the phase comparison circuit 11 via the programmable frequency dividing circuit 15. When the PLL circuit 10 is locked, the lock detection signal is activated (for example, becomes High), the charging circuit 16c and the discharging circuit 26d do not operate, and the output of the speed-up filter 23a has low phase noise. The filter 23b is not affected. Thereby, the phase noise can be reduced.

  When the frequency of the PLL circuit is changed, the reference signal (REF) is changed, or the frequency dividing signal (OPD) is changed by changing the frequency dividing ratio of the programmable frequency dividing circuit. When locked, the lock detection signal is deactivated (for example, becomes Low), and the charging circuit 16c and the discharging circuit 26d become operable. The speed-up filter 23a removes unnecessary frequency components such as input noise and phase jitter from the output voltage of the first charge pump circuit 12a. The speed-up filter 23a uses the speed-up filter 23a to remove low-frequency noise. The filter 23b is charged / discharged. FIG. 6 shows a case where charging is performed by the charging circuit 16c. When the high-speed filter 23a is charged via the charging circuit 16c, the low-phase noise filter 23b is quickly charged, and high-speed locking is possible. . Note that a broken line A in FIG. 6 indicates a case where no speed-up filter is used.

  Further, as described above, the low phase noise filter 23b is charged and discharged by the high speed filter 23a. When the charging / discharging is completed, the potential difference between the output (node N2a) of the high speed filter 23a and the capacitors C11b, C12b, C13b of the low phase noise filter 23b disappears, and the PLL is synchronized. When the PLL is synchronized, the diode 165c, 165d of the charge / discharge circuit 16 is reverse-biased by the lock detection signal (LDS), so that the output (node N2a) of the speed-up filter 23a is reduced to the low phase noise filter 23b. The capacitors C11b, C12b, and C13b are electrically separated, and only the output of the low phase noise filter 23b is connected to the voltage controlled oscillator 14. Therefore, the PLL circuit according to the second embodiment can switch between the high speed filter and the low phase noise filter while the PLL is synchronized.

  The receiver 70 can use the PLL circuit 20 according to the second embodiment instead of the PLL circuit 10 according to the first embodiment.

  The charge / discharge circuit of the first embodiment can be used for the PLL circuit of the second embodiment, and the charge / discharge circuit of the second embodiment can be used for the PLL circuit of the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and needless to say, various modifications can be made.

  Although it has been described above that the PLL circuits 10 and 20 are used in the receiver, it is needless to say that the PLL circuits 10 and 20 can be used in the transmitter.

  Although the switch 163d has been described as being configured with an N-channel MOS transistor, it may be configured with a P-channel MOS transistor. In this case, an inverted signal of a lock detection signal (LDS) for controlling the switch 163c is used as a signal for controlling the switch.

  The PLL circuits 10 and 20 include a programmable frequency divider circuit 15 between the phase comparison circuit 11 and the voltage controlled oscillator 14, but the programmable frequency divider circuit 15 is not provided and the output of the voltage controlled oscillator 14 is sent to the phase comparison circuit 11. You may make it input.

DESCRIPTION OF SYMBOLS 10 ... PLL circuit 11 ... Phase comparison circuit 12a ... 1st charge pump circuit 12b ... 2nd charge pump circuit 13a ... High speed filter 13b ... Low phase noise filter 14 ..Voltage controlled oscillator (VCO)
DESCRIPTION OF SYMBOLS 15 ... Programmable frequency dividing circuit 16 ... Charge / discharge circuit 16c ... Charging circuit 161c ... Operational amplifier 162c ... Resistance 163c ... Switch 164c ... Operational amplifier 165c ... Diode 16d ... Discharge circuit 161d ... operational amplifier 162d ... resistor 163d ... switch 164d ... operational amplifier 165d ... diode

Claims (5)

A phase comparison circuit that compares the phases of the reference signal and the comparison signal to generate a pulse signal based on the phase difference;
A first charge pump circuit for generating a voltage based on the pulse signal;
A second charge pump circuit for generating a voltage based on the pulse signal;
A high-speed filter for removing unnecessary frequency components from the output voltage of the first charge pump circuit;
A low phase noise filter for removing unnecessary frequency components from the output voltage of the second charge pump circuit;
A charge / discharge circuit that charges and discharges the low-phase noise filter based on the output of the speed-up filter;
A voltage controlled oscillator that oscillates based on the output of the low phase noise filter;
With
A signal based on the output of the voltage controlled oscillator is the comparison signal,
When the phase comparison circuit does not detect the locked state, the low phase noise filter is charged / discharged based on the output of the high speed filter,
A PLL circuit that electrically separates the output of the speed-up filter from the low-phase noise filter when the phase comparison circuit detects a locked state. In claim 1,
The charge / discharge circuit includes a diode and a circuit that reversely vise the diode,
When the lock detection signal from the phase comparison circuit does not indicate a locked state, the low phase noise filter is charged / discharged based on the output of the high speed filter,
When the lock detection signal from the phase comparison circuit indicates a locked state, the diode is reverse-biased by the circuit, and the output of the speed-up filter is electrically separated from the low-phase noise filter. circuit. In claim 2,
The high speed filter and the low phase noise filter are each composed of a resistor and a capacitor,
An output of the charge / discharge circuit is connected to a capacitor of the low phase noise filter.   A receiving apparatus comprising: the PLL circuit according to any one of claims 1 to 3; and a mixer that performs frequency conversion using a reception signal from an antenna and an output of the PLL circuit.   A wireless communication device comprising the receiving device and the transmitting device according to claim 4 for transmitting and receiving by switching a plurality of frequencies.

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