JP2017161996A - Command control device, command control method, and command control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To successively process command signals received in parallel on a plurality of reception channels.SOLUTION: Provided is a command control device used in a communication system, comprising: a plurality of buffers for receiving a command signal from each of a plurality of communication channels, holding the command signal and detecting bits in it, and outputting the command signal when the detection result is normal, or a low-level signal when the detection result is abnormal, as an intermediate processing command signal; and a state machine for receiving a plurality of intermediate processing command signals outputted by the plurality of buffers, successively selecting one intermediate processing command signal from among the plurality of intermediate processing command signals, and outputting it as a command processing signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a command control device, a command control method, and a command control program. In particular, the present invention relates to a command control device, a command control method, and a command control program used in a communication system.

  With the increasing variety of multimedia content, more and more applications are demanding performance levels that exceed the performance achievable with a single device or system, and many of these applications use parallel processing. Yes. As an example of using a plurality of application modules for the parallel processing, Patent Document 1 discloses a memory control that defines a memory, a data transfer between the memory and the memory bus, and a memory use capacity for each of the application modules. Data transfer that allows the frequency of access to the memory bus to be adjusted by including a memory bus command control unit that regulates the number of commands that can be held in the command register, and a command register that holds commands for the memory bus An apparatus is disclosed.

JP 2009-003893 A

  However, in a system having a plurality of signal reception channels, command signals received on other channels are discarded while the processing unit processes the command signals received on one channel. Therefore, the next reception cannot be performed without waiting for the end of the processing of the command signal being processed by the processing unit.

  In addition, when a plurality of command signals are received at the same time on a plurality of receiving channels, only the command signal received by the processing unit at the earliest time is processed, and the signal received late by the processing unit is discarded and processed. It never happened.

  In this regard, as described above, the invention according to Patent Document 1 only adjusts the access frequency to the memory bus, and reduces the discarding of a plurality of command signals issued simultaneously to the memory bus. It wasn't.

  Therefore, an object of the present invention is to provide a command control device, a command control method, and a command control program that can sequentially process command signals received in parallel on a plurality of reception channels.

  According to a first aspect of the present invention, there is provided a command control device used in a communication system, receiving a command signal from each of a plurality of communication channels, holding the command signal and detecting a bit, and detecting a result. A plurality of buffers that output the command signal if the detection result is abnormal, a LOW signal if the detection result is abnormal, and a plurality of intermediate processing command signals output by the plurality of buffers. And a state machine that sequentially selects one intermediate processing command signal from the plurality of intermediate processing command signals and outputs the command processing signal as a command processing signal.

  According to a second aspect of the present invention, there is provided a command control method used in a communication system, wherein a plurality of buffers receive a command signal from each of a plurality of communication channels, hold the command signal, and detect a bit. When the detection result is normal, the command signal is output as an intermediate processing command signal, and when the detection result is abnormal, the state machine outputs a plurality of intermediate processes output by the plurality of buffers. A command control method is provided that receives a command signal, sequentially selects one intermediate processing command signal from the plurality of intermediate processing command signals, and outputs the selected intermediate processing command signal as a command processing signal.

  According to a third aspect of the present invention, there is provided a command control program for causing a computer to execute a command control method used in a communication system, wherein the command control method includes a plurality of buffers having a plurality of communication channels. Receives a command signal from each, holds the command signal and detects the bit, and outputs the command signal as an intermediate processing command signal if the detection result is normal, or the LOW signal if the detection result is abnormal The state machine receives a plurality of intermediate processing command signals output from the plurality of buffers, sequentially selects one intermediate processing command signal from the plurality of intermediate processing command signals, and outputs the result as a command processing signal. A command control program is provided.

  According to the present invention, the function for determining the priority order with respect to the order of processing a plurality of command signals allows the processing based on a predetermined processing order when command signals are received simultaneously on a plurality of channels. It becomes.

It is a figure which shows the structural example of the command control apparatus by embodiment of this invention. It is a figure which shows the structural example of the buffer described in FIG. It is a figure which shows the structural example of the state machine described in FIG. It is a figure which shows the example of the state transition diagram used with the state machine of FIG. It is a figure which shows the example of the state transition table used with the state machine of FIG. It is a figure which shows the example of the state transition table used with the state machine of FIG. It is a figure which shows the example of the state transition table used with the state machine of FIG. It is a figure which shows the example of the state transition table used with the state machine of FIG. It is a figure which shows the example of the circuit which comprises the state machine of FIG.

(Description of configuration)
Hereinafter, the command control apparatus according to the present invention will be described in detail with reference to FIGS.

  FIG. 1 shows a configuration example of a command control apparatus according to the present invention. Referring to FIG. 1, the embodiment of the present invention includes buffers 200-1 to 200-4 and a state machine 300. In FIG. 1, four buffers 200-1 to 200-4 are connected to one state machine 300. However, the embodiment of the present invention is not limited to this, and any plurality of buffers A buffer 200 may be included.

  The buffer 200-1 has a command signal reception path (channel A) for receiving the command signal A, a path for receiving the clock signal, and a path for receiving the reset signal A output from the state machine 300 as will be described later. Have. In addition, the state machine 300 has a path for transmitting the intermediate processing command signal (A) and a path for transmitting the flag signal T (A). Furthermore, a reset signal R (A) for initializing the buffer 200-1 is output and input to the buffer 200-1.

  Similarly, the buffer 200-2 inputs a command signal reception path (channel B) for receiving the command signal B, a path for receiving the clock signal, and a reset signal B output from the state machine 300 as will be described later. Have a route. In addition, the state machine 300 has a path for transmitting an intermediate processing command signal (B) and a path for transmitting a flag signal T (B). Furthermore, a reset signal R (B) for initializing the buffer 200-2 is output and input to the buffer 200-2. Hereinafter, the same applies to the buffer 200-3 and the buffer 200-4.

  The roles of the buffers 200-1 to 200-4 are to detect the bit of the received command signal (count the number of bits), hold the command signal, generate a timing signal synchronized with the clock signal, detect the command signal, and generate a reset signal. Etc.

  The state machine 300 receives four intermediate processing command signals (A) to (D) output from the buffers 200-1 to 200-4, and flag signals T (A) to T (D). ) 4 paths and a path for receiving a clock signal from the outside. The state machine 300 has a path for outputting a command processing signal. Further, the state machine 300 outputs a reset signal S for initializing the state machine, and inputs a path to the state machine 300 and a reset signal A for initializing each of the buffers 200-1 to 200-4. To D.

  The role of the state machine 300 is to determine the order of processing the four intermediate processing command signals (A) to (D) received from the buffers 200-1 to 200-4, to output command processing signals, and to the state machine For example, a reset signal for initializing 300 itself and a reset signal for initializing the buffers 200-1 to 200-4 are generated.

  FIG. 2 shows a configuration example of the buffer 200 described above. The buffer 200 includes a counter 210, a shift register 220, a detector 230, and a timing 240.

  The counter 210 has a path for inputting a command signal (command signal A when the buffer 200 is the buffer 200-1), a path for inputting a clock signal, and a path for inputting a reset signal. Here, the “reset signal” is a combination of the reset signal A received from the state machine 300 described with reference to FIG. 1 and the reset signal R (A) received from the detector 230 described later. The counter 210 outputs a counter signal P (counter signal P (A) when the buffer 200 is the buffer 200-1) to the shift register 220, and a counter signal Q (buffer 200 is the buffer 200 to the timing 240). In the case of −1, there is a path for outputting the counter signal Q (A)).

  The shift register 220 has a path for inputting a counter signal P received from the counter 210, a path for inputting a clock signal, and a path for inputting a reset signal. Further, the detector 230 has a path for outputting a shift register signal (a shift register signal (A) when the buffer 200 is the buffer 200-1).

  The detector 230 has a path for inputting a shift register signal, a path for inputting a counter signal Q received from the counter 210, a path for inputting a clock signal, a path for inputting a reset signal, and a timing signal received from a timing 240 described later. Has a route to input. Further, the detector 230 is a path for outputting an intermediate processing command signal (intermediate processing command signal (A) when the buffer 200 is the buffer 200-1) to the state machine 300, a counter 210, a shift register 220, and the detector. 230, a path for outputting a reset signal R for initializing the timing 240 (or a reset signal R (A) when the buffer 200 is the buffer 200-1), a flag signal D (the buffer 200 is the buffer 200- In the case of 1, it has a path for outputting the flag signal D (A)). As described above, the reset signal R (A) is combined with the reset signal A received from the state machine 300 and then input to the counter 210, the shift register 220, the detector 230, and the timing 240.

  The timing 240 has a path for inputting a counter signal Q received from the counter 210, a path for inputting a clock signal, a path for inputting a reset signal, and a path for inputting a flag signal D received from the detector 230. Also, the timing 240 is a path for outputting the flag signal T (the flag signal T (A) when the buffer 200 is the buffer 200-1) to the state machine 300, and the timing signal (the buffer 200 is the buffer 200- In the case of 1, it has a path for outputting the timing signal (A)).

  FIG. 3 shows a configuration example of the state machine 300 described above. The state machine 300 includes a sequential circuit 310 and a selector 320.

  The sequential circuit 310 includes four paths for inputting four flag signals T (A) to T (D) received from the buffers 200-1 to 200-4, a path for inputting a clock signal, and a selector 320 described later. A path for inputting a reset signal S to be received is provided. The sequential circuit 310 has a path for outputting an order signal to the selector 320.

  The selector 320 has four paths for inputting the intermediate processing command signals (A) to (D) received from the buffers 200-1 to 200-4, a path for inputting the order signal from the sequential circuit 310, and a clock. A path for inputting a signal is provided. The selector 320 has a path for outputting a command processing signal and a path for outputting reset signals A to D for initializing the buffers 200-1 to 200-4. Further, the selector 320 has a path for outputting the reset signal S for initializing the sequential circuit 310 and the selector 320 and inputting the reset signal S.

(Description of operation)
In FIG. 1, command signals A to D received via channels A to D are input to buffers 200-1 to 200-4, respectively.

  In FIG. 2, the command signal A input to the buffer 200-1 is input to the counter 210. The counter 210 counts the number of bits of the input command signal A and checks whether it is the prescribed number of bits. When the number of bits is the prescribed number of bits, the counter 210 outputs the command signal A to the shift register 220 as the counter signal P (A). Further, the counter 210 outputs the counter signal Q (A) at timing 240 in synchronization with the timing of outputting the counter signal P (A). As will be described later, the counter signal Q (A) serves as a basis for generating a timing signal for the detector 230 to detect the command signal A included in the shift register signal (A).

  A counter signal P (A) and a clock signal received from the counter 210 are input to the shift register 220, and the counter signal P (A) is stored in the register in synchronization with the clock signal.

  At timing 240, the counter signal Q (A) received from the counter 210 is input. The timing 240 generates a timing signal (A) for detecting the counter signal P (A) included in the shift register signal (A) by the detector 230 based on the counter signal Q (A), and outputs it to the detector 230. To do.

  The detector 230 checks the contents of the shift register signal (A) received from the shift register 220. If the shift register signal (A) is normal, the detector 230 outputs a HIGH level flag signal D (A). At the same time, the detector 230 outputs the checked shift register signal (A) to the state machine 300 as an intermediate processing command signal (A). The timing of the above check is determined by the timing signal (A) received from the timing 240. Each operation in the detector 230 is performed in synchronization with the clock signal.

  Further, the timing 240 generates a flag signal T (A) based on the counter signal Q (A) received from the counter 210 and the flag signal D (A) received from the detector 230, and the flag signal T (A) is output to the state machine 300.

  Thereafter, the detector 230 outputs a reset signal R (A), and initializes the counter 210, the shift register 220, the detector 230, and the timing 240.

  Similarly, the buffer processing units 200-2 to 200-4 generate intermediate processing command signals (B) to (D) and flag signals T (B) to T (D) and output them to the state machine 300.

  In FIG. 3, each operation of the sequential circuit 310 and the selector 320 is executed in synchronization with the clock signal.

  The sequential circuit 310 receives the four flag signals T (A) to T (D) received from the buffers 200-1 to 200-4. Based on each of these flag signals T (A) to T (D), the sequential circuit 310 detects the command signal reception state of each of the buffers 200-1 to 200-4. Further, based on these four flag signals T (A) to T (D), a selector 320 described later determines which of the intermediate processing command signals (A) to (D) is to be processed. Thereafter, the sequential circuit 310 outputs the determined result to the selector 320 as an order signal.

  The selector 320 receives four signals from the intermediate processing command signals (A) to (D), and selects one intermediate processing command signal from these four signals based on the sequential signal received from the sequential circuit 310. select. Thereafter, the selector 320 outputs the selected intermediate processing command signal as a command processing signal.

  Thereafter, the selector 320 sequentially selects and outputs any one of the intermediate processing command signals (A) to (D) based on the order signal. Thereafter, the reset signals A to D and the reset signal S are output at the timing when the output of all signals is completed.

  The buffers 200-1 to 200-4 are initialized by the reset signals A to D output from the selector 320, respectively. In addition, the sequential circuit 310 and the selector 320 are initialized by the reset signal S output from the selector 320.

  Although a system in which command signal reception channels are configured by four channels will be described as an example, embodiments of the present invention are not limited to this.

  A system having four reception channels can be implemented by adopting the same configuration as in FIG.

  Here, the period of the clock signal is 1 μs, the period of the command signal is 4 ms, the HIGH level of each signal is 5.0 V, and the LOW level is 0 V, but the embodiment of the present invention is not limited to this.

  The number of bits of the command signal is 13 bits, and the configuration is such that the first 1 bit is the start bit, the 2nd to 7th bits are the address bits, the 8th to 12th bits are the command bits, and the 13th bit is Although the parity bit is used, the embodiment of the present invention is not limited to this, and the number of bits of the command signal and its configuration are arbitrary.

  In FIG. 1, when command signals A to D are input to buffers 200-1 to 200-4 via channels A to D at approximately the same time, the buffers 200-1 to 200-4 are respectively connected in parallel. Then, the signal is processed in the procedure described below with reference to FIG. In FIG. 2, it is assumed that the clock signal is always input to the clock signal, and the signal processing in FIG. 2 is all performed in synchronization with the clock signal. In addition, it is assumed that the initial value of the reset signal is in the reset release state at the LOW level and the reset is executed when the reset signal is at the HIGH level, but the embodiment of the present invention is not limited to this.

  In the buffer 200 of FIG. 2 (here, the case of the buffer 200-1 will be described), the counter 210 counts the number of bits of the input command signal A. Here, the counter 210 is a 13-bit counter, the initial value of the counter signal P (A) is all 13 bits, and the initial value of the counter signal Q (A) is all LOW level.

  When the result of counting the number of bits of the command signal A in the counter 210 is normal, the counter 210 outputs the command signal A as the counter signal P (A) to the shift register 220, and also to the detector 230 and the timing 240. The level of the counter signal Q (A), which is the output signal of, is changed from the LOW level to the HIGH level. On the other hand, if the counted result is abnormal, the counter signal P (A) is set to the LOW level for all 13 bits, and the counter signal Q (A) also outputs the LOW level.

  If the counted result is normal, the counter signal P (A) output from the counter 210 is stored in the 13-bit shift register 220 in synchronization with the clock signal. On the contrary, if the counted result is abnormal, the counter signal P (A), all of which is at the LOW level, is stored in the shift register 220.

  When the detector 230 determines that the result of the counter 210 counting the command signal A based on the level of the counter signal Q (A) is normal, the start bit, address bit, command bit with respect to the shift register signal (A). The parity bit is detected, a 13-bit signal is output as an intermediate processing command signal, and the flag signal D (A) is changed to a HIGH level. Conversely, if the counter 210 determines that the result of counting the command signal A is abnormal, the detection process is not performed, an intermediate process command signal with all 13 bits set to the LOW level is output, and the flag signal D (A) Is also set to the LOW level.

  At timing 240, the result of ANDing the flag signal D (A) and the counter signal Q (A) output from the detector 230 is output as the flag signal T (A). That is, only when the flag signal D (A) is at a high level and the counter signal Q (A) is at a high level, the flag signal T (A) is at a high level.

  Thereafter, the detector 230 outputs a reset signal R (A), and initializes the counter 210, the shift register 220, the detector 230, and the timing 240.

  Subsequently, the state machine 300 in FIG. 1 processes the intermediate processing command signal and the flag signal according to the procedure described below with reference to FIGS. In FIG. 3, it is assumed that a clock is always input to the clock signal, and the signal processing in FIG. 3 is all performed in synchronization with the clock signal. In addition, it is assumed that the initial value of the reset signal is in the reset release state at the LOW level and the reset is executed when the reset signal is at the HIGH level, but the embodiment of the present invention is not limited to this.

  In the state machine 300 in FIG. 3, flag signals T (A) to T (D) and a clock signal are input to the sequential circuit 310. The sequential circuit 310 detects the command signal reception state of each of the buffers 200-1 to 200-4 based on the flag signals T (A) to T (D), and uses the flag signals T (A) to T (T). Based on the combination of (D), an order signal is output to the selector 320.

  The order signal is generated based on the transition diagram of FIG. 4 and the transition table of FIG.

  In the transition diagram of FIG. 4, four circles represent each channel in FIG. Further, the values described in the squares represent the states from flag signals T (A) to T (D), and in order from the lower digit, flag signals T (A)... Flag signal T (D). Each digit number indicates “1” if the flag signal is HIGH level, “0” if the flag signal is LOW level, and “X” may be “1” or “0”. For example, when the value in the square is “XX10”, the flag signal T (A) is “0”, the flag signal T (B) is “1”, the flag signal T (C) and the flag signal T (D) are It indicates either “0” or “1”. Arrows represent process transitions, and the original circle of the arrow in FIG. 4 represents the channel of the current status, and the circle after the arrow represents the channel of the next status.

  FIG. 5 is a table showing the transition diagram in FIG. The rows in the table represent status and the columns represent channels. 5A to 5D show cases where the current status is channel A to channel D, respectively.

  As can be seen from the transition diagram of FIG. 4 and the transition tables of FIGS. 5A to 5D, taking the case where the current status is channel A as an example, the combination of flags T (A) to T (D) is “0000”. In the case of, the next status remains channel A, as is the current status. In the case of “XX10”, the next status is channel B. In the case of “X100”, the next status is channel C. In the case of “1000”, the next status is channel D. Note that the initial value of the status of the sequential circuit 310 and the status when the reset signal is received are channel A.

  The sequential circuit 310 outputs an order signal corresponding to the next status to the selector 320 based on the transition diagram of FIG. 4 and the transition tables of FIGS. 5A to 5D.

  The selector 320 selects an intermediate processing command signal corresponding to the sequential signal received from the sequential circuit 310 from the intermediate processing command signals (A) to (D), and outputs it as a command processing signal.

  Thereafter, the selector 320 sequentially selects and outputs any one of the intermediate processing command signals (A) to (D) based on the order signal. Thereafter, the reset signals A to D and the reset signal S are output at the timing when the output of all signals is completed.

  6 is a configuration example of a transition diagram of the sequential circuit of FIG. 4 and a circuit diagram of the state machine 300 (sequential circuit 310 and selector 320) for realizing the transition table of the sequential circuit of FIG.

  The sequential circuit 310 includes a logic circuit, a selector circuit, and a latch circuit that receive a flag signal T (A) to a flag signal T (D) and a signal of state <1: 0> (2 bits). For example, when all of the flag signals T (A) to T (D) are at the HIGH level (1), the order signal is a LOW level signal for both 2 bits.

  The selector 320 selects one signal from the intermediate processing command signal A to the intermediate processing command signal D according to the order signal <1: 0> output from the sequential circuit 310. In the case of the above example, the selector 320 selects the intermediate processing command signal A and outputs it as a command processing signal.

  According to the above embodiment, the present invention has a function of temporarily holding the received command signal, so that a plurality of command signals received at the same time can be processed without being lost. In addition, since the present invention has a function for determining the priority order in relation to the order of processing a plurality of command signals, it is possible to perform processing based on a predetermined processing order when command signals are received simultaneously on a plurality of channels. Become.

  In the above description, the state machine 300 uses the intermediate processing command signals (A) to (D) based on the combination of the flag signals T (A) to T (D) generated by the buffers 200-1 to 200-4. The mode of outputting after selecting one signal from the above has been described, but the embodiment of the present invention is not limited to this. The state machine 300 may determine the order of selecting and outputting the intermediate processing command signals (A) to (D) based on another signal or another criterion.

  Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  Each part of the command control device described above can be realized by hardware, software, or a combination thereof. The command control method performed by the command control device can also be realized by either hardware, software, or a combination thereof. Here, being realized by software means that the computer reads and executes a program, or that hardware realizes operation according to microcode corresponding to the program.

  The program may be stored using various types of non-transitory computer readable media and supplied to a computer. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-ROMs. R, CD-R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (random access memory)). The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

  A part or all of the above embodiment is described as in the following supplementary notes, but is not limited thereto.

(Appendix 1)
A command control device used in a communication system,
Receives a command signal from each of a plurality of communication channels, holds the command signal and detects the bit, performs an intermediate process on the command signal if the detection result is normal, and a LOW signal if the detection result is abnormal Multiple buffers that output as command signals,
A state machine that receives a plurality of intermediate processing command signals output from the plurality of buffers, sequentially selects one intermediate processing command signal from the plurality of intermediate processing command signals, and outputs the intermediate processing command signal as a command processing signal; A command control device characterized by that.

(Appendix 2)
The command control device according to attachment 1, wherein
After the state machine selects one intermediate processing command signal from the plurality of intermediate processing command signals, the state machine discards until another intermediate processing command signal is output from the plurality of buffers in the plurality of buffers. A command control device characterized in that the command control device continues to be held without being executed.

(Appendix 3)
The command control device according to appendix 1 or 2,
After each of the plurality of buffers generates a flag signal based on the detection result, the flag signal is transmitted to the state machine,
The command machine is characterized in that the state machine detects a command signal reception state of each of the plurality of buffers based on each of the plurality of flag signals received from the plurality of buffers.

(Appendix 4)
The command control device according to attachment 3, wherein
The command machine is characterized in that the state machine determines the order of selection and output of the plurality of intermediate processing command signals based on a combination of the plurality of flag signals received from the plurality of buffers.

(Appendix 5)
The command control device according to any one of appendices 1 to 4,
A command control device, wherein the state machine generates a reset signal for initializing the state machine and transmits the reset signal to the state machine.

(Appendix 6)
The command control device according to any one of appendices 1 to 5,
The command control device, wherein the state machine generates a reset signal for initializing the plurality of buffers, and transmits the reset signal to the plurality of buffers.

(Appendix 7)
The command control device according to any one of appendices 1 to 6,
Each of the plurality of buffers generates a reset signal that initializes each of the plurality of buffers, and transmits the reset signal to each of the plurality of buffers.

(Appendix 8)
A command control method used in a communication system,
A plurality of buffers receive a command signal from each of a plurality of communication channels, hold the command signal and detect bits. If the detection result is normal, the command signal is displayed. If the detection result is abnormal, the command signal is LOW. Output the signal as an intermediate processing command signal,
The state machine receives a plurality of intermediate processing command signals output from the plurality of buffers, sequentially selects one intermediate processing command signal from the plurality of intermediate processing command signals, and outputs it as a command processing signal A command control method characterized by the above.

(Appendix 9)
A command control method according to appendix 8, wherein
After the state machine selects one intermediate processing command signal from the plurality of intermediate processing command signals, the state machine discards until another intermediate processing command signal is output from the plurality of buffers in the plurality of buffers. A command control method characterized by continuing to be held without being executed.

(Appendix 10)
The command control method according to appendix 8 or 9, wherein
After each of the plurality of buffers generates a flag signal based on the detection result, the flag signal is transmitted to the state machine,
The command control method, wherein the state machine detects a command signal reception state of each of the plurality of buffers based on each of the plurality of flag signals received from the plurality of buffers.

(Appendix 11)
The command control method according to attachment 10, wherein
The command control method, wherein the state machine determines the order of selection and output of the plurality of intermediate processing command signals based on a combination of the plurality of flag signals received from the plurality of buffers.

(Appendix 12)
The command control method according to any one of appendices 8 to 11,
A command control method, wherein the state machine generates a reset signal for initializing the state machine and transmits the reset signal to the state machine.

(Appendix 13)
The command control method according to any one of appendices 8 to 12,
The command control method, wherein the state machine generates a reset signal for initializing the plurality of buffers, and transmits the reset signal to the plurality of buffers.

(Appendix 14)
The command control method according to any one of appendices 8 to 13,
Each of the plurality of buffers generates a reset signal that initializes each of the plurality of buffers, and transmits the reset signal to each of the plurality of buffers.

(Appendix 15)
A command control program for causing a computer to execute a command control method used in a communication system,
The command control method is:
A plurality of buffers receive a command signal from each of a plurality of communication channels, hold the command signal and detect bits. If the detection result is normal, the command signal is displayed. If the detection result is abnormal, the command signal is LOW. Output the signal as an intermediate processing command signal,
The state machine receives a plurality of intermediate processing command signals output from the plurality of buffers, sequentially selects one intermediate processing command signal from the plurality of intermediate processing command signals, and outputs it as a command processing signal A command control program characterized by

(Appendix 16)
A command control program according to attachment 15, wherein
The command method is:
After the state machine selects one intermediate processing command signal from the plurality of intermediate processing command signals, the state machine discards until another intermediate processing command signal is output from the plurality of buffers in the plurality of buffers. A command control program characterized in that the command control program continues to be held without being executed.

(Appendix 17)
The command control program according to appendix 15 or 16,
The command method is:
After each of the plurality of buffers generates a flag signal based on the detection result, the flag signal is transmitted to the state machine,
A command control program, wherein the state machine detects a command signal reception state of each of the plurality of buffers based on each of the plurality of flag signals received from the plurality of buffers.

(Appendix 18)
A command control program according to attachment 17, wherein
The command control method is:
A command control program, wherein the state machine determines the order of selection and output of the plurality of intermediate processing command signals based on a combination of the plurality of flag signals received from the plurality of buffers.

(Appendix 19)
The command control program according to any one of appendices 15 to 18,
The command control method is:
A command control program, wherein the state machine generates a reset signal for initializing the state machine and transmits the reset signal to the state machine.

(Appendix 20)
The command control program according to any one of appendices 15 to 19,
The command control method is:
A command control program, wherein the state machine generates a reset signal for initializing the plurality of buffers and transmits the reset signal to the plurality of buffers.

(Appendix 21)
The command control program according to any one of appendices 15 to 20,
The command control method is:
Each of the plurality of buffers generates a reset signal that initializes each of the plurality of buffers, and transmits the reset signal to each of the plurality of buffers.

  The present invention can be applied to a system including electronic components such as transistors. Furthermore, the present invention can be applied to a system constituted by semiconductor integrated circuits.

100 Command control device 200 200-1 200-2 200-3 200-4 Buffer
210 counter 220 shift register 230 detector 240 timing 300 state machine 310 sequential circuit 320 selector

Claims (9)

A command control device used in a communication system,
Receives a command signal from each of a plurality of communication channels, holds the command signal and detects the bit, performs an intermediate process on the command signal if the detection result is normal, and a LOW signal if the detection result is abnormal Multiple buffers that output as command signals,
A state machine that receives a plurality of intermediate processing command signals output from the plurality of buffers, sequentially selects one intermediate processing command signal from the plurality of intermediate processing command signals, and outputs the intermediate processing command signal as a command processing signal; A command control device characterized by that. The command control device according to claim 1,
After the state machine selects one intermediate processing command signal from the plurality of intermediate processing command signals, the state machine discards until another intermediate processing command signal is output from the plurality of buffers in the plurality of buffers. A command control device characterized in that the command control device continues to be held without being executed. The command control device according to claim 1 or 2,
After each of the plurality of buffers generates a flag signal based on the detection result, the flag signal is transmitted to the state machine,
The command machine is characterized in that the state machine detects a command signal reception state of each of the plurality of buffers based on each of the plurality of flag signals received from the plurality of buffers. The command control device according to claim 3,
The command machine is characterized in that the state machine determines the order of selection and output of the plurality of intermediate processing command signals based on a combination of the plurality of flag signals received from the plurality of buffers. The command control device according to any one of claims 1 to 4,
A command control device, wherein the state machine generates a reset signal for initializing the state machine and transmits the reset signal to the state machine. The command control device according to any one of claims 1 to 5,
The command control device, wherein the state machine generates a reset signal for initializing the plurality of buffers, and transmits the reset signal to the plurality of buffers. The command control device according to any one of claims 1 to 6,
Each of the plurality of buffers generates a reset signal that initializes each of the plurality of buffers, and transmits the reset signal to each of the plurality of buffers. A command control method used in a communication system,
A plurality of buffers receive a command signal from each of a plurality of communication channels, hold the command signal and detect bits. If the detection result is normal, the command signal is displayed. If the detection result is abnormal, LOW. Output the signal as an intermediate processing command signal,
The state machine receives a plurality of intermediate processing command signals output from the plurality of buffers, sequentially selects one intermediate processing command signal from the plurality of intermediate processing command signals, and outputs it as a command processing signal A command control method characterized by the above. A command control program for causing a computer to execute a command control method used in a communication system,
The command control method is:
A plurality of buffers receive a command signal from each of a plurality of communication channels, hold the command signal and detect bits. If the detection result is normal, the command signal is displayed. If the detection result is abnormal, the command signal is LOW. Output the signal as an intermediate processing command signal,
The state machine receives a plurality of intermediate processing command signals output from the plurality of buffers, sequentially selects one intermediate processing command signal from the plurality of intermediate processing command signals, and outputs it as a command processing signal A command control program characterized by