JP2011060162A - Memory control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control device which can efficiently access a synchronous type memory accessed by outputting a row address and a column address at different timings, when accessing thereto. <P>SOLUTION: An issued command determination part 5 of a memory control part 4 determines a memory command, based on all the memory access requests accumulated in a command queue 3 constituted to accumulate the plurality of memory access requests of three or more, in the memory control device. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a memory control device that controls a synchronous memory that outputs and accesses a row address and a column address at different timings.

  As a DRAM (Dynamic Random Access Memory) used as a large-capacity memory, a DDR (double data rate) type synchronous DRAM (SDRAM) such as DDR1-SDRAM, DDR2-SDRAM, or DDR3-SDRAM is mainly used. In the future, a standard for DDR4-SDRAM is being formulated, and the operation speed and capacity of the memory become faster and larger with each generation change. For DDR3-SDRAM that operates at the highest speed at present, a specification with a data rate exceeding 800 MHz to 1.6 GHz is standardized by JEDEC (Joint Electron Device Engineering Council).

  In these memories, once a row address is selected (corresponding to a bank active command in DDR memory, generally called page open), a column address is selected and actual reading or writing is performed. In this case, if only the column address is changed, it can be performed continuously, which increases the operation efficiency. However, when a row address is selected again as a different address, a time for issuing a command for reselection and a waiting time necessary for reselection are generated, resulting in a reduction in efficiency.

  Here, in the memory control device for the synchronous DRAM such as the above-mentioned DDR2-SDRAM, what is necessary to read or write the memory will be described in three cases.

  In the first case, when the page (row address) of the relevant bank is not opened: First, the relevant page must be opened. For this purpose, a bank active command including designation of a bank address to be opened and a row address is issued. Next, in order to actually read or write to the memory, it is necessary to issue a read command or a write command including a column address designation. Thereafter, a precharge command may be issued to close the page if necessary.

  Second case, if the corresponding bank page is already open and the same page (the same row address is specified): There is no need to issue a bank active command, and the actual read or write to the memory A read command or a write command including a column address designation for issuing a command is issued. Thereafter, a precharge command may be issued to close the page if necessary.

  Third case, if the page of the corresponding bank has already been opened and is a different page (a different row address is specified): First, the opened page needs to be closed. For this purpose, a precharge command is issued. Thereafter, in order to open a different page, a bank active command including designation of a bank address and a row address is issued. The operation after issuing the bank active command is the same as in the first case.

  If you want to close the page after issuing a read command or write command, issue a separate precharge command by issuing a read command with precharge or a write command with precharge instead of the read command or write command. There is no need to do.

In general, one of the following two types of access methods is selected for the memory control device that performs such an operation. Or it is operated by selecting either one first.
(A) A method of continuously opening a page until a different page is accessed. If the same page is accessed continuously, the efficiency is increased (hereinafter referred to as an open bank method; see, for example, Patent Documents 1 and 2).
(B) A method of opening and closing a page every time. If different banks are accessed successively, the efficiency is increased (hereinafter referred to as an interleave method; see, for example, Patent Documents 3 and 4).

  The open bank method has a problem that the efficiency is lowered when accesses to different pages in the same bank are consecutive, and the interleave method has a problem that the efficiency is lowered when the same bank is continuously accessed.

  In the open bank method, for example, when the memory is a DDR3-SDRAM, after executing a refresh cycle, after issuing a precharge command to temporarily close the opened bank, wait for an appropriate time. Since a refresh command must be issued, there is a problem that a cycle that becomes inefficient for each refresh period occurs as compared with the interleave method.

  The present invention aims to solve such problems.

  That is, an object of the present invention is to provide a memory control device that can be accessed efficiently when accessing a synchronous memory that outputs and accesses a row address and a column address at different timings.

  According to the first aspect of the present invention, there is provided a command queue capable of storing an external memory access request, and a command control state machine operated by the memory access request stored in the command queue to A memory control unit that issues a command, wherein the command queue stores at least three memory access requests in a memory control device that accesses the memory in which an address space is divided into a plurality of banks The memory control unit is configured to determine the memory command based on all memory access requests stored in the command queue.

  According to a second aspect of the invention, in the first aspect of the invention, the memory control unit includes a bank active flag that stores whether or not each of the plurality of banks in the memory is activated. Is configured to determine the memory command based on all memory access requests stored in the command queue and the bank active flag.

  According to a third aspect of the present invention, in the first aspect of the present invention, when the memory control unit determines the memory command, each memory access request stored in the command queue is determined in each of the memory access requests. The memory command information to be issued first is configured to be written to the command queue for each corresponding memory access request.

  The invention described in claim 4 is the invention described in any one of claims 1 to 3, wherein a refresh control unit that periodically issues a memory refresh request of the memory, and at least the command queue And an arbitration unit that arbitrates the request of the refresh control unit, and the refresh control unit makes a memory refresh request to the arbitration unit, and the first request signal And a second request signal for requesting memory refresh to the memory control unit before a plurality of cycles, and the memory control unit is configured to output the second request signal based on the second request signal. And determining the memory command.

  The invention described in claim 5 is the invention described in any one of claims 1 to 4, further comprising a second command queue different from the command queue, wherein the memory control unit includes the first command queue. The memory command is determined with priority given to requests from the second command queue.

  The invention described in claim 6 is the invention described in any one of claims 1 to 5, wherein a command dividing unit for dividing a memory access request from the outside is provided in a preceding stage of the command queue. It is characterized by being.

  The invention described in claim 7 is the memory device according to any one of claims 1 to 6, wherein the memory command that the memory control unit first issues in response to a memory access request from the command queue is , At least one of a bank active command, a write command, a read command, a write command with precharge, and a read command with precharge.

  In the invention described in claim 8, in the invention described in claim 7, when the bank active command is issued, a flag corresponding to the bank becomes active, and the precharge command, the precharge command, When a write command with charge and a read command with precharge are issued, a flag corresponding to the corresponding bank is configured to be inactive.

  According to the first aspect of the present invention, based on all memory access requests stored in a command queue configured to store a plurality of memory access requests of three or more, the memory control unit sends a memory command. Since the memory command can be issued in consideration of the bank and row address in the memory access request three or more ahead, the page open, page, etc., compared to the case where only the preceding and subsequent memory access requests are considered, for example. The issuance of memory commands related to closing can be reduced, and the access efficiency to the memory can be improved.

  According to the second aspect of the present invention, the bank active flag for storing whether or not each of the plurality of banks in the memory is activated is provided, and the memory command is determined based on the bank active flag. Therefore, the memory command can be issued in consideration of the active bank and the bank and row address in the memory access request three or more ahead, so that, for example, the bank is more than in the case of considering only the preceding and subsequent memory access requests. The issuance of memory commands such as active commands and precharge commands can be reduced, and the memory access efficiency can be improved.

  According to the third aspect of the invention, when determining the memory command, the memory command information to be issued first in each of the memory access requests stored in the command queue is written in the command queue. Efficient memory command issuance order can be determined in advance, so that fewer issuance of memory commands such as bank active commands and precharge commands than when considering only preceding and following memory access requests, for example Thus, the memory access efficiency can be improved.

  According to the invention of claim 4, the refresh control unit outputs a second request signal for requesting memory refresh to the memory control unit a plurality of cycles before the first request signal, and the memory Since the control unit determines the memory command based on the second request signal, the refresh command is issued so that the refresh command can be issued to the memory by issuing a precharge command in advance. The waiting time can be shortened.

  According to the fifth aspect of the present invention, the second command queue different from the command queue is provided, and the memory control unit determines the memory command with priority given to the request from the second command queue. Even in the case of access with high priority, such as CPU cache access, memory access can be performed with the highest priority without degrading CPU performance.

  According to the sixth aspect of the present invention, since the command dividing unit for dividing the memory access request from the outside is provided in the preceding stage of the command queue, the command is input with the bus width of the system bus connected to the command queue. The memory access request can be divided into an appropriate number according to the bus width and burst length of the memory, and there is no need to make a memory access request according to the memory on the system bus side.

  According to the seventh aspect of the present invention, the memory control unit sends an appropriate memory command from the bank active command, write command, read command, write command with precharge, and read command with precharge in response to a request from the command queue. You can choose.

  According to the eighth aspect of the present invention, the flag can be switched by a command for making the bank active or inactive.

1 is a block diagram of a memory control device according to a first embodiment of the present invention. FIG. It is explanatory drawing of the command queue shown in FIG. It is a block diagram of the memory control apparatus concerning the 2nd Embodiment of this invention. 4 is a timing chart showing an operation of the memory control device shown in FIG. 3. It is a block diagram of the memory control apparatus concerning the 3rd Embodiment of this invention. It is a block diagram of the memory control apparatus concerning the 4th Embodiment of this invention. It is a block diagram of the memory control apparatus concerning the 5th Embodiment of this invention.

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of a memory control device according to a first embodiment of the present invention. FIG. 2 is an explanatory diagram of the command queue shown in FIG.

  A memory control device 1 according to the first embodiment of the present invention shown in FIG. 1 includes a command queue 3 and a memory control unit 4, and is connected to the memory 2.

  The memory 2 is, for example, a synchronous DRAM such as DDR1-SDRAM, DDR2-SDRAM, or DDR3-SDRAM. The row address is a bank active command, the column address is a read command, a write command, a read command with precharge, and a precharge. This memory is included in the write command and is output and accessed at different timings. Also, operations such as precharge and refresh are performed by memory commands such as a precharge command and a refresh command.

  The command queue 3 is a queue composed of n standby command buffers # 1 to #n (n is an integer of 3 or more). Each standby command buffer is accessed from the outside of the memory control device 1 to at least the memory 2. Bank and row address (or an address number or the like from which these values can be calculated) are stored (stored). The command queue 3 is stored so that the command buffer # 1 is in the previous entry order, and the entry order is later toward # 2, # 3,.

  The memory control unit 4 includes an issue command determination unit 5, a request reception control unit 6, and a memory command control state machine 7.

  The issued command determination unit 5 determines a command to be issued in the standby command buffer # 1 based on the contents of all the standby command buffers in the command queue 3 and outputs the command to the request reception control unit 6.

  The request acceptance control unit 6 responds to a memory access request signal (Req) from the command queue 3 when the memory command control state machine 7 becomes executable (Ack). And the command to be issued input from the issue command determination unit 5 is output to the memory command control state machine 7.

  The memory command control state machine 7 is a state machine that performs a state transition for issuing a memory command to be output to the memory 2. The memory command control state machine 7 performs a state transition according to a command to be issued input from the issue command determination unit 5. Is output. Further, data output to the memory 2 and data read from the memory 2 are also input.

  The memory control device 1 configured as described above receives a request from the command queue 3, operates the memory command control state machine 7 of the memory control unit 4, and issues a memory command for the memory 2. The memory command is issued based on all the contents stored in the command queue 3 instead of only based on the contents of the command buffer # 1.

  The operation will be specifically described with reference to FIG. FIG. 2 shows that eight commands (memory access requests) transmitted from the system bus (not shown) (not shown) are stored in the command queue 3 as an example. In the figure, the bank to access the memory and the contents of the row address are described. The column address and the type of read / write are omitted because they are not necessary for describing the features of the present invention. The same symbol indicates that the same bank number or the same row address number is stored. Further, the contents stored in the command queue 3 do not have to be the bank address, row address, and column address itself, but may be system address numbers that can calculate these values.

  First, referring to FIG. 2, a case will be described in which commands transmitted from the system bus side are not stored except for the standby command buffer # 1. In that case, the row address R1 of the bank B0 is opened, and thereafter, reading or writing is performed on a column address not shown, and the bank B0 is closed. This is the same as the conventional interleave method.

  Next, a case where commands transmitted from the system bus side are stored in standby command buffers # 1 to # 8 in FIG. In the conventional interleaving method, the standby command buffers # 1, # 2, and # 3 open the same row address and close it after the access to the same row address (page) in the same bank. Resulting in. In this embodiment, first, when executing the standby command buffer # 1, it is confirmed whether or not the standby command buffer # 2 is accessing the same row address of the same bank. Then, since the standby command buffer # 2 is an access to the same row address in the same bank, the standby command buffer # 1 does not perform page close (no precharge command is output). At this time, information indicating that the page is opened is added to the standby command buffer # 2. This makes it possible to identify that it is not necessary to issue a bank active command when executing the standby command buffer # 2. Similarly, in the case of the standby command buffer # 2, the standby command buffer # 3 to be executed immediately after is an access to the same row address in the same bank, so the page is not closed in the standby command buffer # 2. Also at this time, information indicating that the page is opened is added to the standby command buffer # 3.

  In the case of the standby command buffer # 3, the standby command buffer # 4 executed immediately after is not an access to the same row address in the same bank. Therefore, it is confirmed whether or not there is access to the same bank sequentially for the subsequent standby command buffer. Then, the access to the same bank is detected in the standby command buffer # 7. Then, it is confirmed whether the standby command buffer # 7 is accessing the same row address, and it is detected that the standby command buffer # 7 is accessing the same row address. Therefore, the standby command buffer # 3 does not perform page closing. At this time, information indicating that the page is opened is added to the standby command buffer # 7. If the standby command buffer # 7 is an access to a different row address in the same bank, the page is of course closed when the standby command buffer # 3 is executed.

  As described above, the time required to open the row address can be omitted and the efficiency can be improved as compared with the conventional interleaving method and the method of checking only the continuous standby command buffer such as before and after.

  According to the present embodiment, the issued command determination unit 5 of the memory control unit 4 is based on all the memory access requests stored in the command queue 3 configured to store a plurality of three or more memory access requests. Since the memory command is determined, the memory command can be issued in consideration of the bank and the row address in the memory access request three or more ahead, so that the page is more than in the case of considering only the preceding and subsequent memory access requests. The issuance of memory commands relating to open and page close can be reduced, and the access efficiency to the memory 2 can be improved.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS. Note that the same parts as those of the first embodiment described above are denoted by the same reference numerals and description thereof is omitted. FIG. 3 is a block diagram of a memory control device according to the second embodiment of the present invention. FIG. 4 is a timing chart showing the operation of the memory control device shown in FIG.

  In the present embodiment, a bank active flag 8 is added to the first embodiment.

  The bank active flags 8 are provided for the number of banks in the memory 2. For example, when the memory 2 with 8 banks is connected with one CS (chip select), the required bank active flag is 8 and the memory 2 with 8 banks is connected with 2 CSs. If it is, 16 bank active flags are required. The bank active flag 8 is switched between active and inactive by the memory command control state machine 7. That is, if the first command issued after receiving the request is a bank active command, the memory command control state machine 7 updates the bank active flag corresponding to the corresponding bank to an active state. If the first command to be issued is a read command with precharge or a write command with precharge, the bank active flag corresponding to the corresponding bank is updated to an inactive state.

  When the memory control device 1 shown in FIG. 3 receives a request from the command queue 3 and operates the memory command control state machine 7 of the memory control unit 4 to issue a memory command to the memory 2, the issued command determination unit 5 determines a command to be issued from all the contents stored in the command queue 3 and the state of the bank active flag 8.

  Next, the operation of this embodiment will be described with reference to FIG. FIG. 4 shows an operation example of the correspondence between the contents stored in the command queue 3 and the memory command issue order. In the figure, ACT B0 represents an active command for the bank B0, Rd / Wr: a read command or a write command, and Rd / Wr + Pre: a read command with precharge or a write command with precharge. The memory command issuance order is based on the time axis information, but does not indicate that the memory commands are packed without empty cycles. The idle cycle and waiting time required for DDR2-SDRAM, DDR3-SDRAM and the like are omitted.

  First, the memory command corresponding to the command in the standby command buffer # 1 is the issuance of the bank active command for the bank B0 and the read command or the write command. The reason why the memory command issued first is the active command is that the bank active flag 8 corresponding to the bank B0 is inactive, and at the same time when the bank active command is issued, the bank active flag 8 corresponding to the bank B0 is set. Activate.

  Next, the memory command corresponding to the command in the standby command buffer # 2 is a read command or a write command. This is because the read or write is to the same bank and the same row address as the standby command buffer # 1.

  Next, the memory command corresponding to the command in the standby command buffer # 3 is a read command or a write command. In this embodiment, since the determination is made from the contents of the current standby command number to the last (up to standby command buffer # 8, that is, not in the near future, but in the far future), standby command buffer # 7 Can detect a read or write to the same bank and the same row address and confirm that there is no need to close the page during that time, so the read command is not a read command with precharge or a write command with precharge. Alternatively, a write command can be issued.

  Next, the memory command corresponding to the command in the standby command buffer # 4 is the issuance of the bank active command for the bank B1, and the read command or the write command. This is because the bank active flag 8 corresponding to the bank B1 is inactive, and the bank active flag 8 corresponding to the bank B1 is activated simultaneously with the issuance of the bank active command.

  Next, the memory command corresponding to the command in the standby command buffer # 5 is the issuance of the bank active command for the bank B2, and the read command with precharge or the write command with precharge. This is because the bank active flag 8 corresponding to the bank B2 is inactive, and it is detected that read or write to different row addresses in the same bank is stored in the standby command buffer # 8. The bank B2 issues a bank active command and subsequently issues a read command with precharge or a write command with precharge. The bank active flag 8 corresponding to the bank B2 becomes active simultaneously with the issuance of the bank active command, and becomes inactive simultaneously with the issuance of the read command with precharge or the write command with precharge.

  Next, the memory command corresponding to the command in the standby command buffer # 6 is a read command with precharge or a write command with precharge. This is because a read command with a precharge or a write command with a precharge is issued since it is detected that no read or write to the same row address is stored in the same bank until the standby command buffer # 8. The bank active flag 8 corresponding to the bank B1 becomes inactive simultaneously with the issuance of the read command with precharge or the write command with precharge.

  Next, the memory command corresponding to the command in the standby command buffer # 7 is a read command with precharge or a write command with precharge. This is because a read command with a precharge or a write command with a precharge is issued since it is detected that no read or write to the same row address is stored in the same bank until the standby command buffer # 8. The bank active flag 8 corresponding to the bank B0 becomes inactive simultaneously with the issuance of the read command with precharge or the write command with precharge.

  Next, the memory command corresponding to the command in the standby command buffer # 8 is the issuance of the bank active command for the bank B2, and the read command with precharge or the write command with precharge. This is because the bank active flag corresponding to the bank B2 is inactive, and no command is stored after the standby command buffer # 8. Therefore, first, the bank active command for the bank B2 is issued, A read command with charge or a write command with precharge is issued. The bank active flag corresponding to the bank B2 becomes inactive simultaneously with the issuance of the read command with precharge or the write command with precharge.

  FIG. 4 shows an example in which no command comes to the command queue 3 after the standby command buffer # 8. After issuing the memory command corresponding to the command queue # 8, all the bank active flags are in an inactive state. It has become.

  According to this embodiment, bank active flags 8 for storing whether or not a plurality of banks in the memory 2 are activated are provided for the number of accessible banks, and a memory command is determined based on the bank active flags 8. Since the memory command can be issued in consideration of the active bank and the bank and row address in the memory access request three or more ahead, for example, compared to the case where only the preceding and following memory access requests are considered. In addition, the issuance of memory commands such as bank active commands and precharge commands can be reduced, and the access efficiency to the memory 2 can be improved.

  That is, if it is determined only by the contents of the next queue (standby command buffer), for example, in the case of the standby command buffer # 3, a read command with precharge or a write command with precharge is issued. Then, since it can also be determined from the contents of the standby command buffer # 7 that is four points ahead from the current queue number (which occurs in the near future, not the near future), it is not a read command with precharge or a write command with precharge. It is possible to issue a read command or a write command. If the determination is made only with the contents of the next queue, the read command with precharge or the write command with precharge is issued as described above, so the memory command corresponding to the standby command buffer # 7 is the first. Had to issue a bank active command. In this embodiment, the cycle necessary for issuing the bank active command can be omitted, and the efficiency is improved. Furthermore, if it is determined only by the contents of the next queue, when a read command with precharge or a write command with precharge is issued, after waiting for an appropriate waiting time between closing the page and opening it again Since the bank active has to be issued, this waiting time also causes a decrease in efficiency. In the present embodiment, since there is no cause for reducing the efficiency, the efficiency can be increased.

  Further, in the present embodiment, at the time when the operation by the command queue 3 is completed (when it is completed up to the standby command buffer # 8), all banks involved in reading or writing are in a closed state. Therefore, when a refresh command is issued after the operation by the command queue 3 is completed, it is not necessary to issue a precharge command in order to close all open banks, and efficiency is not lowered.

  In the case of the conventional open bank method, as shown in FIG. 4, for example, the memory command corresponding to the standby command buffer # 8 indicates the page of the row address R3 in the bank B1 previously opened in the standby command buffer # 5. In order to be closed once, the precharge command must be issued first. In this embodiment, it is possible to increase efficiency because it is not necessary to issue a precharge and a waiting time corresponding thereto.

  Further, in the conventional open bank system, row address information is necessary for the information of the open bank. In the case of DDR3-SDRAM, the row address information needs 12 to 16 bits for each corresponding bank. On the other hand, in this embodiment, only a 1-bit bank active flag 8 is required for each corresponding bank.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIG. The same parts as those in the first and second embodiments described above are denoted by the same reference numerals and description thereof is omitted. FIG. 5 is a block diagram of a memory control device according to the third embodiment of the present invention.

  In this embodiment, when a request from the command queue 3 is received, a memory command to be issued first corresponding to the first standby command buffer is determined, and at the same time, a command stored in each standby command buffer requested thereafter The first memory command to be issued corresponding to is determined, and the information is added to the contents of each command buffer.

  For example, the bank active command of the bank B0, which is the memory command to be issued first corresponding to the standby command buffer # 1, is determined, and at the same time, the first command corresponding to the commands stored in the standby command buffers # 2 to # 8 is issued. The memory command to be determined is also determined. That is, the standby command buffer # 2 is a read command or a write command, the standby command buffer # 3 is a read command or a write command, the standby command buffer # 4 is a bank active command for the bank B1, and the standby command buffer # 5 is a bank active for the bank B2. Command, standby command buffer # 6 is a read command with precharge or write command with precharge, standby command buffer # 7 is a read command with precharge or write command with precharge, and standby command buffer # 8 is a bank active command for bank B2. And the information is added to the contents of each command buffer. Each memory command is determined with reference to commands in all standby command buffers. That is, an efficient order of issuing memory commands is determined in advance.

  The operation corresponding to this embodiment is exactly the same as that in which the timing diagram of the bank active flag 8 in FIG. 4 is deleted. The effect of this embodiment is the same as that of the second embodiment, and further, there is an effect that the bank active flag 8 becomes unnecessary.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described with reference to FIG. The same parts as those in the first to third embodiments described above are denoted by the same reference numerals and description thereof is omitted. FIG. 6 is a block diagram of a memory control device according to the fourth embodiment of the present invention. In the figure, Write with AP indicates a write command with precharge, and Read with AP indicates a read command with precharge.

  In this embodiment, a refresh control circuit 9 as a refresh control unit is added to the second embodiment (FIG. 3), and the request reception control unit 6 is changed to a request arbitration control unit 6 ′ as an arbitration unit. ing.

  The refresh control circuit 9 outputs a refresh request signal (Req) to the memory 2 as a first request signal to the request arbitration control unit 6 ′ at a predetermined interval, and from the request arbitration control unit 6 ′. A request acceptance signal (Ack) is input. In addition, the refresh control circuit 9 outputs a second refresh request signal (Pre.Req) as a second request signal to the issue command determination unit 5 several cycles before the refresh request signal (Req). . These several cycles may be set as appropriate in accordance with the refresh command issue conditions of the memory 2 to be used.

  The request arbitration control unit 6 ′ arbitrates and accepts an access request signal (Req) to the memory from the command queue 3 and a refresh request signal (Req) to the memory 2 from the refresh control circuit 9. A signal (Ack) indicating that the request has been received is returned to the other block, and the command to be issued or the refresh command input from the issue command determination unit 5 is output to the memory command control state machine 7.

  In the first to third embodiments described above, if a refresh is to be executed while a command (memory access request) is filled in the command queue 3, a precharge command is first issued and an appropriate waiting time is issued. It may be necessary to issue a refresh command later. In order to cope with such a case, in this embodiment, in addition to the normal refresh request signal (Req), a second refresh request signal (Pre.Req) that becomes active several cycles before this signal is issued command determination unit 5 is output. When this signal is active, control is performed so that a read command with precharge or a write command with precharge is issued instead of a read command or a write command, and all pages are closed when a refresh request is accepted. That is, the memory control unit is configured to determine a memory command based on the second request signal.

  According to the present embodiment, the fresh control circuit 9 outputs a second request signal for requesting memory refresh to the issue command determination unit 5 several cycles before the refresh request signal, and issues the command determination unit 5. However, since the memory command is determined based on the second request signal, a refresh command can be issued to the memory 2 by issuing a read command with precharge or a write command with precharge in advance at the time of refresh. Therefore, the waiting time for refresh can be shortened.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described with reference to FIG. The same parts as those in the first to fourth embodiments described above are denoted by the same reference numerals and description thereof is omitted. FIG. 7 is a block diagram of a memory control device according to the fifth embodiment of the present invention.

  In this embodiment, instead of the refresh control circuit 9 of the fourth embodiment, a second command to which a command related to an access having a high priority such as a cache access among commands (memory access requests) from the bus interconnect 12 is input. A command buffer 10 is provided as a queue, and a command dividing circuit 11 is provided as a command dividing unit that divides a command from the bus interconnect 12. A CPU or DMA (not shown) is connected to the bus interconnect 12.

  The command buffer 10 is input with a command that needs to be operated with the memory 2 with the highest priority so as not to reduce the operation performance, such as CPU cache access. When a command is written from the bus interconnect 12, the command buffer 10 outputs an access request signal (Req) to the request arbitration control unit 6 ′ and a request acceptance signal (Ack) from the request arbitration control unit 6 ′. Entered.

  The command division circuit 11 divides a command input from the bus interconnect 12 into a plurality of commands and outputs the command to the command queue 3. Commands on the bus interconnect 12 that define addresses and burst lengths are input to the memory control device 1. For example, if the bus is 128 bits and the burst length is 8, it indicates 128 bytes of memory access. When the connected memory 2 has a 32-bit bus and an accessible size of 32 bytes by a read command or a write command, the command dividing circuit 11 converts a 128-byte command into four commands (32 bytes). Memory access requests).

  According to the present embodiment, the command buffer 10 is provided in addition to the command queue 3, and the request arbitration control unit 6 'determines the memory command with priority given to the request from the command buffer 10. Even in the case of access with a high priority, the memory access can be performed with the highest priority without degrading the performance of the CPU.

  In addition, since a command division circuit 11 that divides an external memory access request is provided in the preceding stage of the command queue 3, a command input with the bus width of the bus interconnect 12 connected to the command queue 3 is stored in the memory 2. It can be divided into an appropriate number according to the bus width and burst length, and it becomes unnecessary to make a memory access request according to the memory 2 on the bus interconnect 12 side.

  The command dividing circuit 11 may be provided not only in the command queue 3 but also in the preceding stage of the command buffer 10. In this case, even in the case of high priority access such as CPU cache access, the memory 2 can be divided into an appropriate number according to the bus width and burst length of the memory 2, and the memory suitable for the memory 2 on the bus interconnect 12 side. There is no need to make an access request.

  The present invention is not limited to the above embodiment. That is, various modifications can be made without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Memory control apparatus 2 Memory 3 Command queue 4 Memory control part 6 'Request arbitration control part (arbitration part)
8 Bank active flag 9 Refresh control circuit (refresh control unit)
10 Command buffer (second command queue)
11 Command division circuit (command division unit)

JP 2004-310394 A Special Table 2002-530743 JP 2006-164099 A JP 2007-249837 A

Claims (8)

A command queue that can store external memory access requests, and a memory control unit that issues a memory command to the memory by operating a command control state machine in response to the memory access requests stored in the command queue; A memory control device for accessing the memory in which an address space is divided into a plurality of banks;
The command queue is configured to store at least three or more memory access requests;
The memory control device, wherein the memory control unit is configured to determine the memory command based on all memory access requests stored in the command queue. A bank active flag for storing whether or not each of the plurality of banks in the memory is activated;
2. The memory control unit according to claim 1, wherein the memory control unit is configured to determine the memory command based on all memory access requests stored in the command queue and the bank active flag. Memory controller.   When the memory control unit determines the memory command, information on the memory command that is first issued in each of all memory access requests stored in the command queue is displayed for each corresponding memory access request. The memory control device according to claim 1, wherein the memory control device is configured to write to a queue. A refresh control unit that periodically issues a memory refresh request for the memory, and an arbitration unit that arbitrates at least the command queue request and the refresh control unit request,
The refresh control unit makes a memory refresh request to the memory control unit a plurality of cycles before the first request signal for making a memory refresh request to the arbitration unit and the first request signal. And a second request signal, and
4. The memory control device according to claim 1, wherein the memory control unit is configured to determine the memory command based on the second request signal. 5.   A second command queue different from the command queue is provided, and the memory control unit is configured to prioritize a request from the second command queue and determine the memory command. The memory control device according to claim 1.   6. The memory control device according to claim 1, wherein a command division unit that divides an external memory access request is provided in a preceding stage of the command queue.   The memory command first issued by the memory control unit in response to a memory access request from the command queue is at least one of a bank active command, a write command, a read command, a write command with precharge, and a read command with precharge. The memory control device according to claim 1, wherein the memory control device is a memory control device.   The bank active flag is activated when the bank active command is issued, and the flag corresponding to the bank is activated when the precharge command, the write command with precharge, or the read command with precharge is issued. The memory control device according to claim 7, wherein the memory control device is configured to be inactive.

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