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JP2017159335A - Semiconductor device and manufacturing method of the same - Google Patents

Semiconductor device and manufacturing method of the same Download PDF

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Publication number
JP2017159335A
JP2017159335A JP2016047391A JP2016047391A JP2017159335A JP 2017159335 A JP2017159335 A JP 2017159335A JP 2016047391 A JP2016047391 A JP 2016047391A JP 2016047391 A JP2016047391 A JP 2016047391A JP 2017159335 A JP2017159335 A JP 2017159335A
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JP
Japan
Prior art keywords
solder
groove
semiconductor device
heat generating
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016047391A
Other languages
Japanese (ja)
Inventor
匠 野村
Takumi Nomura
匠 野村
小林　渉
Wataru Kobayashi
渉 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2016047391A priority Critical patent/JP2017159335A/en
Priority to PCT/JP2016/085662 priority patent/WO2017154289A1/en
Publication of JP2017159335A publication Critical patent/JP2017159335A/en
Pending legal-status Critical Current

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    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/14—Soldering, e.g. brazing, or unsoldering specially adapted for soldering seams
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same which suppress an increase in a size of the semiconductor device while suppressing overflow of a solder.SOLUTION: A semiconductor device is provided with a heating part including a semiconductor chip with an electrode formed, and pairs of first members, second members 19, and third members arranged so as to interpose the heating part. The second member 19 has a main body part 190 electrically connected to the heating part through a first solder, and an extension part 191 extended from the main body part 190. The third member is electrically connected to the extension part 191 through a second solder. The main body part 190 has a first groove part 193 formed so as to surround a connection region 192 of the first solder. The extension part 191 has a second groove part 196 formed on a part of a peripheral region 195 surrounding a connection region 194 of the second solder, and an uneven oxide film 197 formed on a region except for the second groove part 196 of the peripheral region 195.SELECTED DRAWING: Figure 6

Description

この明細書における開示は、半導体装置及びその製造方法に関する。   The disclosure in this specification relates to a semiconductor device and a manufacturing method thereof.

半導体チップを含む発熱部の熱を放熱するために、半導体チップの板厚方向において、発熱部を挟むように一対の放熱部材が配置され、各放熱部材と発熱部とが熱的に接続された両面放熱構造の半導体装置が知られている。   In order to dissipate the heat of the heat generating part including the semiconductor chip, a pair of heat dissipating members are arranged so as to sandwich the heat generating part in the thickness direction of the semiconductor chip, and each heat dissipating member and the heat generating part are thermally connected. A semiconductor device having a double-sided heat dissipation structure is known.

この半導体装置は、放熱部材と発熱部とをはんだを介して板厚方向に積層することで形成される。各放熱部材から冷却器へ放熱させるため、半導体装置の板厚方向の高さの管理が重要となる。放熱部材や発熱部の寸法公差、組み付け公差等によって生じる高さのばらつきは、配置されるはんだの量を適宜調節することによって吸収する。   This semiconductor device is formed by laminating a heat radiating member and a heat generating portion in the plate thickness direction via solder. In order to dissipate heat from each heat radiating member to the cooler, it is important to manage the height of the semiconductor device in the thickness direction. Variations in height caused by dimensional tolerances, assembly tolerances, and the like of the heat radiating member and the heat generating part are absorbed by appropriately adjusting the amount of solder disposed.

この際、上記の各種寸法公差や組み付け公差等がはんだの厚みが狭くなるようにばらつくと、余剰はんだが、発熱部と放熱部材との接続領域から外側に溢れるおそれがある。これに対し、特許文献１には、放熱部材における発熱部との対向面に、余剰はんだを収容するための溝部が形成された半導体装置が開示されている。溝部は、放熱部材において、はんだ接続領域を取り囲むように環状に形成されている。特許文献１では、発熱部が、半導体チップ、ターミナル及びこれらを接続するはんだを有している。   At this time, if the above-described various dimensional tolerances, assembly tolerances, and the like vary so that the thickness of the solder becomes narrow, excess solder may overflow from the connection region between the heat generating portion and the heat radiating member. On the other hand, Patent Document 1 discloses a semiconductor device in which a groove portion for accommodating surplus solder is formed on a surface of a heat radiating member facing a heat generating portion. The groove portion is formed in an annular shape so as to surround the solder connection region in the heat dissipation member. In patent document 1, the heat generating part has a semiconductor chip, a terminal, and solder for connecting them.

特開２０１５−８２６１４号公報JP2015-82614A

両面放熱構造の半導体装置として、三相インバータを構成する３組の上下アームのうちの１組を構成するように、半導体チップ（発熱部）を２つ備えたものが提案されている。この半導体装置は、２ｉｎ１パッケージとも称される。上アームの発熱部及び下アームの発熱部は、板厚方向に直交する直交方向に並んで配置されている。また、各発熱部は、一対の放熱部材によって挟まれている。ここで、２つの半導体チップに対して、板厚方向において同じ側の面である一面側に配置される放熱部材を第１部材、一面と反対の裏面側に配置される放熱部材を第２部材と示す。   As a semiconductor device having a double-sided heat dissipation structure, a semiconductor device having two semiconductor chips (heat generating portions) has been proposed so as to constitute one of three upper and lower arms constituting a three-phase inverter. This semiconductor device is also referred to as a 2-in-1 package. The heat generating part of the upper arm and the heat generating part of the lower arm are arranged side by side in the orthogonal direction orthogonal to the plate thickness direction. Each heat generating part is sandwiched between a pair of heat radiating members. Here, with respect to the two semiconductor chips, the heat radiating member disposed on the same surface in the plate thickness direction is the first member, and the heat radiating member disposed on the back surface opposite to the one surface is the second member. It shows.

上アームの第２部材及び下アームの第２部材は、対応する発熱部とはんだを介して接続される本体部と、本体部から板厚方向に直交する方向へ延設された延設部をそれぞれ有している。例えば、下アームの延設部と対向するように、当該延設部に対して半導体チップ側に外部接続端子が配置されており、はんだを介して延設部と外部接続端子が接続されている。また、下アームの第１部材には、当該第１部材と上アームの延設部とを電気的に中継する継手部が連なっている。継手部は、上アームの延設部と対向するように、当該延設部に対して半導体チップ側に配置されており、はんだを介して延設部と継手部が接続されている。   The second member of the upper arm and the second member of the lower arm include a main body portion connected to the corresponding heat generating portion via solder, and an extending portion extending from the main body portion in a direction perpendicular to the plate thickness direction. Each has. For example, an external connection terminal is arranged on the semiconductor chip side with respect to the extended portion so as to face the extended portion of the lower arm, and the extended portion and the external connection terminal are connected via solder. . In addition, the first member of the lower arm is connected to a joint portion that electrically relays the first member and the extended portion of the upper arm. The joint portion is disposed on the semiconductor chip side with respect to the extension portion so as to face the extension portion of the upper arm, and the extension portion and the joint portion are connected via solder.

このように、各本体部と対応する発熱部との間にはんだが介在するだけでなく、下アームの延設部と外部接続端子との間及び上アームの延設部と継手部との間にもはんだがそれぞれ介在する。したがって、高さのばらつきを吸収するには、本体部側のはんだだけでなく、延設部側のはんだも部材の寸法公差や組み付け公差等を考慮した量が必要である。このため、余剰はんだを収容するための溝部を、本体部だけでなく、延設部にも設けることが考えられる。   Thus, not only the solder is interposed between each main body and the corresponding heat generating part, but also between the extended part of the lower arm and the external connection terminal and between the extended part of the upper arm and the joint part. Solder also intervenes in each. Therefore, in order to absorb the variation in height, not only the solder on the main body part side but also the solder on the extension part side needs an amount in consideration of the dimensional tolerance and assembly tolerance of the member. For this reason, it is conceivable to provide not only the main body portion but also the extending portion for accommodating the excess solder.

しかしながら、延設部に環状の溝部を形成する場合、溝部の形成領域の分、板厚方向に直交する方向において、延設部、ひいては半導体装置の体格が増大してしまう。   However, when an annular groove is formed in the extended portion, the size of the extended portion, and thus the size of the semiconductor device, increases in the direction orthogonal to the plate thickness direction by the formation region of the groove.

本開示はこのような課題にかんがみて、はんだ溢れを抑制しつつ、装置の体格増大を抑制できる半導体装置及びその製造方法を提供することを目的とする。   In view of such problems, the present disclosure aims to provide a semiconductor device and a method for manufacturing the same that can suppress an increase in the size of the device while suppressing solder overflow.

本開示のひとつは、一面（１２ａ）及び一面と板厚方向において反対の裏面（１２ｂ）に電極（１３ａ、１３ｂ）がそれぞれ形成された半導体チップ（１２）を含み、通電により発熱する発熱部（１１）と、発熱部の熱を放熱させるために、板厚方向において発熱部を挟むように配置される一対の放熱部材であって、発熱部と対向するように板厚方向において一面側に配置され、一面の電極と電気的に接続された第１部材（１６）及び発熱部と対向するように板厚方向において裏面側に配置され、裏面の電極と第１はんだ（２０）を介して電気的に接続された本体部（１９０）と、本体部から板厚方向と直交する直交方向に延設された延設部（１９１）と、を含む第２部材（１９）と、延設部と板厚方向において対向するように延設部に対して半導体チップ側に配置され、第２はんだ（２１）を介して延設部と電気的に接続された第３部材（１８，２４）と、を備え、本体部は、発熱部と対向する第１面（１９０ａ）において、第１はんだの接続領域（１９２）を囲むように形成された第１溝部（１９３）を有し、延設部は、第３部材と対向する第２面（１９１ａ）において、第２はんだの接続領域（１９４）を囲む周囲領域（１９５）の一部に形成された第２溝部（１９６）と、周囲領域のうちの第２溝部以外の部分に形成され、表面が連続して凹凸をなす凹凸酸化膜（１９７）と、を有する。   One of the present disclosure includes a semiconductor chip (12) in which electrodes (13a, 13b) are respectively formed on one surface (12a) and one surface (12b) opposite to the one surface in the thickness direction, and a heat generating portion that generates heat by energization ( 11) and a pair of heat dissipating members arranged so as to sandwich the heat generating part in the thickness direction in order to dissipate the heat of the heat generating part, and arranged on one surface side in the thickness direction so as to face the heat generating part The first member (16) electrically connected to the electrode on one side and the heat generating portion are arranged on the back side in the plate thickness direction so as to be electrically connected via the electrode on the back side and the first solder (20). A second member (19) including a main body portion (190) connected to each other, an extending portion (191) extending from the main body portion in a direction orthogonal to the plate thickness direction, and an extending portion, To the extended part so as to face each other in the thickness direction And a third member (18, 24) disposed on the semiconductor chip side and electrically connected to the extending portion via the second solder (21), the main body portion facing the heat generating portion. The surface (190a) has a first groove (193) formed so as to surround the first solder connection region (192), and the extending portion is formed on the second surface (191a) facing the third member. The second groove part (196) formed in a part of the surrounding area (195) surrounding the connection area (194) of the second solder and the surface of the surrounding area other than the second groove part are continuous. And an uneven oxide film (197) having unevenness.

これによれば、周囲領域の一部に余剰の第２はんだを収容する第２溝部が形成されており、周囲領域のうちの第２溝部以外の部分に凹凸酸化膜が形成されている。凹凸酸化膜の表面は粗いため、平坦面に比べてはんだの濡れ性を低下させることができる。また、酸化膜は金属表面よりもはんだの濡れ性が低い。したがって、周囲領域のうち、凹凸酸化膜が形成された部分には、はんだが濡れ拡がり難く、余剰はんだは第２溝部に収容される。このように、周囲領域の一部のみに第２溝部を形成すればよいので、はんだ溢れを抑制しつつ、半導体装置の体格増大を抑制することができる。   According to this, the 2nd groove part which accommodates an excess 2nd solder is formed in a part of surrounding area, and the uneven | corrugated oxide film is formed in parts other than the 2nd groove part in a surrounding area. Since the surface of the concavo-convex oxide film is rough, the wettability of solder can be reduced as compared with a flat surface. Also, the oxide film has lower solder wettability than the metal surface. Therefore, in the surrounding area, the solder is difficult to spread on the portion where the uneven oxide film is formed, and the excess solder is accommodated in the second groove portion. As described above, since the second groove portion only needs to be formed in a part of the peripheral region, it is possible to suppress an increase in the size of the semiconductor device while suppressing solder overflow.

また、本開示は、一面（１２ａ）及び一面と板厚方向において反対の裏面（１２ｂ）に電極（１３ａ、１３ｂ）がそれぞれ形成された半導体チップ（１２）を含み、通電により発熱する発熱部（１１）と、発熱部の熱を放熱させるために、板厚方向において発熱部を挟むように配置される一対の放熱部材であって、発熱部と対向するように板厚方向において一面側に配置され、一面の電極と電気的に接続された第１部材（１６）及び発熱部と対向するように板厚方向において裏面側に配置され、裏面の電極と第１はんだ（２０）を介して電気的に接続された本体部（１９０）と、本体部から板厚方向と直交する直交方向に延設された延設部（１９１）と、を含む第２部材（１９）と、延設部と板厚方向において対向するように延設部に対して半導体チップ側に配置され、第２はんだ（２１）を介して延設部と電気的に接続された第３部材（１８，２４）と、を備え、本体部は、発熱部と対向する第１面（１９０ａ）において、第１はんだの接続領域（１９２）を囲むように形成された第１溝部（１９３）を有し、延設部は、第３部材と対向する第２面（１９１ａ）において、第２はんだの接続領域（１９４）を囲む周囲領域（１９５）の一部に形成された第２溝部（１９６）と、周囲領域のうちの第２溝部以外の部分に形成され、表面が連続して凹凸をなす凹凸酸化膜（１９７）と、を有する半導体装置の製造方法であって、第１溝部と第２溝部とを有する第２部材を準備し、延設部にパルス発振のレーザ光を照射して、第２溝部とともに第２はんだの接続領域を囲むように凹凸酸化膜を形成し、半導体チップの一面の電極と第１部材とを電気的に接続して接続体（３０）を形成し、接続体の発熱部と本体部との間に第１はんだを配置するとともに、延設部と第３部材との間に第２はんだを配置した状態で、第１はんだと第２はんだをリフローし、裏面の電極と本体部とを電気的に接続するとともに、延設部と第３部材とを電気的に接続する。   Further, the present disclosure includes a semiconductor chip (12) in which electrodes (13a, 13b) are formed on one surface (12a) and the back surface (12b) opposite to the one surface in the plate thickness direction, and generates heat when energized ( 11) and a pair of heat dissipating members arranged so as to sandwich the heat generating part in the thickness direction in order to dissipate the heat of the heat generating part, and arranged on one surface side in the thickness direction so as to face the heat generating part The first member (16) electrically connected to the electrode on one side and the heat generating portion are arranged on the back side in the plate thickness direction so as to be electrically connected via the electrode on the back side and the first solder (20). A second member (19) including a main body portion (190) connected to each other, an extending portion (191) extending from the main body portion in a direction orthogonal to the plate thickness direction, and an extending portion, To the extended part so as to face each other in the thickness direction And a third member (18, 24) disposed on the conductor chip side and electrically connected to the extending portion via the second solder (21), the main body portion facing the heat generating portion. The surface (190a) has a first groove (193) formed so as to surround the first solder connection region (192), and the extending portion is formed on the second surface (191a) facing the third member. The second groove part (196) formed in a part of the surrounding area (195) surrounding the connection area (194) of the second solder and the surface of the surrounding area other than the second groove part are continuous. And a concavo-convex oxide film (197) having irregularities, wherein a second member having a first groove portion and a second groove portion is prepared, and a pulsed laser beam is provided in the extended portion. Irradiation of the concavo-convex acid so as to surround the connection area of the second solder together with the second groove A film is formed, the electrode on one surface of the semiconductor chip and the first member are electrically connected to form the connection body (30), and the first solder is disposed between the heat generating portion and the main body portion of the connection body. In addition, in a state where the second solder is disposed between the extending portion and the third member, the first solder and the second solder are reflowed to electrically connect the electrode on the back surface and the main body portion, and to extend The part and the third member are electrically connected.

これによれば、第２溝部及び凹凸酸化膜を形成した後、第２はんだをリフローして、延設部と第３部材とを接続する。よって、半導体装置の高さばらつきを吸収するために必要な量の第２はんだを配置しても、凹凸酸化膜により第２溝部以外へ余剰の第２はんだが溢れ出ることを抑制することができる。また、第２溝部内に余剰の第２はんだを収容することができる。これにより、第２はんだの溢れを抑制することができる。また、周囲領域の一部のみに第２溝部を形成するので、第２溝部を環状とする構成に比べて、半導体装置の体格増大を抑制することができる。   According to this, after forming the second groove portion and the uneven oxide film, the second solder is reflowed to connect the extended portion and the third member. Therefore, even if an amount of the second solder necessary to absorb the height variation of the semiconductor device is disposed, it is possible to suppress the excess second solder from overflowing other than the second groove due to the uneven oxide film. . In addition, surplus second solder can be accommodated in the second groove. Thereby, overflow of the second solder can be suppressed. In addition, since the second groove portion is formed only in a part of the peripheral region, an increase in the size of the semiconductor device can be suppressed as compared with a configuration in which the second groove portion is annular.

この明細書における開示された複数の態様は、それぞれの目的を達成するために、互いに異なる技術的手段を採用する。特許請求の範囲及びこの項に記載した括弧内の符号は、後述する実施形態の部分との対応関係を例示的に示すものであって、技術的範囲を限定することを意図するものではない。この明細書に開示される目的、特徴及び効果は、後続の詳細な説明及び添付の図面を参照することによってより明確になる。   The disclosed embodiments of the present specification employ different technical means to achieve each purpose. Reference numerals in parentheses described in the claims and in this section exemplarily show the correspondence with embodiments described later, and are not intended to limit the technical scope. The objects, features, and advantages disclosed in this specification will become more apparent with reference to the following detailed description and the accompanying drawings.

第１実施形態に係る半導体装置の概略構成を示す平面図である。1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment. 図１に示す半導体装置において、封止樹脂体を省略した平面図である。FIG. 2 is a plan view in which the sealing resin body is omitted in the semiconductor device shown in FIG. 1. 図１のIII−III線に沿う断面図である。It is sectional drawing which follows the III-III line of FIG. 図１のIV−IV線に沿う断面図である。It is sectional drawing which follows the IV-IV line of FIG. 図１のV−V線に沿う断面図である。It is sectional drawing which follows the VV line of FIG. 第２ヒートシンクにおいて、凹凸酸化膜の形成範囲を示す平面図である。It is a top view which shows the formation range of an uneven | corrugated oxide film in a 2nd heat sink. 図６のVII−VII線における断面図である。It is sectional drawing in the VII-VII line of FIG. 凹凸酸化膜の形成工程を示す平面図である。It is a top view which shows the formation process of an uneven | corrugated oxide film. 接続体の形成工程を示す断面図である。It is sectional drawing which shows the formation process of a connection body. ２ｎｄリフロー工程を示す断面図であり、図３に対応している。It is sectional drawing which shows a 2nd reflow process, and respond | corresponds to FIG. ２ｎｄリフロー工程を示す断面図であり、図５に対応している。It is sectional drawing which shows a 2nd reflow process, and respond | corresponds to FIG. 第２ヒートシンクの変形例を示す平面図である。It is a top view which shows the modification of a 2nd heat sink. 第２ヒートシンクの変形例を示す平面図である。It is a top view which shows the modification of a 2nd heat sink. 第２ヒートシンクの変形例を示す平面図である。It is a top view which shows the modification of a 2nd heat sink. 第２実施形態に係る半導体装置の概略構成を示す平面図である。It is a top view which shows schematic structure of the semiconductor device which concerns on 2nd Embodiment. 図１５に示す半導体装置において、封止樹脂体を省略した平面図である。16 is a plan view in which the sealing resin body is omitted in the semiconductor device shown in FIG. 図１５のXVII−XVII線に沿う断面図である。It is sectional drawing which follows the XVII-XVII line of FIG. 図１５のXVIII−XVIII線に沿う断面図である。It is sectional drawing which follows the XVIII-XVIII line of FIG.

以下、本開示の実施の形態を、図面を参照して説明する。以下に示す各実施形態において、共通及び関連する要素には同一の符号を付与するものとする。後述する半導体チップの厚み方向をＺ方向、Ｚ方向に直交し、外部接続端子及び信号端子が延びる方向をＹ方向と示す。また、Ｚ方向及びＹ方向の両方向に直交する方向をＸ方向と示す。特に断りのない限り、上記したＸ方向及びＹ方向により規定されるＸＹ面に沿う形状を、平面形状とする。   Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In each embodiment shown below, the same code | symbol shall be provided to a common and related element. A thickness direction of a semiconductor chip to be described later is a Z direction, a direction orthogonal to the Z direction, and a direction in which an external connection terminal and a signal terminal extend is indicated as a Y direction. A direction orthogonal to both the Z direction and the Y direction is referred to as an X direction. Unless otherwise specified, the shape along the XY plane defined by the X direction and the Y direction is a planar shape.

（第１実施形態）
まず、図１〜図６に基づき、本実施形態の半導体装置の概略構成について説明する。この半導体装置は、例えば、三相インバータに適用される。本実施形態の半導体装置により、三相インバータの上下アームのうち、１組分（一相分）の上下アームが構成される。 (First embodiment)
First, a schematic configuration of the semiconductor device according to the present embodiment will be described with reference to FIGS. This semiconductor device is applied to, for example, a three-phase inverter. With the semiconductor device of this embodiment, one set (one phase) of the upper and lower arms of the three-phase inverter is configured.

半導体装置１は、封止樹脂体１０、発熱部１１、第１ヒートシンク１６、継手部１８、第２ヒートシンク１９、３つの主端子２２，２３，２４及び信号端子２６を備えている。以下において、符号末尾のＨは上アーム側の要素であることを示し、末尾のＬは下アーム側の要素であることを示す。要素の一部には、上アーム、下アームを明確にするために末尾のＨ，Ｌを付与し、別の一部については、上アームの下アームとで共通符号としている。   The semiconductor device 1 includes a sealing resin body 10, a heat generating part 11, a first heat sink 16, a joint part 18, a second heat sink 19, three main terminals 22, 23, 24 and a signal terminal 26. In the following, the suffix “H” indicates an element on the upper arm side, and the suffix “L” indicates an element on the lower arm side. In order to clarify the upper arm and the lower arm, suffixes H and L are given to a part of the elements, and the other parts are common to the lower arm of the upper arm.

封止樹脂体１０は、例えば、エポキシ系樹脂からなる。封止樹脂体１０は、例えば、トランスファモールド法により成形されている。封止樹脂体１０は、平面略矩形状をなしており、Ｚ方向に直交する一面１０ａと、一面１０ａと反対の裏面１０ｂと、一面１０ａと裏面１０ｂとをつなぐ側面１０ｃと、を有している。一面１０ａ及び裏面１０ｂは、例えば、平坦面となっている。   The sealing resin body 10 is made of, for example, an epoxy resin. The sealing resin body 10 is formed by, for example, a transfer mold method. The sealing resin body 10 has a substantially rectangular planar shape, and includes a surface 10a orthogonal to the Z direction, a back surface 10b opposite to the surface 10a, and a side surface 10c that connects the surface 10a and the back surface 10b. Yes. The one surface 10a and the back surface 10b are, for example, flat surfaces.

発熱部１１は、半導体チップ１２を含んでおり、通電により発熱する。発熱部１１は、封止樹脂体１０によって封止されている。発熱部１１は、上アーム側の発熱部１１Ｈと、下アーム側の発熱部１１Ｌを有している。発熱部１１Ｈ，１１Ｌは、同じ構成となっており、互いにＸ方向に並んで配置されている。   The heat generating part 11 includes a semiconductor chip 12 and generates heat when energized. The heat generating part 11 is sealed with a sealing resin body 10. The heat generating part 11 has a heat generating part 11H on the upper arm side and a heat generating part 11L on the lower arm side. The heat generating portions 11H and 11L have the same configuration and are arranged side by side in the X direction.

半導体チップ１２は、シリコンなどの半導体基板に、絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）などのパワートランジスタが形成されてなる。本実施形態では、ｎチャネル型のＩＧＢＴと、当該ＩＧＢＴに逆並列に接続される転流ダイオード（ＦＷＤ）が形成されている。すなわち、半導体チップ１２に、ＲＣ（Reverse Conducting）−ＩＧＢＴが形成されている。半導体チップ１２は、平面略矩形状をなしている。   The semiconductor chip 12 is formed by forming a power transistor such as an insulated gate bipolar transistor (IGBT) on a semiconductor substrate such as silicon. In this embodiment, an n-channel IGBT and a commutation diode (FWD) connected in antiparallel to the IGBT are formed. That is, RC (Reverse Conducting) -IGBT is formed on the semiconductor chip 12. The semiconductor chip 12 has a substantially rectangular planar shape.

ＩＧＢＴ及びＦＷＤは、Ｚ方向に電流が流れるように、いわゆる、縦型構造をなしている。半導体チップ１２の板厚方向、すなわち、Ｚ方向において、一面１２ａにはコレクタ電極１３ａが形成され、一面１２ａと反対の裏面１２ｂにはエミッタ電極１３ｂが形成されている。コレクタ電極１３ａはＦＷＤのカソード電極も兼ねており、エミッタ電極１３ｂはＦＷＤのアノード電極も兼ねている。半導体チップ１２の裏面１２ｂ、すなわちエミッタ電極形成面には、ゲート電極用のパッドを含む図示しないパッドが形成されている。   The IGBT and FWD have a so-called vertical structure so that current flows in the Z direction. In the thickness direction of the semiconductor chip 12, that is, in the Z direction, a collector electrode 13a is formed on one surface 12a, and an emitter electrode 13b is formed on the back surface 12b opposite to the one surface 12a. The collector electrode 13a also serves as an FWD cathode electrode, and the emitter electrode 13b also serves as an FWD anode electrode. Pads (not shown) including pads for gate electrodes are formed on the back surface 12b of the semiconductor chip 12, that is, the emitter electrode forming surface.

半導体チップ１２は、上アーム側の半導体チップ１２Ｈと、下アーム側の半導体チップ１２Ｌを有している。半導体チップ１２Ｈ，１２Ｌは、互いにほぼ同じ平面形状、具体的には平面略矩形状をなすとともに、互いにほぼ同じ大きさとほぼ同じ厚みを有している。半導体チップ１２Ｈ，１２Ｌは、お互いのコレクタ電極１３ａがＺ方向における同じ側となり、お互いのエミッタ電極１３ｂがＺ方向における同じ側となるように配置されている。そして、半導体チップ１２Ｈ，１２Ｌは、Ｚ方向においてほぼ同じ高さに位置するとともに、Ｘ方向において横並びで配置されている。   The semiconductor chip 12 has an upper arm side semiconductor chip 12H and a lower arm side semiconductor chip 12L. The semiconductor chips 12H and 12L have substantially the same planar shape, specifically, a substantially rectangular shape, and have substantially the same size and thickness. The semiconductor chips 12H and 12L are arranged such that their collector electrodes 13a are on the same side in the Z direction and their emitter electrodes 13b are on the same side in the Z direction. The semiconductor chips 12H and 12L are positioned at substantially the same height in the Z direction and are arranged side by side in the X direction.

本実施形態の発熱部１１は、半導体チップ１２に加えて、ターミナル１４と、当該ターミナル１４と半導体チップ１２の電極１３ｂとを接続するはんだ１５を有している。   In addition to the semiconductor chip 12, the heat generating portion 11 according to the present embodiment includes a terminal 14 and solder 15 that connects the terminal 14 and the electrode 13 b of the semiconductor chip 12.

ターミナル１４は、対応する半導体チップ１２と第２ヒートシンク１９との間に介在する。ターミナル１４は、半導体チップ１２と第２ヒートシンク１９との熱伝導、電気伝導経路の途中に位置するため、熱伝導性及び電気伝導性を確保すべく、少なくとも金属材料（例えば、銅）を用いて形成されている。ターミナル１４は、対応する半導体チップ１２の裏面１２ｂのうち、エミッタ電極１３ｂに対向配置され、はんだ１５を介してエミッタ電極１３ｂと電気的に接続されている。   The terminal 14 is interposed between the corresponding semiconductor chip 12 and the second heat sink 19. Since the terminal 14 is located in the middle of the heat conduction and electric conduction path between the semiconductor chip 12 and the second heat sink 19, at least a metal material (for example, copper) is used to ensure the heat conduction and the electric conduction. Is formed. The terminal 14 is disposed to face the emitter electrode 13 b in the back surface 12 b of the corresponding semiconductor chip 12, and is electrically connected to the emitter electrode 13 b through the solder 15.

本実施形態では、ターミナル１４が、上アーム側のターミナル１４Ｈと、下アーム側のターミナル１４Ｌを有している。また、はんだ１５が、上アーム側のはんだ１５Ｈと、下アーム側のはんだ１５Ｌを有している。そして、ターミナル１４Ｈが、半導体チップ１２Ｈのエミッタ電極１３ｂとはんだ１５を介して接続されている。また、ターミナル１４Ｌが、半導体チップ１２Ｌのエミッタ電極１３ｂとはんだ１５を介して接続されている。このように、発熱部１１Ｈが、半導体チップ１２Ｈ、ターミナル１４Ｈ及びはんだ１５Ｈを有し、発熱部１１Ｌが、半導体チップ１２Ｌ、ターミナル１４Ｌ及びはんだ１５Ｌを有している。   In the present embodiment, the terminal 14 includes an upper arm side terminal 14H and a lower arm side terminal 14L. Further, the solder 15 includes an upper arm side solder 15H and a lower arm side solder 15L. The terminal 14H is connected to the emitter electrode 13b of the semiconductor chip 12H via the solder 15. The terminal 14L is connected to the emitter electrode 13b of the semiconductor chip 12L via the solder 15. Thus, the heat generating part 11H has the semiconductor chip 12H, the terminal 14H, and the solder 15H, and the heat generating part 11L has the semiconductor chip 12L, the terminal 14L, and the solder 15L.

第１ヒートシンク１６は、対応する発熱部１１（半導体チップ１２）の熱を半導体装置１の外部に放熱する機能を果たすとともに、配線としての機能も果たす。このため、熱伝導性及び電気伝導性を確保すべく、少なくとも金属材料を用いて形成される。また、第１ヒートシンク１６は上述のように、放熱する機能を果たすので、放熱部材と称されることもある。本実施形態では、第１ヒートシンク１６が、Ｚ方向からの投影視において、対応する発熱部１１を内包するように設けられている。第１ヒートシンク１６が、特許請求の範囲の「第１部材」に相当する。   The first heat sink 16 functions to dissipate the heat of the corresponding heat generating portion 11 (semiconductor chip 12) to the outside of the semiconductor device 1 and also functions as a wiring. For this reason, in order to ensure thermal conductivity and electrical conductivity, it is formed using at least a metal material. Moreover, since the 1st heat sink 16 fulfill | performs the function to thermally radiate as mentioned above, it may be called a heat radiating member. In this embodiment, the 1st heat sink 16 is provided so that the corresponding heat generating part 11 may be included in the projection view from a Z direction. The first heat sink 16 corresponds to a “first member” in the claims.

第１ヒートシンク１６は、半導体チップ１２の一面１２ａに対向する対向面１６ａと、対向面１６ａと反対の放熱面１６ｂを有している。第１ヒートシンク１６の対向面１６ａと対応する半導体チップ１２のコレクタ電極１３ａとが、はんだ１７を介して電気的に接続されている。第１ヒートシンク１６の大部分は封止樹脂体１０によって覆われている。対向面１６ａは封止樹脂体１０内に配置され、放熱面１６ｂは封止樹脂体１０から露出されている。本実施形態では、放熱面１６ｂが、封止樹脂体１０の一面１０ａから露出されるとともに、放熱面１６ｂが一面１０ａとほぼ面一となっている。   The first heat sink 16 has a facing surface 16a facing the one surface 12a of the semiconductor chip 12, and a heat radiating surface 16b opposite to the facing surface 16a. The opposing surface 16 a of the first heat sink 16 and the corresponding collector electrode 13 a of the semiconductor chip 12 are electrically connected via the solder 17. Most of the first heat sink 16 is covered with the sealing resin body 10. The facing surface 16 a is disposed in the sealing resin body 10, and the heat dissipation surface 16 b is exposed from the sealing resin body 10. In the present embodiment, the heat radiating surface 16b is exposed from the one surface 10a of the sealing resin body 10, and the heat radiating surface 16b is substantially flush with the one surface 10a.

本実施形態では、第１ヒートシンク１６が、上アーム側の第１ヒートシンク１６Ｈと、下アーム側の第１ヒートシンク１６Ｌを有している。また、はんだ１７も、上アーム側のはんだ１７Ｈと、下アーム側のはんだ１７Ｌを有している。そして、第１ヒートシンク１６Ｈが、半導体チップ１２Ｈのコレクタ電極１３ａと、はんだ１７Ｈを介して接続されている。また、第１ヒートシンク１６Ｌが、半導体チップ１２Ｌのコレクタ電極１３ａがはんだ１７Ｌを介して接続されている。第１ヒートシンク１６Ｈ，１６Ｌは、Ｘ方向に並んで配置されるとともに、Ｚ方向においてほぼ同じ位置に配置されている。そして、第１ヒートシンク１６Ｈ，１６Ｌの放熱面１６ｂが、封止樹脂体１０の一面１０ａから露出されるとともに、互いにＸ方向に並んでいる。   In the present embodiment, the first heat sink 16 has a first heat sink 16H on the upper arm side and a first heat sink 16L on the lower arm side. The solder 17 also has an upper arm side solder 17H and a lower arm side solder 17L. The first heat sink 16H is connected to the collector electrode 13a of the semiconductor chip 12H via the solder 17H. The first heat sink 16L is connected to the collector electrode 13a of the semiconductor chip 12L via the solder 17L. The first heat sinks 16H and 16L are arranged side by side in the X direction and are arranged at substantially the same position in the Z direction. The heat radiation surfaces 16b of the first heat sinks 16H and 16L are exposed from the one surface 10a of the sealing resin body 10 and are arranged in the X direction.

図２及び図３に示すように、下アーム側の第１ヒートシンク１６Ｌには、継手部１８が連なっている。継手部１８は、特許請求の範囲の「第３部材」に相当する。本実施形態では、継手部１８が、同一の金属板を加工することで、第１ヒートシンク１６Ｌと一体的に設けられている。継手部１８は、封止樹脂体１０に被覆されるように、第１ヒートシンク１６Ｌよりも薄く設けられている。継手部１８は、第１ヒートシンク１６Ｌの対向面１６ａに面一で連なっている。継手部１８は、図２に示すように、第１ヒートシンク１６ＬにおけるＹ方向の一端付近から、後述する第２ヒートシンク１９Ｈに向けて延設されている。本実施形態では、継手部１８が、屈曲部を２箇所有している。   As shown in FIGS. 2 and 3, the joint portion 18 is connected to the first heat sink 16 </ b> L on the lower arm side. The joint portion 18 corresponds to a “third member” in the claims. In the present embodiment, the joint portion 18 is integrally provided with the first heat sink 16L by processing the same metal plate. The joint portion 18 is provided thinner than the first heat sink 16L so as to be covered with the sealing resin body 10. The joint portion 18 is flush with the facing surface 16a of the first heat sink 16L. As shown in FIG. 2, the joint 18 extends from the vicinity of one end of the first heat sink 16L in the Y direction toward a second heat sink 19H described later. In the present embodiment, the joint portion 18 has two bent portions.

第２ヒートシンク１９は、対応する発熱部１１（半導体チップ１２）の熱を半導体装置１の外部に放熱する機能を果たすとともに、配線としての機能も果たす。このため、第１ヒートシンク１６と同様に、熱伝導性及び電気伝導性を確保すべく、少なくとも金属材料を用いて形成される。また、第２ヒートシンク１９は上述のように、放熱する機能を果たすので、放熱部材と称されることもある。本実施形態では、第２ヒートシンク１９が、Ｚ方向からの投影視において、対応する発熱部１１を内包するように設けられている。第２ヒートシンク１９が、特許請求の範囲の「第２部材」に相当する。   The second heat sink 19 functions to dissipate heat from the corresponding heat generating portion 11 (semiconductor chip 12) to the outside of the semiconductor device 1 and also functions as a wiring. For this reason, like the 1st heat sink 16, in order to ensure heat conductivity and electrical conductivity, it forms using a metal material at least. Moreover, since the 2nd heat sink 19 fulfill | performs the function to thermally radiate as mentioned above, it may be called a heat radiating member. In the present embodiment, the second heat sink 19 is provided so as to include the corresponding heat generating portion 11 in the projection view from the Z direction. The second heat sink 19 corresponds to a “second member” in the claims.

第２ヒートシンク１９は、対応するターミナル１４に対向する対向面１９ａと、対向面１９ａと反対の放熱面１９ｂを有している。第２ヒートシンク１９の対向面１９ａと対応するターミナル１４とが、はんだ２０を介して電気的に接続されている。はんだ２０が、特許請求の範囲の「第１はんだ」に相当する。第２ヒートシンク１９の大部分は封止樹脂体１０によって覆われている。対向面１９ａは封止樹脂体１０内側の面であり、放熱面１９ｂは封止樹脂体１０から露出している側の面である。本実施形態では、放熱面１９ｂが、封止樹脂体１０の裏面１０ｂから露出されるとともに、放熱面１９ｂが裏面１０ｂとほぼ面一となっている。   The second heat sink 19 has a facing surface 19a facing the corresponding terminal 14 and a heat radiating surface 19b opposite to the facing surface 19a. The opposing surface 19 a of the second heat sink 19 and the corresponding terminal 14 are electrically connected via the solder 20. The solder 20 corresponds to the “first solder” in the claims. Most of the second heat sink 19 is covered with the sealing resin body 10. The facing surface 19 a is a surface inside the sealing resin body 10, and the heat dissipation surface 19 b is a surface exposed from the sealing resin body 10. In the present embodiment, the heat dissipation surface 19b is exposed from the back surface 10b of the sealing resin body 10, and the heat dissipation surface 19b is substantially flush with the back surface 10b.

本実施形態では、第２ヒートシンク１９が、上アーム側の第２ヒートシンク１９Ｈと、下アーム側の第２ヒートシンク１９Ｌを有している。また、はんだ２０も、上アーム側のはんだ２０Ｈと、下アーム側のはんだ２０Ｌを有している。そして、第２ヒートシンク１９Ｈとターミナル１４Ｈとが、はんだ２０Ｈを介して接続されている。また、第２ヒートシンク１９Ｌとターミナル１４Ｌとが、はんだ２０Ｌを介して接続されている。第２ヒートシンク１９Ｈ，１９Ｌは、Ｘ方向に並んで配置されるとともに、Ｚ方向においてほぼ同じ位置に配置されている。そして、第２ヒートシンク１９Ｈ，１９Ｌの放熱面１９ｂが、封止樹脂体１０の裏面１０ｂから露出されるとともに、互いにＸ方向に並んでいる。   In the present embodiment, the second heat sink 19 has a second heat sink 19H on the upper arm side and a second heat sink 19L on the lower arm side. The solder 20 also has an upper arm side solder 20H and a lower arm side solder 20L. The second heat sink 19H and the terminal 14H are connected via the solder 20H. The second heat sink 19L and the terminal 14L are connected via the solder 20L. The second heat sinks 19H and 19L are arranged side by side in the X direction and are arranged at substantially the same position in the Z direction. And the heat radiating surface 19b of 2nd heat sink 19H, 19L is exposed from the back surface 10b of the sealing resin body 10, and is located in a line with the X direction mutually.

また、第２ヒートシンク１９Ｈ，１９Ｌを共通形状としており、第２ヒートシンク１９Ｈと第２ヒートシンク１９Ｌは、２回対称となるように配置されている。第２ヒートシンク１９は、図６に示すように、平面略Ｌ字状をなしており、はんだ２０を介して対応するターミナル１４に接続される本体部１９０と、本体部１９０から延設された延設部１９１を有している。延設部１９１は、本体部１９０よりも薄く設けられている。また、延設部１９１の延設方向がＸ方向に沿うように、第２ヒートシンク１９が配置されている。対向面１９ａは、本体部１９０における対向面１９０ａと延設部１９１における対向面１９１ａを有している。本体部１９０における対向面１９０ａと反対の面が、放熱面１９ｂをなしている。本実施形態では、対向面１９０ａ，１９１ａが面一で連なっている。これにより、対向面１９ａが平坦となっている。本体部１９０の対向面１９０ａが、特許請求の範囲の「第１面」に相当し、延設部１９１の対向面１９１ａが、特許請求の範囲の「第２面」に相当する。   The second heat sinks 19H and 19L have a common shape, and the second heat sink 19H and the second heat sink 19L are disposed so as to be two-fold symmetrical. As shown in FIG. 6, the second heat sink 19 has a substantially L-shaped plane, and a main body 190 connected to the corresponding terminal 14 via the solder 20, and an extension extending from the main body 190. It has an installation part 191. The extending portion 191 is provided thinner than the main body portion 190. Further, the second heat sink 19 is arranged so that the extending direction of the extending part 191 is along the X direction. The facing surface 19 a has a facing surface 190 a in the main body 190 and a facing surface 191 a in the extending portion 191. A surface of the main body 190 opposite to the facing surface 190a forms a heat radiating surface 19b. In the present embodiment, the opposing surfaces 190a and 191a are flush with each other. Thereby, the opposing surface 19a is flat. The opposing surface 190a of the main body 190 corresponds to the “first surface” in the claims, and the opposing surface 191a of the extending portion 191 corresponds to the “second surface” in the claims.

本実施形態では、半導体装置１が、本体部１９０として、上アーム側の本体部１９０Ｈと下アーム側の本体部１９０Ｌを有している。また、延設部１９１として、上アーム側の延設部１９１Ｈと下アーム側の延設部１９１Ｌを有している。そして、Ｘ方向において、延設部１９１Ｈが、本体部１９０Ｌと対向し、延設部１９１Ｌが本体部１９０Ｈと対向するように、２つの第２ヒートシンク１９Ｈ，１９Ｌが配置されている。   In the present embodiment, the semiconductor device 1 includes a main body portion 190H on the upper arm side and a main body portion 190L on the lower arm side as the main body portion 190. Further, as the extending portion 191, an extending portion 191H on the upper arm side and an extending portion 191L on the lower arm side are provided. In the X direction, the two second heat sinks 19H and 19L are arranged such that the extending portion 191H faces the main body portion 190L and the extending portion 191L faces the main body portion 190H.

延設部１９１Ｈは、Ｚ方向からの投影視において、継手部１８の先端部分と重なっている。延設部１９１Ｈと継手部１８は、はんだ２１を介して接続されている。はんだ２１が、特許請求の範囲の「第２はんだ」に相当する。   The extending portion 191H overlaps the tip end portion of the joint portion 18 in the projection view from the Z direction. The extending part 191 </ b> H and the joint part 18 are connected via a solder 21. The solder 21 corresponds to “second solder” in the claims.

主端子２２は、直流電源の高電位側に接続される。このため、主端子２２は、高電位電源端子、Ｐ端子とも称される。主端子２２は、第１ヒートシンク１６Ｈと電気的に接続されており、Ｙ方向に延設されて、封止樹脂体１０の側面１０ｃのひとつから外部に突出している。本実施形態では、同一の金属板を加工することで、主端子２２が第１ヒートシンク１６Ｈと一体的に設けられている。   The main terminal 22 is connected to the high potential side of the DC power supply. For this reason, the main terminal 22 is also referred to as a high potential power supply terminal or a P terminal. The main terminal 22 is electrically connected to the first heat sink 16H, extends in the Y direction, and protrudes from one of the side surfaces 10c of the sealing resin body 10 to the outside. In the present embodiment, the main terminal 22 is integrally provided with the first heat sink 16H by processing the same metal plate.

主端子２３は、三相モータの出力線に接続される。このため、主端子２３は、出力端子、Ｏ端子とも称される。主端子２３は、第１ヒートシンク１６Ｌと電気的に接続されており、Ｙ方向に延設されて、主端子２２と同じ側面１０ｃから外部に突出している。   The main terminal 23 is connected to the output line of the three-phase motor. For this reason, the main terminal 23 is also referred to as an output terminal or an O terminal. The main terminal 23 is electrically connected to the first heat sink 16L, extends in the Y direction, and protrudes from the same side surface 10c as the main terminal 22 to the outside.

主端子２４は、直流電源の低電位側に接続される。このため、主端子２４は、低電位電源端子、Ｎ端子とも称される。主端子２４は、Ｚ方向からの投影視において、第２ヒートシンク１９Ｌの延設部１９１Ｌと重なるように配置されている。主端子２４は、Ｚ方向において、延設部１９１Ｌに対して半導体チップ１２側に配置されている。そして、主端子２４と延設部１９１Ｌは、はんだ２５を介して接続されている。主端子２４が、特許請求の範囲の「外部接続端子及び第３部材」に相当する。また、はんだ２５が、特許請求の範囲の「第２はんだ」に相当する。   The main terminal 24 is connected to the low potential side of the DC power supply. For this reason, the main terminal 24 is also referred to as a low potential power supply terminal or an N terminal. The main terminal 24 is disposed so as to overlap with the extending portion 191L of the second heat sink 19L in the projection view from the Z direction. The main terminal 24 is disposed on the semiconductor chip 12 side with respect to the extending portion 191L in the Z direction. The main terminal 24 and the extended portion 191 </ b> L are connected via the solder 25. The main terminal 24 corresponds to “external connection terminal and third member” in the claims. The solder 25 corresponds to “second solder” in the claims.

主端子２４は、Ｙ方向に延設されて、主端子２２，２３と同じ側面１０ｃから外部に突出している。主端子２２，２３，２４における封止樹脂体１０からの突出部分は、Ｚ方向において互いにほぼ同じ位置に配置されている。また、Ｘ方向において、主端子２２、主端子２４、主端子２３の順に並んで配置されている。   The main terminal 24 extends in the Y direction and protrudes from the same side surface 10 c as the main terminals 22 and 23. The protruding portions from the sealing resin body 10 in the main terminals 22, 23, 24 are arranged at substantially the same position in the Z direction. In the X direction, the main terminal 22, the main terminal 24, and the main terminal 23 are arranged in this order.

信号端子２６は、対応する半導体チップ１２のパッドに、ボンディングワイヤ２７を介して電気的に接続されている。信号端子３６は、Ｙ方向に延設されており、封止樹脂体１０の側面１０ｃのひとつから外部に突出している。具体的には、主端子２２，２３，２４とは反対の側面１０ｃから、外部に突出している。   The signal terminal 26 is electrically connected to the corresponding pad of the semiconductor chip 12 via a bonding wire 27. The signal terminal 36 extends in the Y direction and protrudes from one of the side surfaces 10 c of the sealing resin body 10 to the outside. Specifically, it protrudes to the outside from the side surface 10c opposite to the main terminals 22, 23, 24.

本実施形態では、信号端子２６が、上アーム側の信号端子２６Ｈと、下アーム側の信号端子２６Ｌを有している。信号端子２６Ｈは半導体チップ１２Ｈのパッドに接続され、信号端子２６Ｌは半導体チップ１２Ｌのパッドに接続されている。   In the present embodiment, the signal terminal 26 includes an upper arm side signal terminal 26H and a lower arm side signal terminal 26L. The signal terminal 26H is connected to the pad of the semiconductor chip 12H, and the signal terminal 26L is connected to the pad of the semiconductor chip 12L.

以上のように構成される半導体装置１では、封止樹脂体１０により、発熱部１１、第１ヒートシンク１６の一部、第２ヒートシンク１９の一部、主端子２２，２３，２４の一部、及び信号端子２６の一部が、一体的に封止されている。半導体装置１では、封止樹脂体１０によって、一相分の上下アームを構成する２つの半導体チップ１２Ｈ，１２Ｌが封止されている。このため、半導体装置１は、２ｉｎ１パッケージとも称される。   In the semiconductor device 1 configured as described above, due to the sealing resin body 10, the heat generating part 11, a part of the first heat sink 16, a part of the second heat sink 19, a part of the main terminals 22, 23, 24, A part of the signal terminal 26 is integrally sealed. In the semiconductor device 1, the two semiconductor chips 12 </ b> H and 12 </ b> L constituting the upper and lower arms for one phase are sealed with the sealing resin body 10. For this reason, the semiconductor device 1 is also referred to as a 2-in-1 package.

また、第１ヒートシンク１６及び第２ヒートシンク１９は、後述するように、封止樹脂体１０とともに切削加工されている。そして、第１ヒートシンク１６Ｈ，１６Ｌの放熱面１６ｂが、同一面内に位置するとともに、封止樹脂体１０の一面１０ａと略面一となっている。同じく、第２ヒートシンク１９Ｈ，１９Ｌの放熱面１９ｂが、同一面内に位置するとともに、封止樹脂体１０の裏面１０ｂと略面一となっている。   Moreover, the 1st heat sink 16 and the 2nd heat sink 19 are cut with the sealing resin body 10 so that it may mention later. The heat radiation surfaces 16b of the first heat sinks 16H and 16L are located in the same plane and are substantially flush with the one surface 10a of the sealing resin body 10. Similarly, the heat radiating surfaces 19b of the second heat sinks 19H and 19L are located in the same plane and are substantially flush with the back surface 10b of the sealing resin body 10.

次に、図３〜図７に基づき、はんだ２０，２１，２５を介した第２ヒートシンク１９の接続構造について説明する。   Next, based on FIGS. 3-7, the connection structure of the 2nd heat sink 19 via the solder 20,21,25 is demonstrated.

図７に示すように、第２ヒートシンク１９は、金属材料を用いて形成された基材１９ｃと、基材表面に形成された金属薄膜１９ｄを有している。基材に用いられる材料としては、Ｃｕ、Ｃｕ合金、Ａｌ合金などの熱伝導性及び電気伝導性に優れる材料を採用することができる。金属薄膜１９ｄは、金属を構成材料とする膜である。金属薄膜１９ｄは、例えば、めっき、蒸着により形成されたものである。金属薄膜１９ｄとして、Ｎｉを主成分とする膜を含む構成が好ましい。より好ましくは、無電解Ｎｉめっき膜を含む構成がよい。本実施形態において、凹凸酸化膜１９７の形成領域における金属薄膜１９ｄは、無電解Ｎｉめっき膜を有している。一方、凹凸酸化膜１９７の形成されない領域における金属薄膜１９ｄは、無電解Ｎｉめっき膜と、無電解Ｎｉめっき膜上に形成されたＡｕめっき膜を有している。このように、凹凸酸化膜１９７の形成領域にＡｕめっき膜が存在しないのは、レーザ光の照射によりＡｕめっき膜を除去するとともに、下層の無電解Ｎｉめっき膜から凹凸酸化膜１９７を形成するためである。無電解Ｎｉめっき膜は、主成分であるＮｉに加えて、Ｐ（リン）を含んでいる。   As shown in FIG. 7, the second heat sink 19 includes a base material 19c formed using a metal material and a metal thin film 19d formed on the surface of the base material. As a material used for the base material, a material having excellent thermal conductivity and electrical conductivity such as Cu, Cu alloy, Al alloy and the like can be adopted. The metal thin film 19d is a film containing metal as a constituent material. The metal thin film 19d is formed by, for example, plating or vapor deposition. The metal thin film 19d preferably includes a film containing Ni as a main component. More preferably, a configuration including an electroless Ni plating film is preferable. In the present embodiment, the metal thin film 19d in the formation region of the uneven oxide film 197 has an electroless Ni plating film. On the other hand, the metal thin film 19d in the region where the uneven oxide film 197 is not formed has an electroless Ni plating film and an Au plating film formed on the electroless Ni plating film. As described above, the reason why the Au plating film does not exist in the formation region of the uneven oxide film 197 is to remove the Au plated film by laser light irradiation and to form the uneven oxide film 197 from the lower electroless Ni plated film. It is. The electroless Ni plating film contains P (phosphorus) in addition to Ni as the main component.

なお、後述するレーザ光の照射条件が同じであれば、無電解Ｎｉめっき膜のほうが、電気Ｎｉめっき膜よりも、凹凸酸化膜１９７の膜厚が厚くなる。無電解Ｎｉめっき膜（Ｎｉ−Ｐ）の融点は、Ｐの含有量にもよるが約８００度程度であり、電気Ｎｉめっき膜（Ｎｉ）の融点は、約１４５０度である。このように、無電解Ｎｉめっき膜ほうが融点が低いため、低いエネルギーのレーザ光で溶融及び蒸発し、凹凸酸化膜１９７の膜厚が厚くなると考えられる。   If the laser light irradiation conditions described later are the same, the electroless Ni plating film has a thicker uneven oxide film 197 than the electric Ni plating film. The melting point of the electroless Ni plating film (Ni-P) is about 800 degrees depending on the P content, and the melting point of the electric Ni plating film (Ni) is about 1450 degrees. Thus, since the electroless Ni plating film has a lower melting point, it is considered that the electroless Ni plating film is melted and evaporated by a low energy laser beam, and the thickness of the uneven oxide film 197 is increased.

本体部１９０は、対向面１９０ａに、はんだ２０の接続領域１９２を有している。対向面１９０ａには、接続領域１９２を囲むように第１溝部１９３が形成されている。接続領域１９２は、はんだ２０が接続される領域、換言すれば塗布される領域である。 第１溝部１９３は、接続領域１９２から溢れたはんだ２０を収容するために形成されている。本実施形態では、第１溝部１９３が、接続領域１９２を囲むように環状に形成されている。しかしながら、第１溝部１９３は環状に限定されない。例えば、接続領域１９２を囲むように不連続に形成されたものを採用することもできる。第１溝部１９３の深さ及び幅は、余剰のはんだ２０を吸収できるように適宜設定される。   The main body 190 has a connection region 192 for the solder 20 on the opposing surface 190a. A first groove 193 is formed on the facing surface 190 a so as to surround the connection region 192. The connection region 192 is a region to which the solder 20 is connected, in other words, a region to be applied. The first groove 193 is formed to accommodate the solder 20 overflowing from the connection region 192. In the present embodiment, the first groove portion 193 is formed in an annular shape so as to surround the connection region 192. However, the first groove 193 is not limited to an annular shape. For example, those formed discontinuously so as to surround the connection region 192 may be employed. The depth and width of the first groove portion 193 are appropriately set so that the excess solder 20 can be absorbed.

延設部１９１は、対向面１９１ａに、対応するはんだ２１，２５の接続領域１９４を有している。接続領域１９４は、はんだ２１，２５で共通の形状となっている。対向面１９１ａのうち、接続領域１９４を囲む周囲領域１９５の一部には第２溝部１９６が形成されて周囲領域１９５のうち、第２溝部１９６以外の部分には、凹凸酸化膜１９７が形成されている。接続領域１９４は、はんだ２１，２５が接続される領域である。周囲領域１９５は、図６に破線で示すように、接続領域１９４を取り囲む環状の仮想領域である。   The extended portion 191 has a connection region 194 for the corresponding solders 21 and 25 on the opposing surface 191a. The connection region 194 has a shape common to the solders 21 and 25. A second groove 196 is formed in a part of the surrounding area 195 surrounding the connection area 194 in the facing surface 191a, and a concavo-convex oxide film 197 is formed in a part other than the second groove 196 in the surrounding area 195. ing. The connection region 194 is a region where the solders 21 and 25 are connected. The surrounding area 195 is an annular virtual area surrounding the connection area 194 as indicated by a broken line in FIG.

第２溝部１９６は、接続領域１９４から溢れたはんだ２１，２５を収容するために形成されている。第２溝部１９６は、周囲領域１９５のうちの一部に形成されている。   The second groove 196 is formed to accommodate the solder 21 and 25 overflowing from the connection region 194. The second groove 196 is formed in a part of the surrounding area 195.

本実施形態では、第２溝部１９６が、接続領域１９４を挟むように、複数箇所に形成されている。第２溝部１９６は、平面略矩形状の接続領域１９４における相対する２辺に隣接するように形成されている。具体的には、Ｙ方向において接続領域１９４を挟むように、第２溝部１９６が形成されている。すなわち、延設部１９１の延設方向に直交する方向において接続領域１９４を挟むように、第２溝部１９６が２箇所に形成されている。また、第２溝部１９６は、平面略矩形状をなす接続領域１９４の相対する２辺に隣接しつつし、当該２辺の一端から他端にわたってそれぞれ形成されている。なお、第２溝部１９６の深さ及び幅は、余剰のはんだ２１，２５を収容できるように適宜設定される。   In the present embodiment, the second groove 196 is formed at a plurality of locations so as to sandwich the connection region 194. The second groove portion 196 is formed so as to be adjacent to two opposite sides in the connection region 194 having a substantially rectangular plane. Specifically, the second groove portion 196 is formed so as to sandwich the connection region 194 in the Y direction. That is, the second groove portion 196 is formed at two locations so as to sandwich the connection region 194 in a direction orthogonal to the extending direction of the extending portion 191. Further, the second groove portion 196 is formed from one end of the two sides to the other end while adjoining two opposite sides of the connection region 194 having a substantially rectangular plane shape. The depth and width of the second groove 196 are set as appropriate so that the excess solder 21 and 25 can be accommodated.

凹凸酸化膜１９７は、図６に示すように、周囲領域１９５のうちの第２溝部１９６が形成されている部分以外に形成されている。すなわち、周囲領域１９５の一部に第２溝部１９６が形成され、残りの部分に凹凸酸化膜１９７が形成されている。本実施形態では、対向面１９１ａのうち、接続領域１９４及び第２溝部１９６以外の部分に凹凸酸化膜１９７が形成されている。すなわち、周囲領域１９５より外側にも、凹凸酸化膜１９７が形成されている。このように凹凸酸化膜１９７は、対向面１９１ａにおいて、接続領域１９４と第２溝部１９６を囲むように、接続領域１９４及び第２溝部１９６以外の部分の全面に形成されている。なお、図６では、凹凸酸化膜１９７の形成範囲を明確化するために、ハッチングを施している。   As shown in FIG. 6, the uneven oxide film 197 is formed in a portion other than the portion where the second groove portion 196 is formed in the surrounding region 195. That is, the second groove portion 196 is formed in a part of the surrounding region 195, and the uneven oxide film 197 is formed in the remaining portion. In the present embodiment, a concavo-convex oxide film 197 is formed in a portion of the facing surface 191a other than the connection region 194 and the second groove 196. That is, the uneven oxide film 197 is also formed outside the surrounding region 195. As described above, the uneven oxide film 197 is formed on the entire surface other than the connection region 194 and the second groove portion 196 so as to surround the connection region 194 and the second groove portion 196 on the opposing surface 191a. In FIG. 6, hatching is performed to clarify the formation range of the uneven oxide film 197.

凹凸酸化膜１９７は、金属薄膜１９ｄにレーザ光を照射することで、金属薄膜１９ｄを構成する金属を酸化して形成されている。すなわち、凹凸酸化膜１９７は、金属薄膜１９ｄを酸化することで、金属薄膜１９ｄの表面に形成された酸化物の膜である。このため、金属薄膜１９ｄの一部分が、凹凸酸化膜１９７を提供しているとも言える。金属薄膜１９ｄの表面のうち、凹凸酸化膜１９７の形成領域には、図７に示すように凹部１９ｅが形成されている。この凹部１９ｅは、後述するように、パルス発振のレーザ光の照射により形成されている。例えば、１パルスごとに１つの凹部１９ｅが形成されている。凹部１９ｅは、レーザ光のスポットに対応している。また、レーザ光の走査方向において、隣り合う凹部１９ｅが連なっている。各凹部１９ｅの幅は、５μｍ〜３００μｍとなっている。また、凹部１９ｅの深さは、０．５μｍ〜５μｍとなっている。   The uneven oxide film 197 is formed by oxidizing the metal constituting the metal thin film 19d by irradiating the metal thin film 19d with laser light. That is, the uneven oxide film 197 is an oxide film formed on the surface of the metal thin film 19d by oxidizing the metal thin film 19d. For this reason, it can be said that a part of the metal thin film 19d provides the uneven oxide film 197. In the surface of the metal thin film 19d, in the formation region of the uneven oxide film 197, a recess 19e is formed as shown in FIG. As will be described later, the recess 19e is formed by irradiation with pulsed laser light. For example, one recess 19e is formed for each pulse. The recess 19e corresponds to a laser beam spot. Further, adjacent recesses 19e are continuous in the scanning direction of the laser beam. The width of each recess 19e is 5 μm to 300 μm. Moreover, the depth of the recessed part 19e is 0.5 micrometer-5 micrometers.

なお、凹部１９ｅの深さが０．５μｍより浅いと、レーザ光の照射による金属薄膜１９ｄの表面の溶融及び蒸着が不十分となり、後述する凹凸酸化膜１９７が形成され難くなる。凹部１９ｅの深さが５μｍよりも深いと、金属薄膜１９ｄの表面が溶融飛散しやすくなり、蒸着よりも溶融飛散による表面形成が支配的となり、凹凸酸化膜１９７が形成され難くなる。   If the depth of the recess 19e is less than 0.5 μm, the surface of the metal thin film 19d is not sufficiently melted and deposited by the laser beam irradiation, and the uneven oxide film 197 described later is difficult to be formed. If the depth of the recess 19e is deeper than 5 μm, the surface of the metal thin film 19d is likely to be melted and scattered, and surface formation by melting and scattering becomes more dominant than vapor deposition, and the uneven oxide film 197 is difficult to be formed.

本実施形態では、凹凸酸化膜１９７を構成する成分のうち、８０％はＮｉ２Ｏ３、１０％はＮｉＯ、残り１０％がＮｉとなっている。このように、凹凸酸化膜１９７の主成分は、金属薄膜１９ｄを構成するＮｉの酸化物である。すなわち、凹凸酸化膜１９７は、２層構造の金属薄膜１９ｄのうち、Ａｕめっき膜由来ではなく、無電解Ｎｉめっき膜由来である。凹凸酸化膜１９７の平均膜厚は、１０ｎｍ〜数百ｎｍとなっている。凹凸酸化膜１９７は、凹部１９ｅを有する金属薄膜１９ｄの表面の凹凸に倣って形成されている。また、凹部１９ｅの幅よりも細かいピッチで凹凸が形成されている。すなわち、非常に微細な凹凸が形成されている。換言すれば、複数の凸部１９ｆ（柱状体）が、細かいピッチで形成されている。例えば、凸部１９ｆの平均幅が１ｎｍ〜３００ｎｍ、凸部１９ｆ間の平均間隔が１ｎｍ〜３００ｎｍとなっている。 In the present embodiment, among the components constituting the uneven oxide film 197, 80% is Ni 2 O 3 , 10% is NiO, and the remaining 10% is Ni. Thus, the main component of the uneven oxide film 197 is an oxide of Ni constituting the metal thin film 19d. That is, the concavo-convex oxide film 197 is not derived from the Au plating film but from the electroless Ni plating film in the metal thin film 19d having a two-layer structure. The average film thickness of the uneven oxide film 197 is 10 nm to several hundred nm. The uneven oxide film 197 is formed following the unevenness on the surface of the metal thin film 19d having the recess 19e. Further, irregularities are formed at a pitch finer than the width of the recess 19e. That is, very fine irregularities are formed. In other words, the plurality of convex portions 19f (columnar bodies) are formed at a fine pitch. For example, the average width of the convex portions 19f is 1 nm to 300 nm, and the average interval between the convex portions 19f is 1 nm to 300 nm.

本実施形態では、第２ヒートシンク１９における延設部１９１の対向面１９１ａにおいて、第２はんだ２１，２５の接続領域１９４及び第２溝部１９６以外の部分に凹凸酸化膜１９７が形成されている。このように凹凸酸化膜１９７を形成すると、凹凸酸化膜１９７を形成していない構成、すなわち、金属薄膜１９ｄの表面が露出する構成に比べて、第２はんだ２１，２５に対する濡れ性を低下させることができる。   In the present embodiment, an uneven oxide film 197 is formed in a portion other than the connection region 194 of the second solders 21 and 25 and the second groove portion 196 on the facing surface 191 a of the extending portion 191 in the second heat sink 19. When the uneven oxide film 197 is formed in this way, the wettability with respect to the second solders 21 and 25 is reduced as compared with the structure in which the uneven oxide film 197 is not formed, that is, the structure in which the surface of the metal thin film 19d is exposed. Can do.

また、凹凸酸化膜１９７を有することで、延設部１９１の対向面１９１ａに微細な凹凸が形成されている。このような粗化面には、はんだ２１，２５入り込み難い。このため、はんだ２１，２５の一部と対向面１９１ａとの接触面積が小さくなり、はんだ２１，２５の一部は表面張力によって球状になる。すなわち、接触角が大きくなる。したがって、凹凸酸化膜１９７が形成された部分において、はんだ２１，２５に対する濡れ性を低くすることができる。   Further, by having the uneven oxide film 197, fine unevenness is formed on the opposing surface 191a of the extended portion 191. It is difficult for solder 21 and 25 to enter such a roughened surface. For this reason, the contact area between a part of the solders 21 and 25 and the opposing surface 191a becomes small, and part of the solders 21 and 25 becomes spherical due to surface tension. That is, the contact angle increases. Therefore, the wettability with respect to the solders 21 and 25 can be lowered in the portion where the uneven oxide film 197 is formed.

また、凹凸酸化膜１９７を有することで、対向面１９１ａと封止樹脂体１０との接触面積が増える。さらには、封止樹脂体１０が凹凸酸化膜１９７の凹凸に絡みついてアンカー効果が生じる。したがって、対向面１９１ａと封止樹脂体１０との密着性を向上し、封止樹脂体１０との間に強固な接続構造を形成することができる。特にＮｉを含む金属薄膜１９ｄを形成すると、長期にわたって安定した接続構造を保持することができる。   Further, by providing the uneven oxide film 197, the contact area between the facing surface 191a and the sealing resin body 10 increases. Furthermore, the sealing resin body 10 is entangled with the unevenness of the uneven oxide film 197 and an anchor effect is produced. Therefore, the adhesion between the facing surface 191a and the sealing resin body 10 can be improved, and a strong connection structure can be formed between the sealing resin body 10 and the sealing surface. In particular, when the metal thin film 19d containing Ni is formed, a stable connection structure can be maintained over a long period of time.

（第１実施形態の製造方法）
次に、図８から図１１に基づき、本実施形態の半導体装置１の製造方法の一例について説明する。 (Manufacturing method of the first embodiment)
Next, an example of a method for manufacturing the semiconductor device 1 according to the present embodiment will be described with reference to FIGS.

まず、半導体装置１を構成する各要素を準備する。すなわち、半導体チップ１２、ターミナル１４、継手部１８及び主端子２２，２３を含む第１ヒートシンク１６、第２ヒートシンク１９、主端子２４、及び信号端子２６をそれぞれ準備する。この準備工程では、第１溝部１９３及び第２溝部１９６を有する第２ヒートシンク１９を準備する。 具体的には、第２ヒートシンク１９を構成する基材１９ｃを準備する。そして、プレス加工や切削などにより、基材１９ｃにおける本体部１９０の対向面１９０ａに第１溝部１９３を形成し、延設部１９１の対向面１９１ａに第２溝部１９６を形成する。第１溝部１９３及び第２溝部１９６の形成後、基材１９ｃの表面全面に、無電解Ｎｉめっき膜を形成し、次に、Ａｕめっき膜を形成する。このように、無電解Ｎｉ膜とＡｕめっき膜を有する金属薄膜１９ｄを形成する。このとき、無電解Ｎｉ膜の膜厚を、１０μｍ程度とする。Ａｕめっき膜を施すことで、はんだ２１，２５に対する濡れ性を向上することができる。   First, each element constituting the semiconductor device 1 is prepared. That is, the first heat sink 16, the second heat sink 19, the main terminal 24, and the signal terminal 26 including the semiconductor chip 12, the terminal 14, the joint portion 18, and the main terminals 22 and 23 are prepared. In this preparation step, a second heat sink 19 having a first groove 193 and a second groove 196 is prepared. Specifically, a base material 19c constituting the second heat sink 19 is prepared. And the 1st groove part 193 is formed in the opposing surface 190a of the main-body part 190 in the base material 19c by press work, cutting, etc., and the 2nd groove part 196 is formed in the opposing surface 191a of the extension part 191. After the formation of the first groove 193 and the second groove 196, an electroless Ni plating film is formed on the entire surface of the substrate 19c, and then an Au plating film is formed. In this way, the metal thin film 19d having the electroless Ni film and the Au plating film is formed. At this time, the thickness of the electroless Ni film is set to about 10 μm. By applying the Au plating film, wettability to the solders 21 and 25 can be improved.

次に、第２ヒートシンク１９に凹凸酸化膜１９７を形成する。具体的には、第２ヒートシンク１９の延設部１９１における対向面１９１ａうち、はんだ２１，２５の接続領域１９４及び第２溝部１９６以外の部分に、パルス発振のレーザ光を照射する。   Next, an uneven oxide film 197 is formed on the second heat sink 19. Specifically, a portion of the opposing surface 191 a of the extended portion 191 of the second heat sink 19 other than the connection region 194 of the solders 21 and 25 and the second groove 196 is irradiated with pulsed laser light.

具体的には、レーザ光の照射により、金属薄膜１９ｄのうち、上層のＡｕめっき膜を除去する。また、下層の無電解Ｎｉめっき膜の表層部分を溶融させるとともに、蒸発（気化）させて、外気中に浮遊させる。パルス発振のレーザ光は、エネルギー密度が０Ｊ／ｃｍ２より大きく１００Ｊ／ｃｍ２以下で、パルス幅が１μ秒以下となるように調整される。この条件を満たすために、ＹＡＧレーザ、ＹＶＯ４レーザ、ファイバレーザなどを採用することができる。例えば、ＹＡＧレーザの場合、エネルギー密度が１Ｊ／ｃｍ２以上であればよい。無電解Ｎｉめっき膜の場合、後述するように例えば、５Ｊ／ｃｍ２程度でも加工することができる。なお、エネルギー密度は、パルスフルーエンスとも称される。 Specifically, the upper Au plating film of the metal thin film 19d is removed by laser light irradiation. In addition, the surface layer portion of the lower electroless Ni plating film is melted and evaporated (vaporized) to float in the outside air. Pulsed laser light energy density is large 100 J / cm 2 or less than 0 J / cm 2, the pulse width is adjusted to be equal to or less than 1μ seconds. In order to satisfy this condition, a YAG laser, a YVO 4 laser, a fiber laser, or the like can be employed. For example, in the case of a YAG laser, the energy density may be 1 J / cm 2 or more. In the case of an electroless Ni plating film, as will be described later, for example, it can be processed even at about 5 J / cm 2 . The energy density is also referred to as pulse fluence.

このとき、レーザ光の光源と第２ヒートシンク１９とを相対的に移動させることにより、図８に示すように、レーザ光を対向面１９１ａの複数の位置に順に照射する。なお、レーザ光の光源を移動させてもよいし、第２ヒートシンク１９を移動させてもよい。さらには、ミラーの回転動作によって、レーザ光を走査してもよい。すなわち、レーザ光を走査することで、対向面１９１ａの複数の位置にレーザ光を順に照射してもよい。接続領域１９４及び第２溝部１９６を除くように、例えば、レーザ光をＹ方向に走査して対向面１９１ａの一端から他端まで照射する。照射が完了すると、Ｘ方向においてレーザ光の照射領域をずらす。すなわち、Ｘ方向にレーザ光を走査する。そして、同様にＹ方向に走査して、一端から他端までレーザ光を照射する。これを繰り返すことで、延設部１９１の対向面１９１ａのうち、接続領域１９４及び第２溝部１９６を除く部分のほぼ全域にレーザ光を照射する。すなわち、ＸＹ座標における所定ピッチの格子点に、レーザ光を照射する。   At this time, by relatively moving the light source of the laser light and the second heat sink 19, the laser light is sequentially applied to a plurality of positions on the facing surface 191 a as shown in FIG. 8. The laser light source may be moved, or the second heat sink 19 may be moved. Further, the laser beam may be scanned by rotating the mirror. That is, the laser beam may be sequentially irradiated to a plurality of positions on the facing surface 191a by scanning the laser beam. For example, laser light is scanned in the Y direction so as to exclude the connection region 194 and the second groove portion 196 and irradiate from one end to the other end of the facing surface 191a. When the irradiation is completed, the irradiation region of the laser beam is shifted in the X direction. That is, the laser beam is scanned in the X direction. Similarly, scanning is performed in the Y direction, and laser light is irradiated from one end to the other end. By repeating this, laser light is irradiated to almost the entire area of the opposing surface 191 a of the extended portion 191 except for the connection region 194 and the second groove portion 196. That is, a laser beam is irradiated to a lattice point having a predetermined pitch in the XY coordinates.

本実施形態では、隣り合うレーザ光のスポット（１パルスによる照射範囲）がＹ方向において一部重なるようにして、Ｙ方向においてレーザ光を走査する。また、隣り合うレーザ光のスポットがＸ方向において一部重なるようにして、Ｘ方向においてレーザ光を走査する。 このように、レーザ光を照射し、金属薄膜１９ｄの表面を溶融、気化させることで、金属薄膜１９ｄの表面には、凹部１９ｅが形成される。金属薄膜１９ｄのうち、レーザ光を照射した部分の平均厚みは、レーザ光を照射しない部分の平均厚みよりも薄くなる。   In this embodiment, the laser beam is scanned in the Y direction so that adjacent laser beam spots (irradiation range by one pulse) partially overlap in the Y direction. Further, the laser beam is scanned in the X direction so that adjacent laser beam spots partially overlap in the X direction. Thus, the laser beam is irradiated to melt and vaporize the surface of the metal thin film 19d, whereby a recess 19e is formed on the surface of the metal thin film 19d. Of the metal thin film 19d, the average thickness of the portion irradiated with the laser light is thinner than the average thickness of the portion not irradiated with the laser light.

次に、溶融した金属薄膜１９ｄ（無電解Ｎｉめっき膜）の部分を凝固させる。具体的には、溶融して気化した金属薄膜１９ｄを、レーザ光が照射された部分やその周辺部分に蒸着させる。このように、溶融して気化した金属薄膜１９ｄを蒸着させることにより、金属薄膜１９ｄの表面上に、凹凸が連続する凹凸酸化膜１９７が形成される。以上により、対向面１９１ａのうちはんだ２１の接続領域１９４及び第２溝部１９６以外の表面上に、凹凸酸化膜１９７が形成される。レーザ光の照射によって形成された凹凸酸化膜１９７の膜厚は、自然酸化膜に較べて十分に厚く、１０ｎｍ以上の厚みとなっている。以上により、第１溝部１９３及び第２溝部１９６に加え、凹凸酸化膜１９７を有する第２ヒートシンク１９の準備が完了する。   Next, the molten metal thin film 19d (electroless Ni plating film) is solidified. Specifically, the metal thin film 19d that has been melted and vaporized is deposited on the portion irradiated with the laser light and its peripheral portion. In this way, by depositing the metal thin film 19d that has been melted and vaporized, a concavo-convex oxide film 197 having concavities and convexities is formed on the surface of the metal thin film 19d. As described above, the uneven oxide film 197 is formed on the surface other than the connection region 194 of the solder 21 and the second groove 196 in the facing surface 191a. The thickness of the concavo-convex oxide film 197 formed by laser light irradiation is sufficiently larger than that of the natural oxide film, and is 10 nm or more. Thus, the preparation of the second heat sink 19 having the uneven oxide film 197 in addition to the first groove portion 193 and the second groove portion 196 is completed.

上記したように、レーザ光のスポットが、例えば、Ｙ方向において一部重なるように、Ｙ方向にレーザ光を走査するとともに、スポットがＸ方向において一部重なるように、Ｘ方向にレーザ光を走査する。したがって、レーザ光のスポットに対応して形成される複数の凹部１９ｅは、Ｙ方向において連なるとともに、Ｘ方向においても連なる。これにより、レーザ照射痕である凹部１９ｅは、鱗状となる。   As described above, for example, the laser beam is scanned in the Y direction so that the laser beam spot partially overlaps in the Y direction, and the laser beam is scanned in the X direction so that the spot partially overlaps in the X direction. To do. Therefore, the plurality of recesses 19e formed corresponding to the laser beam spots are continuous in the Y direction and also in the X direction. Thereby, the recessed part 19e which is a laser irradiation trace becomes a scale shape.

なお、レーザ光の照射において、エネルギー密度を１００Ｊ／ｃｍ２よりも大きい１５０Ｊ／ｃｍ２や、３００Ｊ／ｃｍ２とした場合、凹凸酸化膜１９７が形成されなかった。また、パルス発振ではなく、連続発振のレーザ光を照射した場合にも、凹凸酸化膜１９７が形成されなかった。 Incidentally, the irradiation of the laser beam, the energy density large and 150 J / cm 2 than 100 J / cm 2, when a 300 J / cm 2, uneven oxide film 197 is not formed. Further, the uneven oxide film 197 was not formed even when continuous oscillation laser light was irradiated instead of pulse oscillation.

次に、図９に示すように、はんだ１７を介して発熱部１１と第１ヒートシンク１６を接続し、接続体３０を形成する。本実施形態では、接続体３０として、上アーム側の接続体３０Ｈと、下アーム側の接続体３０Ｌを形成する。   Next, as shown in FIG. 9, the heat generating portion 11 and the first heat sink 16 are connected via the solder 17 to form a connection body 30. In the present embodiment, as the connection body 30, an upper arm side connection body 30H and a lower arm side connection body 30L are formed.

先ず接続体３０Ｈの形成方法について説明する。図９に示すように、第１ヒートシンク１６Ｈの対向面１６ａ上に、はんだ１７Ｈを介して、半導体チップ１２Ｈを配置する。次に、半導体チップ１２Ｈ上に、例えば、予め両面にはんだ１５Ｈ及びはんだ２０Ｈが迎えはんだとして配置されたターミナル１４Ｈを、はんだ１５Ｈが半導体チップ１２Ｈ側となるように配置する。また、はんだ２０Ｈについては、半導体装置１における高さばらつきを吸収可能な量を配置しておく。   First, a method for forming the connection body 30H will be described. As shown in FIG. 9, the semiconductor chip 12H is disposed on the facing surface 16a of the first heat sink 16H via the solder 17H. Next, on the semiconductor chip 12H, for example, the terminal 14H in which the solder 15H and the solder 20H are arranged in advance on both sides as a solder is arranged so that the solder 15H is on the semiconductor chip 12H side. Further, the solder 20H is disposed in an amount capable of absorbing the height variation in the semiconductor device 1.

そして、この積層状態で、はんだ１５Ｈ，１７Ｈ，２０Ｈをリフロー（１ｓｔリフロー）させることにより、はんだ１７Ｈを介して、半導体チップ１２Ｈと第１ヒートシンク１６Ｈとを接続する。また、はんだ１５Ｈを介して、半導体チップ１２Ｈとターミナル１４Ｈとを接続する。はんだ２０Ｈについては、接続対象である第２ヒートシンク１９Ｈがまだないので、表面張力により、第２ヒートシンク１９Ｈとの対向面の中心を頂点として盛り上がった形状となる。   Then, in this laminated state, the solder 15H, 17H, and 20H are reflowed (1st reflow), thereby connecting the semiconductor chip 12H and the first heat sink 16H via the solder 17H. Further, the semiconductor chip 12H and the terminal 14H are connected via the solder 15H. Since there is no second heat sink 19H to be connected yet, the solder 20H has a shape that rises with the center of the surface facing the second heat sink 19H as a vertex due to surface tension.

接続体３０Ｌも、接続体３０Ｈと同様に形成することができる。異なる点は、リフローの前に、継手部１８における延設部１９１Ｈとの対向面上に、はんだ２１を配置する。はんだ２１については、はんだ２０Ｈと同様に、半導体装置１における高さばらつきを吸収可能な量を配置しておく。   The connection body 30L can also be formed similarly to the connection body 30H. A different point is that the solder 21 is disposed on the surface of the joint portion 18 facing the extended portion 191H before reflow. About the solder 21, the quantity which can absorb the height variation in the semiconductor device 1 is arrange | positioned similarly to the solder 20H.

そして、この積層状態で、はんだ１５Ｌ，１７Ｌ，２０Ｌ，２１をリフロー（１ｓｔリフロー）させることにより、はんだ１７Ｌを介して、半導体チップ１２Ｌと第１ヒートシンク１６Ｌとを接続する。また、はんだ１５Ｌを介して、半導体チップ１２Ｌとターミナル１４Ｌとを接続する。はんだ２０Ｌについては、接続対象である第２ヒートシンク１９Ｌがまだないので、表面張力により、第２ヒートシンク１９Ｈとの対向面の中心を頂点として盛り上がった形状となる。はんだ２１も、接続対象である第２ヒートシンク１９Ｈの延設部１９１Ｈがまだないので、表面張力により、盛り上がった形状となる。   Then, in this laminated state, the solder 15L, 17L, 20L, and 21 are reflowed (1st reflow), thereby connecting the semiconductor chip 12L and the first heat sink 16L via the solder 17L. Further, the semiconductor chip 12L and the terminal 14L are connected via the solder 15L. The solder 20L does not yet have the second heat sink 19L to be connected, and thus has a shape that rises with the center of the surface facing the second heat sink 19H as a vertex due to surface tension. Since the solder 21 does not yet have the extended portion 191H of the second heat sink 19H to be connected, the solder 21 has a raised shape due to surface tension.

次に、信号端子２６Ｈ，２６Ｌと対応する半導体チップ１２Ｈ，１２Ｌのパッドを、ボンディングワイヤ２７により接続する。   Next, the pads of the semiconductor chips 12H and 12L corresponding to the signal terminals 26H and 26L are connected by bonding wires 27.

次に、はんだ２０を介して、接続体３０と、対応する第２ヒートシンク１９とを接続する。本実施形態では、はんだ２０Ｈを介して、接続体３０Ｈと第２ヒートシンク１９Ｈを接続するとともに、はんだ２０Ｌを介して、接続体３０Ｌと第２ヒートシンク１９Ｌを接続する。また、はんだ２１を介して、上アームと下アームを接続する。さらに、はんだ２５を介して、主端子２４と延設部１９１Ｌを接続する。すなわち、はんだ２０，２１，２５を同時にリフロー（２ｎｄリフロー）させる。   Next, the connection body 30 and the corresponding second heat sink 19 are connected via the solder 20. In the present embodiment, the connection body 30H and the second heat sink 19H are connected via the solder 20H, and the connection body 30L and the second heat sink 19L are connected via the solder 20L. Further, the upper arm and the lower arm are connected via the solder 21. Further, the main terminal 24 and the extending portion 191L are connected via the solder 25. That is, the solders 20, 21, and 25 are simultaneously reflowed (2nd reflow).

図１０及び図１１に示すように、対向面１９ａが上になるようにして第２ヒートシンク１９Ｈ，１９Ｌを台座３１上に配置する。このとき、第２ヒートシンク１９Ｌの延設部１９１Ｌにおける対向面１９１ａ上に、はんだ２５（例えばはんだ箔）を配置する。はんだ２５については、半導体装置１における高さばらつきを吸収可能な量を配置しておく。なお、はんだ２５については、主端子２４上に予め迎えはんだしてもよい。   As shown in FIGS. 10 and 11, the second heat sinks 19 </ b> H and 19 </ b> L are arranged on the pedestal 31 so that the facing surface 19 a faces up. At this time, the solder 25 (for example, solder foil) is disposed on the facing surface 191a of the extending portion 191L of the second heat sink 19L. About the solder 25, the quantity which can absorb the height variation in the semiconductor device 1 is arrange | positioned. The solder 25 may be greeted and soldered on the main terminal 24 in advance.

次に、ターミナル１４Ｈ，１４Ｌが対応する第２ヒートシンク１９Ｈ，１９Ｌに対向するように、接続体３０Ｈ，３０Ｌを第２ヒートシンク１９Ｈ，１９Ｌの対向面１９ａ上に配置する。はんだ２１は、継手部１８と延設部１９１Ｈとにより挟まれる。また、はんだ２５は、延設部１９１Ｌと主端子２４とにより挟まれる。   Next, the connection bodies 30H and 30L are disposed on the facing surface 19a of the second heat sinks 19H and 19L so that the terminals 14H and 14L face the corresponding second heat sinks 19H and 19L. The solder 21 is sandwiched between the joint portion 18 and the extending portion 191H. Further, the solder 25 is sandwiched between the extending portion 191L and the main terminal 24.

そして、第２ヒートシンク１９Ｈ，１９Ｌを下にした状態で２ｎｄリフローを行う。２ｎｄリフローでは、第１ヒートシンク１６Ｈ，１６Ｌ側から荷重を加えることで、半導体装置１の高さが所定の高さとなるようにする。具体的には、図示しないスペーサを、第２ヒートシンク１９Ｈ，１９Ｌの本体部１９０Ｈ，１９０Ｌと台座３１との間に配置し、スペーサに、本体部１９０Ｈ，１９０Ｌと台座３１を接触させる。このようにして、半導体装置１の高さが所定の高さとなるようにする。すなわち、台座３１とスペーサが、高さ調整部材として機能する。   Then, 2nd reflow is performed with the second heat sinks 19H and 19L down. In the 2nd reflow, the load of the first heat sinks 16H and 16L is applied so that the height of the semiconductor device 1 becomes a predetermined height. Specifically, a spacer (not shown) is disposed between the main body portions 190H and 190L of the second heat sinks 19H and 19L and the base 31, and the main body portions 190H and 190L and the base 31 are brought into contact with the spacer. In this way, the height of the semiconductor device 1 is set to a predetermined height. That is, the base 31 and the spacer function as a height adjustment member.

上述のように、高さばらつきを吸収可能な量のはんだ２０Ｈ，２０Ｌをターミナル１４Ｈ，１４Ｌと第２ヒートシンク１９Ｈ，１９Ｌとの間に配置している。したがって、２ｎｄリフローにおいて、ターミナル１４Ｈ，１４Ｌと第２ヒートシンク１９Ｈ，１９Ｌとの間のはんだ２０Ｈ，２０Ｌは不足せず、確実な接続を行うことができる。また、高さばらつきを吸収可能な量のはんだ２１を延設部１９１Ｈと継手部１８との間に配置しているため、２ｎｄリフローにおいて、延設部１９１Ｈと継手部１８との間のはんだ２１は不足せず、確実な接続を行うことができる。さらに、高さばらつきを吸収可能な量のはんだ２５を延設部１９１Ｌと主端子２４との間に配置しているため、２ｎｄリフローにおいて、延設部１９１Ｌと主端子２４との間のはんだ２５は不足せず、確実な接続を行うことができる。   As described above, the amount of solder 20H, 20L capable of absorbing the height variation is disposed between the terminals 14H, 14L and the second heat sinks 19H, 19L. Therefore, in the 2nd reflow, the solders 20H and 20L between the terminals 14H and 14L and the second heat sinks 19H and 19L are not insufficient, and a reliable connection can be performed. Further, since the solder 21 in an amount capable of absorbing the height variation is disposed between the extending portion 191H and the joint portion 18, the solder 21 between the extending portion 191H and the joint portion 18 in the 2nd reflow. There is no shortage and a reliable connection can be made. Further, since the solder 25 in an amount capable of absorbing the height variation is disposed between the extending portion 191L and the main terminal 24, the solder 25 between the extending portion 191L and the main terminal 24 in 2nd reflow. There is no shortage and a reliable connection can be made.

また、上述の荷重の印加などにより、ターミナル１４Ｈ，１４Ｌと第２ヒートシンク１９Ｈ，１９Ｌとの間から、余剰のはんだ２０Ｈ，２０Ｌが押し出される。しかしながら、余剰のはんだ２０Ｈ，２０Ｌは、第１溝部１９３に収容される。同様に、延設部１９１と継手部１８の間から余剰のはんだ２１が押し出される余剰のはんだ２１は、第２溝部１９６に収容される。同様に、延設部１９１Ｌと主端子２４の間から、余剰のはんだ２５が押し出される。しかしながら、余剰のはんだ２５は、凹凸酸化膜１９７上を濡れ拡がらず、第２溝部１９６に収容される。   Further, excess solder 20H, 20L is pushed out between the terminals 14H, 14L and the second heat sinks 19H, 19L by applying the above-described load. However, the excess solders 20H and 20L are accommodated in the first groove portion 193. Similarly, the excess solder 21 from which the excess solder 21 is pushed out between the extended portion 191 and the joint portion 18 is accommodated in the second groove portion 196. Similarly, excess solder 25 is pushed out from between the extended portion 191 </ b> L and the main terminal 24. However, the excess solder 25 does not spread over the uneven oxide film 197 and is accommodated in the second groove 196.

なお、１ｓｔリフロー及び２ｎｄリフローは、水素雰囲気下のリフローとされる。これにより、はんだ付けに不要な金属表面の自然酸化膜を、還元により除去することができる。したがって、各はんだ１５，１７，２０，２１，２５としてフラックスレスのはんだを用いることができる。また、減圧により、はんだ１５，１７，２０，２１，２５にボイドが生じるのを抑制することができる。なお、凹凸酸化膜１９７も還元により厚みが薄くなるため、還元されても凹凸酸化膜１９７が残るように、レーザ光の照射により所望厚みの凹凸酸化膜１９７を形成しておく。上記したように、金属薄膜１９ｄが無電解Ｎｉめっき膜を含むと、凹凸酸化膜１９７を厚くできるため、好ましい。   Note that the first reflow and the second reflow are reflows in a hydrogen atmosphere. Thereby, the natural oxide film on the metal surface unnecessary for soldering can be removed by reduction. Accordingly, a fluxless solder can be used as each of the solders 15, 17, 20, 21, 25. Moreover, it can suppress that a void arises in solder 15,17,20,21,25 by pressure reduction. Since the uneven oxide film 197 is also reduced in thickness by reduction, the uneven oxide film 197 having a desired thickness is formed by laser light irradiation so that the uneven oxide film 197 remains even if reduced. As described above, it is preferable that the metal thin film 19d includes an electroless Ni plating film because the uneven oxide film 197 can be thickened.

次に、トランスファモールド法により封止樹脂体１０の成形を行う。本実施形態では、各ヒートシンク１６，１９が完全に被覆されるように、封止樹脂体１０を形成する。この場合、成形した封止樹脂体１０をヒートシンク１６，１９の一部ごと切削することにより、各ヒートシンク１６，１９の放熱面１６ｂ，１９ｂを露出させる。   Next, the sealing resin body 10 is molded by a transfer mold method. In the present embodiment, the sealing resin body 10 is formed so that the heat sinks 16 and 19 are completely covered. In this case, the molded sealing resin body 10 is cut along with a part of the heat sinks 16 and 19 to expose the heat radiation surfaces 16b and 19b of the heat sinks 16 and 19, respectively.

なお、各ヒートシンク１６，１９の放熱面１６ｂ，１９ｂを成形金型のキャビティ壁面に押し当て、密着させた状態で、封止樹脂体１０を成形してもよい。この場合、封止樹脂体１０を成形した時点で、放熱面１６ｂ，１９ｂが封止樹脂体１０から露出される。このため、成形後の切削が不要となる。   In addition, you may shape | mold the sealing resin body 10 in the state which pressed the heat sinking surfaces 16b and 19b of each heat sink 16 and 19 against the cavity wall surface of the molding die, and was stuck. In this case, when the sealing resin body 10 is molded, the heat radiation surfaces 16 b and 19 b are exposed from the sealing resin body 10. For this reason, the cutting after shaping | molding becomes unnecessary.

そして、リードフレームの不要部分を除去することで、半導体装置１を得ることができる。   Then, the semiconductor device 1 can be obtained by removing unnecessary portions of the lead frame.

次に、上述の第１実施形態の半導体装置１の効果について説明する。   Next, effects of the semiconductor device 1 according to the first embodiment will be described.

本実施形態によると、周囲領域１９５の一部に余剰のはんだ２１，２５を収容する第２溝部１９６が形成されており、残りの部分に、凹凸酸化膜１９７が形成されている。凹凸酸化膜１９７の表面は粗いため、平坦面に比べてはんだ２１，２５の濡れ性を低下させることができる。また、酸化膜は金属表面よりもはんだ２１，２５の濡れ性が低い。したがって、周囲領域１９５のうち、凹凸酸化膜１９７が形成された部分には、はんだ２１，２５が濡れ拡がり難く、余剰のはんだ２１，２５は第２溝部１９６に収容される。このように、周囲領域１９５の一部のみに第２溝部１９６を形成すればよいので、はんだ溢れを抑制しつつ、半導体装置の体格増大を抑制することができる。   According to the present embodiment, the second groove portion 196 that accommodates the excess solder 21 and 25 is formed in a part of the peripheral region 195, and the uneven oxide film 197 is formed in the remaining portion. Since the surface of the uneven oxide film 197 is rough, the wettability of the solders 21 and 25 can be reduced compared to a flat surface. The oxide film has lower wettability of the solders 21 and 25 than the metal surface. Accordingly, in the peripheral region 195, the portions where the uneven oxide film 197 is formed do not easily spread the solders 21 and 25, and the surplus solders 21 and 25 are accommodated in the second groove portion 196. As described above, since the second groove 196 may be formed only in a part of the peripheral region 195, an increase in the size of the semiconductor device can be suppressed while suppressing solder overflow.

また、一般的に、はんだと樹脂とは密着性がよくないことが知られている。そのため、接続領域１９４を囲むように環状の第２溝部１９６を形成すると、使用環境での温度変化などにより、第２溝部１９６に収容されたはんだ２１，２５と封止樹脂体１０との界面に剥離が生じやすい。この場合、延設部１９１の接続領域１９４に接続されたはんだ２１，２５の周囲、すなわちはんだ接合部の周囲に、封止樹脂体１０の密着していない領域が存在することとなる。これにより、封止樹脂体１０によるはんだ接合部の拘束力が低下するため、はんだ２１，２５にクラックなどが生じる虞がある。   Further, it is generally known that the adhesion between the solder and the resin is not good. Therefore, when the annular second groove 196 is formed so as to surround the connection region 194, due to a temperature change in the usage environment, the interface between the solder 21 and 25 accommodated in the second groove 196 and the sealing resin body 10 is formed. Peeling easily occurs. In this case, a region where the sealing resin body 10 is not in close contact exists around the solders 21 and 25 connected to the connection region 194 of the extending portion 191, that is, around the solder joint portion. Thereby, since the restraining force of the solder joint part by the sealing resin body 10 falls, there exists a possibility that a crack etc. may arise in the solders 21 and 25. FIG.

そこで、本実施形態では、周囲領域１９５の一部のみに、第２溝部１９６が形成されている。よって、第２溝部１９６に収容されたはんだ２１，２５と封止樹脂体１０の界面で剥離が生じても、はんだ接合部周りの一部にすぎない。したがって、封止樹脂体１０の剥離による拘束力低下を抑制し、はんだ接合部の接続信頼性を向上することができる。   Therefore, in the present embodiment, the second groove portion 196 is formed only in a part of the surrounding region 195. Therefore, even if peeling occurs at the interface between the solder 21 and 25 accommodated in the second groove 196 and the sealing resin body 10, it is only a part around the solder joint. Therefore, it is possible to suppress a reduction in restraining force due to peeling of the sealing resin body 10 and to improve the connection reliability of the solder joint portion.

さらに、周囲領域１９５の全域に凹凸酸化膜１９７を形成すると、はんだボールの発生が懸念される。なぜなら、高さばらつきを吸収可能な量のはんだ２１を配置したときに、余剰のはんだ２１は凹凸酸化膜１９７に弾かれる。この弾かれたはんだ２１が自身の表面張力によってボール状になるからである。例えば、凹凸酸化膜１９７上にはんだボールが位置すると、延設部１９１と封止樹脂体１０との間にはんだボールが介在するため、上述のような剥離の原因となることがある。また、はんだボールが凹凸酸化膜１９７上を転がって対向面１９１ａの外部に移動し、これにより短絡などが生じる虞もある。   Furthermore, when the uneven oxide film 197 is formed over the entire peripheral region 195, there is a concern about the generation of solder balls. This is because, when an amount of solder 21 that can absorb the height variation is disposed, surplus solder 21 is repelled by the uneven oxide film 197. This is because the repelled solder 21 has a ball shape due to its surface tension. For example, when the solder ball is positioned on the uneven oxide film 197, the solder ball is interposed between the extended portion 191 and the sealing resin body 10, and thus may cause the above-described peeling. Further, the solder ball rolls on the uneven oxide film 197 and moves to the outside of the facing surface 191a, which may cause a short circuit.

これに対し本実施形態では、凹凸酸化膜１９７に加えて第２溝部１９６も形成されており、第２溝部１９６内に余剰のはんだ２１，２５を収容することができる。よって、はんだボールの発生原因である余剰のはんだ２１、２５は凹凸酸化膜１９７が形成された領域に広がりにくくなるので、はんだボールの発生を抑制することができる。   On the other hand, in the present embodiment, the second groove portion 196 is formed in addition to the uneven oxide film 197, and excess solder 21 and 25 can be accommodated in the second groove portion 196. Therefore, the surplus solders 21 and 25 that are the cause of the generation of the solder balls are difficult to spread in the region where the uneven oxide film 197 is formed, so that the generation of the solder balls can be suppressed.

ところで、第２ヒートシンク１９において、本体部１９０のほうが、延設部１９１よりも大きい。このように本体部１９０の熱容量が大きいため、２ｎｄリフロー時において、本体部１９０から延設部１９１に熱が伝達される。本実施形態では、延設部１９１がＸ方向に延設されており、第２溝部１９６は、平面略矩形状の接続領域１９４をＹ方向において挟むように形成されている。このため、本体部１９０から熱が伝達されて第２溝部１９６に収容されたはんだ２１，２５が溶融する際、一方の第２溝部１９６に収容されたはんだ２１，２５と、他方の第２溝部１９６に収容されたはんだ２１，２５とに、同じように熱が伝わる。これにより、一方の第２溝部１９６と他方の第２溝部１９６とで同じようにはんだ２１，２５が溶融する。したがって、２ｎｄリフロー時に、延設部１９１と継手部１８、延設部１９１と主端子２４の位置にずれが生じるのを抑制することができる。   By the way, in the second heat sink 19, the main body portion 190 is larger than the extending portion 191. Since the heat capacity of the main body 190 is thus large, heat is transmitted from the main body 190 to the extending portion 191 during the 2nd reflow. In the present embodiment, the extending portion 191 extends in the X direction, and the second groove portion 196 is formed so as to sandwich the connection region 194 having a substantially planar shape in the Y direction. Therefore, when heat is transmitted from the main body 190 and the solders 21 and 25 accommodated in the second groove 196 melt, the solders 21 and 25 accommodated in the one second groove 196 and the other second groove Similarly, heat is transferred to the solders 21 and 25 accommodated in 196. As a result, the solders 21 and 25 are melted in the same manner in one second groove 196 and the other second groove 196. Therefore, it is possible to suppress the occurrence of a shift in the positions of the extending portion 191 and the joint portion 18 and the extending portion 191 and the main terminal 24 during the 2nd reflow.

また、本実施形態の半導体装置１の製造方法によると、第２溝部１９６及び凹凸酸化膜１９７を形成した後、はんだ２１をリフローして、継手部１８と主端子２４とを接続する。よって、半導体装置の高さばらつきを吸収可能な量のはんだ２１を配置しても、凹凸酸化膜１９７により第２溝部１９６以外へ余剰のはんだ２１が溢れ出ることを抑制することができる。また、第２溝部１９６内に余剰のはんだ２１を収容することができる。これにより、はんだ２１の溢れを抑制することができる。また、周囲領域１９５の一部のみに第２溝部１９６を形成するので、第２溝部１９６を環状とする構成に比べて、半導体装置の体格増大を抑制することができる。なお、第２溝部１９６及び凹凸酸化膜１９７の配置は、上記例に限定されない。周囲領域１９５の一部に第２溝部１９６が形成され、残りの部分に凹凸酸化膜１９７が形成されればよい。例えば、図１２に示す第１変形例では、第２溝部１９６が、Ｘ方向において接続領域１９４を挟むように形成されている。   Further, according to the manufacturing method of the semiconductor device 1 of the present embodiment, after the second groove 196 and the uneven oxide film 197 are formed, the solder 21 is reflowed to connect the joint 18 and the main terminal 24. Therefore, even if an amount of the solder 21 that can absorb the height variation of the semiconductor device is disposed, it is possible to suppress the surplus solder 21 from overflowing beyond the second groove 196 due to the uneven oxide film 197. Further, excess solder 21 can be accommodated in the second groove 196. Thereby, the overflow of the solder 21 can be suppressed. In addition, since the second groove portion 196 is formed only in a part of the peripheral region 195, an increase in the size of the semiconductor device can be suppressed as compared with a configuration in which the second groove portion 196 is annular. The arrangement of the second groove 196 and the uneven oxide film 197 is not limited to the above example. The second groove 196 may be formed in a part of the surrounding region 195 and the uneven oxide film 197 may be formed in the remaining part. For example, in the first modification shown in FIG. 12, the second groove 196 is formed so as to sandwich the connection region 194 in the X direction.

図１３に示す第２変形例では、平面略矩形状の接続領域１９４のうち、相対する２辺の全長ではなく、一部に隣接して第２溝部１９６が形成されている。第１変形例及び第２変形例に示す構成でも、はんだ溢れを抑制しつつ、半導体装置１の体格増大を抑制することができる。   In the second modified example shown in FIG. 13, the second groove portion 196 is formed adjacent to a part of the connection region 194 having a substantially rectangular plane, not the entire length of the two opposite sides. Even in the configurations shown in the first modification and the second modification, an increase in the size of the semiconductor device 1 can be suppressed while suppressing solder overflow.

第２ヒートシンク１９の対向面１９ａのうち、延設部１９１の対向面１９１ａのみに凹凸酸化膜１９７が形成される例を示した。しかしながら、図１４に示す第３変形例のように、本体部１９０の対向面１９０ａにも、凹凸酸化膜１９７が形成された構成を採用することができる。図１４では、対向面１９０ａのうち、接続領域１９２及び第１溝部１９３以外の部分に、凹凸酸化膜１９７が形成されている。これによれば、凹凸酸化膜１９７と封止樹脂体１０との接触面積が増加するため、ヒートシンク１９と封止樹脂体１０との密着性を高めることができる。   The example in which the uneven oxide film 197 is formed only on the facing surface 191a of the extending portion 191 among the facing surface 19a of the second heat sink 19 is shown. However, as in the third modification shown in FIG. 14, a configuration in which the uneven oxide film 197 is also formed on the facing surface 190 a of the main body 190 can be employed. In FIG. 14, an uneven oxide film 197 is formed in a portion other than the connection region 192 and the first groove portion 193 in the facing surface 190a. According to this, since the contact area between the uneven oxide film 197 and the sealing resin body 10 is increased, the adhesion between the heat sink 19 and the sealing resin body 10 can be enhanced.

（第２実施形態）
本実施形態は、先行実施形態を参照できる。このため、先行実施形態に示した半導体装置１及びその製造方法と共通する部分についての説明は省略する。 (Second Embodiment)
This embodiment can refer to the preceding embodiment. For this reason, the description about the part which is common in the semiconductor device 1 and its manufacturing method shown in the previous embodiment is omitted.

本実施形態の半導体装置１は、図１５〜図１８に示すように、半導体チップ１２（発熱部１１）を１つのみ有している。この半導体装置１により、三相インバータを構成する６つのアームのうちの１つが構成される。このような半導体装置１は、１ｉｎ１パッケージとも称される。   As shown in FIGS. 15 to 18, the semiconductor device 1 according to the present embodiment has only one semiconductor chip 12 (heat generating portion 11). This semiconductor device 1 constitutes one of six arms constituting a three-phase inverter. Such a semiconductor device 1 is also referred to as a 1 in 1 package.

第２実施形態の半導体装置１は、本実施形態と同様に、半導体チップ１２を含む発熱部１１が、一対の第１ヒートシンク１６及び第２ヒートシンク１９に挟まれるように配置されている。   As in the present embodiment, the semiconductor device 1 of the second embodiment is arranged such that the heat generating portion 11 including the semiconductor chip 12 is sandwiched between a pair of first heat sink 16 and second heat sink 19.

発熱部１１は、半導体チップ１２と、半導体チップ１２のエミッタ電極１３ｂとはんだ１５を介して接続されたターミナル１４を有している。第１ヒートシンク１６は、はんだ１７を介して半導体チップ１２のコレクタ電極１３ａと接続されている。第１ヒートシンク１６には、主端子２８が連なっている。   The heat generating part 11 has a semiconductor chip 12 and a terminal 14 connected to the emitter electrode 13 b of the semiconductor chip 12 via a solder 15. The first heat sink 16 is connected to the collector electrode 13 a of the semiconductor chip 12 via the solder 17. A main terminal 28 is connected to the first heat sink 16.

半導体装置１が上アームを構成する場合、主端子２８は、直流電源の高電位側に接続される。また、半導体装置１が下アームを構成する場合、主端子２８は、三相モータの出力線に接続される。主端子２８は、第１ヒートシンク１６からＹ方向に延設されて、封止樹脂体１０の側面１０ｃのひとつから外部に突出している。本実施形態では、同一の金属板を加工することで、主端子２２が第１ヒートシンク１６Ｈと一体的に設けられている。   When the semiconductor device 1 constitutes an upper arm, the main terminal 28 is connected to the high potential side of the DC power supply. When the semiconductor device 1 constitutes the lower arm, the main terminal 28 is connected to the output line of the three-phase motor. The main terminal 28 extends from the first heat sink 16 in the Y direction and protrudes from one of the side surfaces 10c of the sealing resin body 10 to the outside. In the present embodiment, the main terminal 22 is integrally provided with the first heat sink 16H by processing the same metal plate.

第２ヒートシンク１９は、本実施形態と同様に、はんだ２０を介して発熱部１１(ターミナル１４)と電気的に接続される本体部１９０と、本体部１９０から延設され、はんだ２５を介して主端子２９と電気的に接続される延設部１９１を有する。半導体装置１が上アームを構成する場合、主端子２９は、三相モータの出力線に接続される。また、半導体装置１が下アームを構成する場合、主端子２９は、直流電源の低電位側に接続される。主端子２９はＹ方向に延設され、主端子２８と同じ側面１０ｃから外部に突出している。   As in the present embodiment, the second heat sink 19 is extended from the main body 190 and the main body 190 electrically connected to the heat generating portion 11 (terminal 14) via the solder 20 and via the solder 25. The extending portion 191 is electrically connected to the main terminal 29. When the semiconductor device 1 constitutes an upper arm, the main terminal 29 is connected to the output line of the three-phase motor. When the semiconductor device 1 constitutes a lower arm, the main terminal 29 is connected to the low potential side of the DC power supply. The main terminal 29 extends in the Y direction and protrudes to the outside from the same side surface 10 c as the main terminal 28.

延設部１９１は、主端子２９の延設方向と同じ方向、すなわちＹ方向に延設されている。主端子２９は、延設部１９１に対し、Ｚ方向において半導体チップ１２側に配置されている。主端子２９は、一端側が、Ｚ方向からの投影視において延設部１９１と重なるように配置されている。延設部１９１と主端子２９との間には、はんだ２１が介在している。   The extending portion 191 extends in the same direction as the extending direction of the main terminal 29, that is, in the Y direction. The main terminal 29 is disposed on the semiconductor chip 12 side in the Z direction with respect to the extending portion 191. The main terminal 29 is arranged so that one end side thereof overlaps with the extending portion 191 in the projection view from the Z direction. Solder 21 is interposed between the extended portion 191 and the main terminal 29.

延設部１９１は、対向面１９１ａに、はんだ２１の接続領域１９４を有している。対向面１９１ａのうち、接続領域１９４を囲む周囲領域１９５の一部には、第２溝部１９６が形成されている。周囲領域１９５のうち、第２溝部１９６以外の部分には、凹凸酸化膜１９７が形成されている。   The extending portion 191 has a connection region 194 for the solder 21 on the opposing surface 191a. A second groove 196 is formed in a part of the surrounding area 195 surrounding the connection area 194 in the facing surface 191a. An uneven oxide film 197 is formed in a portion other than the second groove portion 196 in the surrounding region 195.

第２実施形態の半導体装置１の製造方法については、本実施形態における上アーム又は下アームとして機能する両面放熱構造の製造方法と同様であるので、説明を省略する。   The manufacturing method of the semiconductor device 1 of the second embodiment is the same as the manufacturing method of the double-sided heat dissipation structure that functions as the upper arm or the lower arm in the present embodiment, and thus the description thereof is omitted.

次に、上述の第２実施形態の半導体装置１の効果について説明する。   Next, effects of the semiconductor device 1 according to the second embodiment will be described.

主端子２９と第２ヒートシンク１９とが別部材の場合、主端子２９と延設部１９１との間に、高さばらつきを吸収可能な量のはんだ２５を配置する必要がある。第２実施形態では、延設部１９１における周囲領域１９５の一部に、第２溝部１９６が形成されている。このため、余剰のはんだ２５を第２溝部１９６に収容することができる。   When the main terminal 29 and the second heat sink 19 are separate members, it is necessary to dispose an amount of solder 25 that can absorb height variations between the main terminal 29 and the extending portion 191. In the second embodiment, a second groove 196 is formed in a part of the peripheral region 195 in the extended portion 191. For this reason, the excess solder 25 can be accommodated in the second groove portion 196.

また、周囲領域１９５の残りの部分に、凹凸酸化膜１９７が形成されている。これにより、第２溝部１９６を環状に形成する場合に較べて、はんだ溢れを抑制しつつ、半導体装置１の体格増大を抑制することができる。つまり、１ｉｎ１パッケージの半導体装置１を例示する第２実施形態は、本実施形態と同様の効果を奏する。よって、本実施形態の効果の箇所で述べた内容と同一内容の効果を、第２実施形態においても奏する。   In addition, an uneven oxide film 197 is formed in the remaining portion of the surrounding region 195. Thereby, compared with the case where the 2nd groove part 196 is formed in cyclic | annular form, the physique increase of the semiconductor device 1 can be suppressed, suppressing a solder overflow. That is, the second embodiment illustrating the semiconductor device 1 in a 1 in 1 package has the same effect as this embodiment. Therefore, the same effects as the contents described in the effect section of the present embodiment are also exhibited in the second embodiment.

なお、本実施形態の第２ヒートシンク１９Ｈ，１９Ｌについての変形例は、第２実施形態においても同様に適用することができる。   In addition, the modification about 2nd heat sink 19H, 19L of this embodiment is applicable similarly in 2nd Embodiment.

また、主端子２９が、第２ヒートシンク１９と別部材とされる例を示したが、主端子２８，２９の少なくとも一方が第２ヒートシンク１９と別部材とされた構成に適用できる。   Moreover, although the example in which the main terminal 29 is a separate member from the second heat sink 19 has been shown, the present invention can be applied to a configuration in which at least one of the main terminals 28 and 29 is a separate member from the second heat sink 19.

この明細書の開示は、例示された実施形態に制限されない。開示は、例示された実施形態と、それらに基づく当業者による変形態様を包含する。例えば、本開示は、実施形態において示された要素の組み合わせに限定されない。本開示は、多様な組み合わせによって実施可能である。開示される技術的範囲は、実施形態の記載に限定されない。開示されるいくつかの技術的範囲は、特許請求の範囲の記載によって示され、さらに、特許請求の範囲の記載と均等の意味及び範囲内でのすべての変更を含むものと解されるべきである。   The disclosure of this specification is not limited to the illustrated embodiments. The disclosure encompasses the illustrated embodiments and variations by those skilled in the art based thereon. For example, the present disclosure is not limited to the combination of elements shown in the embodiments. The present disclosure can be implemented in various combinations. The technical scope disclosed is not limited to the description of the embodiments. Some technical scope disclosed is indicated by the description of the scope of claims, and should be understood to include all modifications within the meaning and scope equivalent to the description of the scope of claims. is there.

１ｉｎ１パッケージ及び２ｉｎ１パッケージについて説明をしたが、これらに限られず、三相インバータの３組の上下アームのうち２組の上下アームをなす４ｉｎ１パッケージとしてもよい。さらに、三相インバータの３組の上下アームがひとつのパッケージに集約した６ｉｎ１パッケージとしてもよい。つまり、三相インバータの３組の上下アームの構成として一般的に採用されている半導体装置に適用することができる。   Although the 1 in 1 package and the 2 in 1 package have been described, the present invention is not limited to these, and a 4 in 1 package having two sets of upper and lower arms among the three upper and lower arms of the three-phase inverter may be used. Further, a 6-in-1 package in which three sets of upper and lower arms of a three-phase inverter are integrated into one package may be used. That is, the present invention can be applied to a semiconductor device generally adopted as a configuration of three upper and lower arms of a three-phase inverter.

発熱部１１が、半導体チップ１２に加えて、ターミナル１４を有する例を示した。しかしながら、発熱部１１は少なくとも半導体チップ１２を有していればよい。すなわち、ターミナル１４を有さない発熱部１１を採用することもできる。   The example in which the heat generating part 11 has the terminal 14 in addition to the semiconductor chip 12 is shown. However, the heat generating part 11 only needs to have at least the semiconductor chip 12. That is, the heat generating portion 11 that does not have the terminal 14 can be employed.

金属薄膜１９ｄが、無電解Ｎｉめっき膜とＡｕめっき膜を有する例を示した。しかしながら、金属薄膜１９ｄが、無電解Ｎｉめっき膜のみを有してもよい。   An example in which the metal thin film 19d has an electroless Ni plating film and an Au plating film is shown. However, the metal thin film 19d may have only an electroless Ni plating film.

１…半導体装置、１０…封止樹脂体、１０ａ…一面、１０ｂ…裏面、１０ｃ…側面、１１，１１Ｈ，１１Ｌ…発熱部、１２，１２Ｈ，１２Ｌ…半導体チップ、１２ａ…一面、１２ｂ…裏面、１３ａ…コレクタ電極、１３ｂ…エミッタ電極、１４，１４Ｈ，１４Ｌ…ターミナル、１５，１５Ｈ，１５Ｌ…はんだ、１６，１６Ｈ，１６Ｌ…第１ヒートシンク、１６ａ…対向面、１６ｂ…放熱面、１７，１７Ｈ，１７Ｌ…はんだ、１８…継手部、１９，１９Ｈ，１９Ｌ…第２ヒートシンク、１９ａ…対向面、１９ｂ…放熱面、１９ｃ…基材、１９ｄ…金属薄膜、１９ｅ…凹部、１９ｆ…凸部、１９０，１９０Ｈ，１９０Ｌ…本体部、１９０ａ…対向面、１９１，１９１Ｈ，１９１Ｌ…延設部、１９１ａ…対向面、１９２…接続領域、１９３…第１溝部、１９４…接続領域、１９５…周囲領域、１９６…第２溝部、１９７…凹凸酸化膜、２０，２０Ｈ，２０Ｌ…はんだ、２１…はんだ、２２，２３，２４，２８，２９…主端子、２５…はんだ、２６，２６Ｈ，２６Ｌ…信号端子、２７…ボンディングワイヤ、３０，３０Ｈ，３０Ｌ…接続体、３１…台座 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 10 ... Sealing resin body, 10a ... One surface, 10b ... Back surface, 10c ... Side surface, 11, 11H, 11L ... Heat generating part, 12, 12H, 12L ... Semiconductor chip, 12a ... One surface, 12b ... Back surface, 13a ... Collector electrode, 13b ... Emitter electrode, 14, 14H, 14L ... Terminal, 15, 15H, 15L ... Solder, 16, 16H, 16L ... First heat sink, 16a ... Opposing surface, 16b ... Heat dissipation surface, 17, 17H, 17L ... solder, 18 ... joint portion, 19, 19H, 19L ... second heat sink, 19a ... facing surface, 19b ... radiating surface, 19c ... base material, 19d ... metal thin film, 19e ... concave, 19f ... convex, 190, 190H, 190L ... main body, 190a ... opposing surface, 191, 191H, 191L ... extended portion, 191a ... opposing surface, 192 ... connection region, 193 ... first groove , 194 ... connection area, 195 ... peripheral area, 196 ... second groove, 197 ... uneven oxide film, 20, 20H, 20L ... solder, 21 ... solder, 22, 23, 24, 28, 29 ... main terminal, 25 ... Solder, 26, 26H, 26L ... signal terminal, 27 ... bonding wire, 30, 30H, 30L ... connection body, 31 ... pedestal

Claims (7)

一面（１２ａ）及び前記一面と板厚方向において反対の裏面（１２ｂ）に電極（１３ａ、１３ｂ）がそれぞれ形成された半導体チップ（１２）を含み、通電により発熱する発熱部（１１）と、
前記発熱部の熱を放熱させるために、前記板厚方向において前記発熱部を挟むように配置される一対の放熱部材であって、前記発熱部と対向するように前記板厚方向において前記一面側に配置され、前記一面の電極と電気的に接続された第１部材（１６）、及び、前記発熱部と対向するように前記板厚方向において前記裏面側に配置され、前記裏面の電極と第１はんだ（２０）を介して電気的に接続された本体部（１９０）と、前記本体部から前記板厚方向と直交する直交方向に延設された延設部（１９１）と、を含む第２部材（１９）と、
前記延設部と前記板厚方向において対向するように前記延設部に対して前記半導体チップ側に配置され、第２はんだ（２１，２５）を介して前記延設部と電気的に接続された第３部材（１８，２４）と、を備え、
前記本体部は、前記発熱部と対向する第１面（１９０ａ）において、前記第１はんだの接続領域（１９２）を囲むように形成された第１溝部（１９３）を有し、
前記延設部は、前記第３部材と対向する第２面（１９１ａ）において、前記第２はんだの接続領域（１９４）を囲む周囲領域（１９５）の一部に形成された第２溝部（１９６）と、前記周囲領域のうちの前記第２溝部以外の部分に形成され、表面が連続して凹凸をなす凹凸酸化膜（１９７）と、を有する半導体装置。 A heating part (11) that includes a semiconductor chip (12) having electrodes (13a, 13b) formed on one surface (12a) and the back surface (12b) opposite to the one surface in the thickness direction;
A pair of heat dissipating members disposed so as to sandwich the heat generating portion in the plate thickness direction in order to dissipate heat of the heat generating portion, the one surface side in the plate thickness direction facing the heat generating portion And the first member (16) electrically connected to the electrode on the one surface and the rear surface side in the plate thickness direction so as to face the heat generating portion, A main body part (190) electrically connected via one solder (20), and an extending part (191) extending from the main body part in an orthogonal direction orthogonal to the plate thickness direction. Two members (19);
It arrange | positions at the said semiconductor chip side with respect to the said extension part so as to oppose the said extension part in the said plate | board thickness direction, and is electrically connected with the said extension part via 2nd solder (21, 25). A third member (18, 24),
The main body has a first groove (193) formed so as to surround the connection area (192) of the first solder on the first surface (190a) facing the heat generating part,
The extended portion is a second groove portion (196) formed in a part of a peripheral region (195) surrounding the connection region (194) of the second solder on the second surface (191a) facing the third member. ) And a concavo-convex oxide film (197) formed in a portion other than the second groove portion in the peripheral region and having a continuous rugged surface. 三相インバータを構成する３組の上下アームのうちの１組をなす半導体装置であって、
前記上下アームを構成する上アームの前記発熱部と下アームの前記発熱部とが、前記直交方向に並んで配置されており、
前記上アームの前記第２部材及び前記下アームの前記第２部材が、前記延設部をそれぞれ有し、
前記第３部材として、前記上アーム及び前記下アームのうちの一方の前記第１部材に連なり、他方の前記延設部に接続される継手部（１８）と、一方の前記延設部に接続される主端子（２４）と、を有する請求項１に記載の半導体装置。 A semiconductor device forming one set of three upper and lower arms constituting a three-phase inverter,
The heat generating part of the upper arm and the heat generating part of the lower arm constituting the upper and lower arms are arranged side by side in the orthogonal direction,
The second member of the upper arm and the second member of the lower arm each have the extending portion,
As said 3rd member, it connects with said 1st member of one of said upper arm and said lower arm, and is connected to one said extension part, and the joint part (18) connected to said other extension part. The semiconductor device according to claim 1, further comprising: a main terminal to be operated. 前記第２溝部は、前記第２はんだの接続領域を挟むように、複数箇所に形成されている請求項１又は請求項２に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the second groove is formed at a plurality of locations so as to sandwich a connection region of the second solder. 複数の前記第２溝部は、前記板厚方向及び前記延設部の延設方向の両方向に直交する方向において、前記第２はんだの接続領域を挟んでいる請求項３に記載の半導体装置。   The semiconductor device according to claim 3, wherein the plurality of second groove portions sandwich the connection region of the second solder in a direction orthogonal to both the plate thickness direction and the extending direction of the extending portion. 前記凹凸酸化膜は、前記第１面において前記第１はんだの接続領域及び前記第１溝部以外の領域に形成されるとともに、前記第２面において、前記第２はんだの接続領域及び前記第２溝部以外の領域に形成されている請求項１から４までのいずれか１項に記載の半導体装置。   The uneven oxide film is formed in a region other than the first solder connection region and the first groove portion on the first surface, and the second solder connection region and the second groove portion on the second surface. The semiconductor device according to claim 1, wherein the semiconductor device is formed in a region other than. 前記第１面と前記第２面とが面一になっている請求項１から５までのいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the first surface and the second surface are flush with each other. 一面（１２ａ）及び前記一面と板厚方向において反対の裏面（１２ｂ）に電極（１３ａ、１３ｂ）がそれぞれ形成された半導体チップ（１２）を含み、通電により発熱する発熱部（１１）と、
前記発熱部の熱を放熱させるために、前記板厚方向において前記発熱部を挟むように配置される一対の放熱部材であって、前記発熱部と対向するように前記板厚方向において前記一面側に配置され、前記一面の電極と電気的に接続された第１部材（１６）、及び、前記発熱部と対向するように前記板厚方向において前記裏面側に配置され、前記裏面の電極と第１はんだ（２０）を介して電気的に接続された本体部（１９０）と、前記本体部から前記板厚方向と直交する直交方向に延設された延設部（１９１）と、を含む第２部材（１９）と、
前記延設部と前記板厚方向において対向するように前記延設部に対して前記半導体チップ側に配置され、第２はんだ（２１，２５）を介して前記延設部と電気的に接続された第３部材（１８，２４）と、を備え、
前記本体部は、前記発熱部と対向する第１面（１９０ａ）において、前記第１はんだの接続領域（１９２）を囲むように形成された第１溝部（１９３）を有し、
前記延設部は、前記第３部材と対向する第２面（１９１ａ）において、前記第２はんだの接続領域（１９４）を囲む周囲領域（１９５）の一部に形成された第２溝部（１９６）と、前記周囲領域のうちの前記第２溝部以外の部分に形成され、表面が連続して凹凸をなす凹凸酸化膜（１９７）と、を有する半導体装置の製造方法であって、
前記第１溝部と前記第２溝部とを有する前記第２部材を準備し、
前記延設部にパルス発振のレーザ光を照射して、前記第２溝部とともに前記第２はんだの接続領域を囲むように前記凹凸酸化膜を形成し、
前記半導体チップの前記一面の電極と前記第１部材とを電気的に接続して接続体（３０）を形成し、
前記接続体の前記発熱部と前記本体部との間に前記第１はんだを配置するとともに、前記延設部と前記第３部材との間に前記第２はんだを配置した状態で、前記第１はんだと前記第２はんだをリフローし、前記裏面の電極と前記本体部とを電気的に接続するとともに、前記延設部と前記第３部材とを電気的に接続する半導体装置の製造方法。 A heating part (11) that includes a semiconductor chip (12) having electrodes (13a, 13b) formed on one surface (12a) and the back surface (12b) opposite to the one surface in the thickness direction;
A pair of heat dissipating members disposed so as to sandwich the heat generating portion in the plate thickness direction in order to dissipate heat of the heat generating portion, the one surface side in the plate thickness direction facing the heat generating portion And the first member (16) electrically connected to the electrode on the one surface and the rear surface side in the plate thickness direction so as to face the heat generating portion, A main body part (190) electrically connected via one solder (20), and an extending part (191) extending from the main body part in an orthogonal direction orthogonal to the plate thickness direction. Two members (19);
It arrange | positions at the said semiconductor chip side with respect to the said extension part so as to oppose the said extension part in the said plate | board thickness direction, and is electrically connected with the said extension part via 2nd solder (21, 25). A third member (18, 24),
The main body has a first groove (193) formed so as to surround the connection area (192) of the first solder on the first surface (190a) facing the heat generating part,
The extended portion is a second groove portion (196) formed in a part of a peripheral region (195) surrounding the connection region (194) of the second solder on the second surface (191a) facing the third member. And a concavo-convex oxide film (197) that is formed in a portion other than the second groove portion in the surrounding region and has a continuous concavo-convex surface, (197),
Preparing the second member having the first groove portion and the second groove portion;
Irradiating the extended portion with pulsed laser light to form the uneven oxide film so as to surround the connection region of the second solder together with the second groove portion,
Electrically connecting the electrode of the one surface of the semiconductor chip and the first member to form a connection body (30);
The first solder is disposed between the heat generating portion and the main body portion of the connection body, and the first solder is disposed between the extending portion and the third member. A method of manufacturing a semiconductor device in which the solder and the second solder are reflowed to electrically connect the electrode on the back surface and the main body portion, and to electrically connect the extending portion and the third member.
JP2016047391A 2016-03-10 2016-03-10 Semiconductor device and manufacturing method of the same Pending JP2017159335A (en)

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