JP2022181812A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device with high connection reliability.SOLUTION: A semiconductor device includes a semiconductor element 40, a pair of substrates having the semiconductor element therebetween, a sintered member 101A, and a sealing body 30. The semiconductor element includes a drain electrode provided on one surface of a semiconductor substrate 41, a source electrode 40S provided on a back surface, and a protection film 44 provided on the back surface and including an opening part 440. The source electrode is connected to the substrate through a conductive spacer 70. The sintered member exists between the source electrode and the conductive spacer. The source electrode includes a base electrode 42 with a peripheral part covered with the protection film 44, and a connection electrode 43 formed on the base electrode in the opening part. The sintered member bonds the connection electrode and the conductive spacer with a predetermined distance from an inner peripheral surface 442 of the protection film that defines the opening part.SELECTED DRAWING: Figure 91

Description

The disclosure in this specification relates to semiconductor devices.

Patent Document 1 discloses a semiconductor device including a semiconductor element having main electrodes on both sides, a pair of wiring members (heat sinks) arranged to sandwich the semiconductor element (semiconductor chip), and a sealing body (resin portion). is doing. The contents of the prior art documents are incorporated by reference as descriptions of technical elements in this specification.

JP-A-2005-19447

In Patent Document 1, a base electrode (first metal layer) is formed on one surface of a semiconductor substrate, and a protective film (passivation film) is formed so as to cover the periphery of the base electrode. The protective film has an opening on the base electrode, and the connection electrode (second metal layer, third metal layer) is formed on the base electrode in the opening. The main electrode (emitter electrode) has a base electrode and a connection electrode. Solder joins the main electrode and the conductive spacer (internal heat sink). In this configuration, a triple point of encapsulant, main electrode, and solder is formed. For this reason, thermal stress concentrates on the triple point, and cracks are likely to occur in the base electrode immediately below the boundary between the protective film and the connection electrode. In other words, there is a possibility that the connection reliability may deteriorate due to the thermal stress. Further improvements are desired in the semiconductor device from the viewpoints described above or from other viewpoints not mentioned.

One object of the disclosure is to provide a semiconductor device with high connection reliability.

The semiconductor device disclosed herein is
a semiconductor substrate (41), a first main electrode (40D) provided on one surface of the semiconductor substrate, a second main electrode (40S) provided on the back surface opposite to the one surface in the plate thickness direction, and a semiconductor element (40) having a protective film (44) with an opening (440) for exposing the second main electrode for bonding;
a first wiring member (50) electrically connected to the first main electrode;
a second wiring member (60, 70) arranged so as to sandwich the semiconductor element between itself and the first wiring member in the plate thickness direction, and to which the second main electrode is connected;
a sintered member (101A) interposed between the second main electrode and the second wiring member and joining the second main electrode and the second wiring member;
A sealing body (30) that seals the semiconductor element, the first wiring member, the second wiring member, and the sintered member,
The second main electrode includes a base electrode (42) formed on the back surface of the semiconductor substrate and having a peripheral portion covered with a protective film, and a connection electrode (43) formed on the base electrode in the opening. have
The sintered member joins the connection electrode and the second wiring member with a predetermined distance from the inner peripheral surface (442) of the protective film that defines the opening.

According to the disclosed semiconductor device, the sintered member is employed as the bonding material for bonding the second main electrode and the second wiring member. Unlike solder, the sintered member does not wet and spread on the surfaces of the second main electrode and the second wiring member during bonding. Thereby, the sintered member can be arranged with a predetermined distance from the inner peripheral surface of the protective film. Therefore, no triple point is formed by the sealing body, the second main electrode, and the sintered member that is the bonding material. As a result, concentration of thermal stress can be suppressed, and a semiconductor device with high connection reliability can be provided.

The multiple aspects disclosed in this specification employ different technical means to achieve their respective objectives. Reference numerals in parentheses described in the claims and this section are intended to exemplify the correspondence with portions of the embodiments described later, and are not intended to limit the technical scope. Objects, features, and advantages disclosed in this specification will become clearer with reference to the following detailed description and accompanying drawings.

It is a figure which shows the circuit structure of the power converter device to which the semiconductor device which concerns on 1st Embodiment is applied. 1 is a perspective view showing a semiconductor device; FIG. 1 is a perspective view showing a semiconductor device; FIG. 1 is a plan view showing a semiconductor device; FIG. FIG. 5 is a cross-sectional view taken along line V-V of FIG. 4; FIG. 5 is a cross-sectional view taken along line VI-VI of FIG. 4; FIG. 5 is a cross-sectional view taken along line VII-VII of FIG. 4; FIG. 5 is a cross-sectional view taken along line VIII-VIII of FIG. 4; FIG. 9 is an enlarged view of a region IX shown in FIG. 8; 1 is an exploded perspective view for explaining a semiconductor device; FIG. FIG. 4 is a plan view showing a state in which a semiconductor element is mounted on the substrate on the drain electrode side; FIG. 4 is a plan view showing a circuit pattern of a substrate on the drain electrode side; FIG. 4 is a plan view showing a circuit pattern of a substrate on the source electrode side; FIG. 4 is a diagram showing the arrangement of circuit patterns, semiconductor elements, and terminals on the drain electrode side; FIG. 4 is a diagram showing the arrangement of circuit patterns, semiconductor elements, and terminals on the source electrode side; FIG. 4 is a plan view showing a current loop of a reference example; FIG. 4 is a plan view showing a current loop; FIG. 4 is a side view showing a current loop; It is a figure which shows the current density about a reference example. FIG. 4 is a diagram showing current densities for the present embodiment; It is a top view which shows a modification. It is a top view which shows a modification. FIG. 11 is a plan view showing a circuit pattern of a substrate on the side of a drain electrode in a modified example; FIG. 11 is a plan view showing a circuit pattern of a substrate on the source electrode side in a modified example; It is a cross-sectional view showing a semiconductor device according to a second embodiment. FIG. 4 is a diagram for explaining the effect of inductance Ls; FIG. 4 is a diagram for explaining the effect of inductance Ls; FIG. 4 is a plan view showing a circuit pattern of a substrate on the source electrode side; FIG. 4 is a diagram showing current paths; It is a sectional view showing an arm connection part. FIG. 11 is a plan view showing a modification of the substrate on the source electrode side; FIG. 4 is a plan view showing a state in which a semiconductor element is mounted on the substrate on the drain electrode side; FIG. 4 is a diagram showing current paths; FIG. 11 is a plan view showing a modification of the substrate on the drain electrode side; FIG. 4 is a diagram showing current paths; It is a sectional view showing a modification of an arm connection part. It is a sectional view showing a modification of an arm connection part. FIG. 11 is a plan view showing a circuit pattern of a substrate on the source electrode side in a modified example; FIG. 4 is a cross-sectional view showing warping at high temperature; It is a sectional view showing a semiconductor device concerning a 3rd embodiment. 1 is a cross-sectional view showing a semiconductor device at room temperature; FIG. 1 is a cross-sectional view showing a semiconductor device at high temperature; FIG. It is a figure which shows the relationship between the ratio of thickness T1 and T2, and the amount of warpage. It is sectional drawing which shows a modification. It is sectional drawing which shows a modification. FIG. 11 is an enlarged plan view of the periphery of a signal terminal in a semiconductor device according to a fourth embodiment; FIG. 47 is a cross-sectional view along line XLVII-XLVII of FIG. 46; It is a figure explaining wire bonding. It is sectional drawing which shows a modification. It is sectional drawing which shows a modification. It is sectional drawing which shows a modification. It is sectional drawing which shows a modification. It is a top view which shows a modification. FIG. 4 is a cross-sectional view showing a relay board; FIG. 54 is a cross-sectional view along the LV-LV line of FIG. 53; It is sectional drawing which shows a modification. It is a sectional view showing a semiconductor device concerning a 5th embodiment. FIG. 58 is a plan view seen from the LVIII direction shown in FIG. 57; 58 is an enlarged view of the area LVIX shown in FIG. 57; FIG. FIG. 59 is a diagram in which a bonding material is omitted from FIG. It is a top view which shows a modification. 62 is a plan view seen from the LXII direction shown in FIG. 61; FIG. It is a top view which shows a modification. It is sectional drawing which shows a modification. 65 is an enlarged view of a region LXV shown in FIG. 64; FIG. It is sectional drawing which shows a modification. 67 is an enlarged view of a region LXVII shown in FIG. 66; FIG. It is sectional drawing which shows a modification. It is a sectional view showing a semiconductor device concerning a 6th embodiment. FIG. 4 is a diagram showing the relationship between the glass transition point and linear expansion coefficient of a sealing body and an insulating base material; It is a figure which shows the curvature of a reference example. It is a figure which shows the curvature at the time of high temperature. It is a sectional view showing a semiconductor device concerning a 7th embodiment. 74 is an enlarged view of region LXXIV in FIG. 73; FIG. It is a figure which shows the formation method of a roughening part. It is sectional drawing which shows a modification. It is sectional drawing which shows a modification. It is sectional drawing which shows a modification. It is a sectional view showing the semiconductor device concerning an 8th embodiment. FIG. 80 is an enlarged view of region LXXX in FIG. 79; It is a figure which shows the relationship between a space|interval, thickness, and an inductance. It is a figure which shows the simulation result in the case of space|interval<thickness. It is a figure which shows the simulation result in the case of space>thickness. It is a cross-sectional view showing a semiconductor device according to a ninth embodiment. It is a top view which shows a board|substrate center. 85 is an enlarged view of region LXXXVI in FIG. 84; FIG. FIG. 10 is a diagram showing dimensions and angles; It is a side view of a laminated body. FIG. 20 is a cross-sectional view showing a semiconductor device according to a tenth embodiment; It is a top view which shows a semiconductor element. FIG. 90 is an enlarged view of region XCI of FIG. 89; FIG. 4 is a cross-sectional view showing the arrangement of sintered members; It is sectional drawing which shows the joining method. FIG. 5 is a diagram showing the relationship between the distance between the inner peripheral surface of the protective film and the sintered member and the strain amplitude of the base electrode; FIG. 4 is a cross-sectional view showing the arrangement of solder, which is a joining material; It is a sectional view showing a semiconductor device concerning an 11th embodiment. FIG. 97 is an enlarged view of region XCVII of FIG. 96; FIG. 3 is a plan view showing the arrangement of the semiconductor element, the sintered member, and the uneven oxide film; FIG. 98 is an enlarged view of region XCIX in FIG. 97; It is sectional drawing which shows a modification. FIG. 3 is a plan view showing the arrangement of the semiconductor element, the sintered member, and the uneven oxide film; It is sectional drawing which shows a modification. FIG. 3 is a plan view showing the arrangement of the semiconductor element, the sintered member, and the uneven oxide film; It is sectional drawing which shows a modification. FIG. 21 is a cross-sectional view showing a semiconductor device according to a twelfth embodiment; FIG. 106 is an enlarged view of area CVI in FIG. 105; FIG. 4 is a diagram showing the relationship between Young's modulus and yield stress of the base electrode, sintered layer, and brittle layer. It is sectional drawing which shows a modification. It is sectional drawing which shows a modification. It is sectional drawing which shows a modification. It is a figure which shows the circuit structure of the power converter device to which the semiconductor device which concerns on 13th Embodiment is applied. 1 is a perspective view showing a semiconductor device; FIG. 1 is a plan view showing a semiconductor device; FIG. FIG. 4 is a plan view showing a state in which a semiconductor element is mounted on the substrate on the drain electrode side; FIG. 4 is a plan view showing a circuit pattern of a substrate on the drain electrode side; FIG. 4 is a plan view showing a circuit pattern of a substrate on the source electrode side; 114 is a cross-sectional view along line CXVII-CXVII of FIG. 113; FIG. 114 is a cross-sectional view along line CXVIII-CXVIII of FIG. 113; FIG. 114 is a cross-sectional view along line CXIX-CXIX of FIG. 113; FIG. 114 is a cross-sectional view taken along line CXX-CXX of FIG. 113; FIG. FIG. 121 is an enlarged view of region CXXI of FIG. 120;

A plurality of embodiments will be described below based on the drawings. Note that redundant description may be omitted by assigning the same reference numerals to corresponding components in each embodiment. When only a part of the configuration is described in each embodiment, the configurations of other embodiments previously described can be applied to other portions of the configuration. In addition, not only the combinations of the configurations specified in the description of each embodiment, but also the configurations of a plurality of embodiments can be partially combined even if they are not specified unless there is a particular problem with the combination. .

The semiconductor device of the present embodiment is applied, for example, to a power conversion device for a moving object that uses a rotating electrical machine as a drive source. Mobile objects include, for example, electric vehicles such as electric vehicles (EV), hybrid vehicles (HV), and plug-in hybrid vehicles (PHV), flying vehicles such as drones, ships, construction machinery, and agricultural machinery. An example applied to a vehicle will be described below.

(First embodiment)
First, based on FIG. 1, a schematic configuration of a vehicle drive system 1 will be described.

<Vehicle drive system>
As shown in FIG. 1 , a vehicle drive system 1 includes a DC power supply 2 , a motor generator 3 , and a power conversion device 4 .

The DC power supply 2 is a DC voltage source composed of a rechargeable secondary battery. Secondary batteries are, for example, lithium ion batteries and nickel metal hydride batteries. The motor generator 3 is a three-phase alternating-current rotating electric machine. The motor generator 3 functions as a vehicle drive source, that is, as an electric motor. The motor generator 3 functions as a generator during regeneration. The power converter 4 performs power conversion between the DC power supply 2 and the motor generator 3 .

<Power converter>
Next, based on FIG. 1, the circuit configuration of the power conversion device 4 will be described. The power conversion device 4 includes a power conversion circuit. The power conversion device 4 of this embodiment includes a smoothing capacitor 5 and an inverter 6 that is a power conversion circuit.

Smoothing capacitor 5 mainly smoothes the DC voltage supplied from DC power supply 2 . The smoothing capacitor 5 is connected to a P line 7 that is a power supply line on the high potential side and an N line 8 that is a power supply line on the low potential side. The P line 7 is connected to the positive pole of the DC power supply 2 and the N line 8 is connected to the negative pole of the DC power supply 2 . The positive terminal of smoothing capacitor 5 is connected to P line 7 between DC power supply 2 and inverter 6 . The negative electrode of smoothing capacitor 5 is connected to N line 8 between DC power supply 2 and inverter 6 . A smoothing capacitor 5 is connected in parallel with the DC power supply 2 .

The inverter 6 is a DC-AC conversion circuit. Inverter 6 converts the DC voltage into a three-phase AC voltage and outputs it to motor generator 3 according to switching control by a control circuit (not shown). Thereby, the motor generator 3 is driven to generate a predetermined torque. During regenerative braking of the vehicle, inverter 6 converts the three-phase AC voltage generated by motor generator 3 in response to the torque from the wheels into DC voltage according to switching control by the control circuit, and outputs the DC voltage to P line 7 . Thus, inverter 6 performs bidirectional power conversion between DC power supply 2 and motor generator 3 .

The inverter 6 is configured with upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes called legs. The upper and lower arm circuits 9 each have an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8 with the upper arm 9H on the P line 7 side. A connection point between the upper arm 9</b>H and the lower arm 9</b>L is connected to a corresponding phase winding 3 a in the motor generator 3 via an output line 10 . Inverter 6 has six arms. Each arm is configured with a switching element. At least part of each of P line 7, N line 8 and output line 10 is formed of a conductive member such as a bus bar.

In this embodiment, an n-channel MOSFET 11 is employed as a switching element that constitutes each arm. The number of switching elements forming each arm is not particularly limited. One or more may be used. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

As an example, each arm has two MOSFETs 11 in this embodiment. Two MOSFETs 11 forming one arm are connected in parallel. The drains of two MOSFETs 11 connected in parallel are connected to the P line 7 in the upper arm 9H. The sources of two MOSFETs 11 connected in parallel are connected to the N line 8 in the lower arm 9L. The sources of the two MOSFETs 11 connected in parallel on the upper arm 9H and the drains of the two MOSFETs 11 connected in parallel on the lower arm 9L are connected to each other. The two MOSFETs 11 connected in parallel are turned on and off at the same timing by a common gate driving signal (driving voltage).

A freewheeling diode 12 is connected in antiparallel to each of the MOSFETs 11 . The diode 12 may be a parasitic diode (body diode) of the MOSFET 11 or may be provided separately from the parasitic diode. The anode of diode 12 is connected to the source of corresponding MOSFET 11, and the cathode is connected to the drain. The upper and lower arm circuits 9 for one phase are provided by one semiconductor device 20 . Details of the semiconductor device 20 will be described later.

The power conversion device 4 may further include a converter as a power conversion circuit. A converter is a DC-DC conversion circuit that converts a DC voltage into DC voltages of different values. The converter is provided between the DC power supply 2 and the smoothing capacitor 5 . The converter includes, for example, a reactor and the upper and lower arm circuits 9 described above. According to this configuration, it is possible to step up and down. The power conversion device 4 may include a filter capacitor that removes power noise from the DC power supply 2 . A filter capacitor is provided between the DC power supply 2 and the converter.

The power conversion device 4 may include a drive circuit for switching elements forming the inverter 6 and the like. The drive circuit supplies a drive voltage to the gate of the MOSFET 11 of the corresponding arm based on the drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11 by applying a drive voltage, that is, turns it on and off. A driving circuit is sometimes referred to as a driver.

The power conversion device 4 may include a control circuit for switching elements. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates a drive command based on, for example, a torque request input from a host ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

Various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects a phase current flowing through each phase winding 3a. The rotation angle sensor detects the rotation angle of the rotor of motor generator 3 . A voltage sensor detects the voltage across the smoothing capacitor 5 . The control circuit outputs, for example, a PWM signal as the drive command. The control circuit comprises, for example, a processor and memory. PWM is an abbreviation for Pulse Width Modulation.

<Semiconductor device>
Next, the semiconductor device will be described with reference to FIGS. 2 to 13. FIG. FIG. 2 is a perspective view of the semiconductor device 20. FIG. FIG. 3 is a perspective view of the semiconductor device 20, similar to FIG. FIG. 3 is a transparent view showing the internal structure. FIG. 4 is a plan view of the semiconductor device 20. FIG. FIG. 4 is a transparent view showing the internal structure. 5 is a cross-sectional view taken along line VV in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII of FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII of FIG. 4. FIG. FIG. 9 is an enlarged view of a region IX indicated by a dashed line in FIG.

FIG. 10 is an exploded perspective view for explaining the semiconductor device 20. FIG. In FIG. 10, the lead frame 94 is shown for convenience. FIG. 11 is a plan view showing a state in which the semiconductor element 40 is mounted on the substrate 50. FIG. 12 is a plan view showing the circuit pattern of the surface metal body 52 on the substrate 50. FIG. FIG. 13 is a plan view showing the circuit pattern of the surface metal body 62 on the substrate 60. As shown in FIG.

Hereinafter, the plate thickness direction of the semiconductor element (semiconductor substrate) is defined as the Z direction. The direction orthogonal to the Z direction and in which the semiconductor elements forming the upper arm 9H and the semiconductor elements forming the lower arm 9L are aligned is defined as the Y direction. A direction perpendicular to both the Z direction and the Y direction is defined as the X direction. Unless otherwise specified, a planar shape is defined as a planar shape viewed from the Z direction, in other words, a planar shape along the XY plane defined by the X and Y directions. A planar view from the Z direction may be simply referred to as a planar view. Further, the term "arrangement" is not limited to the mounting surface, and may be indicated as "arrangement" when there is an overlapping positional relationship in a plan view.

As shown in FIGS. 2 to 13, the semiconductor device 20 constitutes one of the upper and lower arm circuits 9 described above, that is, the upper and lower arm circuits 9 for one phase. The semiconductor device 20 includes a sealing body 30 , a semiconductor element 40 , substrates 50 and 60 , conductive spacers 70 , arm connecting portions 80 and external connection terminals 90 .

The encapsulant 30 encapsulates a part of other elements that constitute the semiconductor device 20 . The rest of the other elements are exposed outside the encapsulant 30 . Sealing body 30 is made of resin, for example. An example of the resin is an epoxy resin. The sealing body 30 is made of resin and is molded by, for example, a transfer molding method. Such a sealing body 30 is sometimes referred to as a sealing resin body, mold resin, or resin molded body. Sealing body 30 may be formed using gel, for example. The gel is filled (arranged) in opposing regions of the pair of substrates 50 and 60, for example.

As shown in FIGS. 2 to 4, the sealing body 30 has a substantially rectangular planar shape. The sealing body 30 has one surface 30a and a back surface 30b opposite to the one surface 30a in the Z direction as surfaces forming an outline. One surface 30a and back surface 30b are, for example, flat surfaces. It also has a side surface that connects the one surface 30a and the back surface 30b. The side surfaces include two side surfaces 30c and 30d from which external connection terminals 90 protrude. The side surface 30d is a surface opposite to the side surface 30c in the X direction.

The semiconductor element 40 is formed by forming a switching element on a semiconductor substrate made of silicon (Si), a wide bandgap semiconductor having a wider bandgap than silicon, or the like. Wide bandgap semiconductors include, for example, silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga ₂ O ₃ ), and diamond. The semiconductor element 40 is sometimes called a power element or a semiconductor chip.

The semiconductor element 40 of this embodiment is formed by forming the above-described n-channel MOSFET 11 on a semiconductor substrate made of SiC. The MOSFET 11 has a vertical structure so that the main current flows in the plate thickness direction of the semiconductor element 40 (semiconductor substrate), that is, in the Z direction. The semiconductor element 40 has main electrodes of switching elements on both sides thereof in the plate thickness direction, that is, in the Z direction. Specifically, as a main electrode, it has a drain electrode 40D on one surface and a source electrode 40S on the back surface opposite to the one surface in the Z direction.

When the diode 12 is a parasitic diode, the source electrode 40S serves also as an anode electrode, and the drain electrode 40D serves as a cathode electrode. Diode 12 may be configured on a separate chip from MOSFET 11 . The drain electrode 40D is a high potential side main electrode (first main electrode), and the source electrode 40S is a low potential side main electrode (second main electrode). Below, the drain electrode 40D and the source electrode 40S may be referred to as main electrodes 40D and 40S.

The semiconductor element 40 has a substantially rectangular planar shape. As shown in FIG. 11, the semiconductor element 40 has a pad 40P formed at a different position from the source electrode 40S on the back surface. The source electrode 40S and the pad 40P are exposed from a protective film (not shown) formed on the back surface of the semiconductor substrate. The drain electrode 40D is formed over substantially the entire surface. The source electrode 40S is formed on a portion of the back surface of the semiconductor element 40. As shown in FIG. In plan view, the drain electrode 40D has a larger area than the source electrode 40S.

The pad 40P is a signal electrode. Pad 40P is electrically isolated from source electrode 40S. The pad 40P is formed at the end opposite to the formation region of the source electrode 40S in the Y direction. The pads 40P include pads for gate electrodes.

The semiconductor device 20 includes a plurality of semiconductor elements 40 configured as described above. The configuration of each semiconductor element 40 is common to each other. The plurality of semiconductor elements 40 includes a semiconductor element 40H forming the upper arm 9H and a semiconductor element 40L forming the lower arm 9L. The semiconductor element 40H is sometimes called an upper arm element, and the semiconductor element 40L is sometimes called a lower arm element. Each of the semiconductor elements 40H and 40L is an arm element forming one arm. The semiconductor device 20 of this embodiment includes two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are arranged in the X direction. Similarly, two semiconductor elements 40L are arranged in the X direction. The semiconductor element 40H and the semiconductor element 40L are arranged in the Y direction. The Y direction is the first direction orthogonal to the Z direction, which is the plate thickness direction of the semiconductor element 40 . The X direction is a second direction orthogonal to the Z direction and the first direction (Y direction). The semiconductor device 20 has two rows of semiconductor elements 40H and 40L along the Y direction.

Each semiconductor element 40 is arranged at substantially the same position in the Z direction. A drain electrode 40</b>D of each semiconductor element 40 faces the substrate 50 . A source electrode 40</b>S of each semiconductor element 40 faces the substrate 60 .

The substrates 50 and 60 are arranged so as to sandwich the plurality of semiconductor elements 40 in the Z direction. The substrates 50 and 60 are arranged so that at least parts of them face each other in the Z direction. The substrates 50, 60 include all of the plurality of semiconductor elements 40 (40H, 40L) in plan view.

The substrate 50 is arranged on the drain electrode 40D side with respect to the semiconductor element 40 . The substrate 60 is arranged on the source electrode 40S side with respect to the semiconductor element 40 . The substrate 50 is electrically connected to the drain electrode 40D and provides a wiring function, as will be described later. Similarly, substrate 60 is electrically connected to source electrode 40S and provides a wiring function. Therefore, the substrates 50 and 60 are sometimes called wiring substrates. Substrate 50 is sometimes referred to as the drain substrate and substrate 60 is sometimes referred to as the source substrate. The substrates 50 and 60 provide a heat dissipation function for dissipating heat generated by the semiconductor element 40 . For this reason, the substrates 50 and 60 are sometimes called heat dissipation members. Of the pair of substrates 50 and 60 sandwiching the semiconductor element 40 in the Z direction, the substrate 50 is the first substrate and the substrate 60 is the second substrate.

The substrate 50 has a facing surface 50a facing the semiconductor element 40 and a back surface 50b opposite to the facing surface 50a. The substrate 50 includes an insulating base material 51 , a front metal body 52 and a back metal body 53 . The substrate 50 is a substrate in which an insulating base material 51 and metal bodies 52 and 53 are laminated. The substrate 60 has a facing surface 60a facing the semiconductor element 40 and a back surface 60b opposite to the facing surface 60a. The substrate 60 includes an insulating base material 61 , a front metal body 62 and a back metal body 63 . The substrate 60 is a substrate in which an insulating base material 61 and metal bodies 62 and 63 are laminated. In the substrate 50 which is the first substrate, the insulating base material 51 is the first insulating base material, the surface metal body 52 is the first surface metal body, and the back metal body 53 is the first back metal body. In the substrate 60 which is the second substrate, the insulating base material 61 is the second insulating base material, the surface metal body 62 is the second surface metal body, and the back metal body 63 is the second back metal body. The surface metal bodies 52 and 62 and the back metal bodies 53 and 63 may be simply referred to as metal bodies 52, 53, 62 and 63 below.

The insulating base material 51 electrically separates the front metal body 52 and the back metal body 53 . Similarly, the insulating base material 61 electrically isolates the front metal body 62 and the back metal body 63 . The insulating base materials 51 and 61 are sometimes called insulating layers. The insulating base materials 51 and 61 are made of resin or inorganic ceramic. As the resin, for example, an epoxy resin, a polyimide resin, or the like can be used. Examples of ceramics that can be used include Al ₂ O ₃ (alumina) and Si ₃ N ₄ (silicon nitride). When the insulating base materials 51 and 61 are made of resin, the substrates 50 and 60 are sometimes called metal-resin substrates. When the insulating substrates 51, 61 are ceramic, the substrates 50, 60 are sometimes referred to as metal-ceramic substrates.

In the case of the insulating base materials 51 and 61 using a resin material, an inorganic filler (inorganic filler) may be included in the resin in order to improve heat dissipation, insulation, and the like. The coefficient of linear expansion may be adjusted by adding a filler. Examples of fillers that can be used include Al ₂ O ₃ , SiO ₂ (silicon dioxide), AlN (aluminum nitride), and BN (boron nitride). The insulating base materials 51 and 61 may contain only one type of filler, or may contain a plurality of types.

Considering heat dissipation and insulation, in the case of a resin system, the thickness of each of the insulating bases 51 and 61, that is, the length in the Z direction, is preferably about 50 μm to 300 μm. In the case of ceramics, the thickness of the insulating bases 51 and 61 is preferably about 200 μm to 500 μm. In the Z direction, the front surfaces of the insulating bases 51 and 61 are inner surfaces, that is, surfaces on the semiconductor element 40 side, and the back surfaces opposite to the front surfaces in the Z direction are outer surfaces. The insulating base materials 51 and 61 may have a common (same) material configuration, or may have different material configurations. In this embodiment, resin-based insulating base materials 51 and 61 are employed, and the material configuration is common. The linear expansion coefficients of the insulating base materials 51 and 61 are adjusted to substantially the same value as that of the sealing body 30 by adding a filler to the resin. By adding a filler to the resin, the linear expansion coefficients of the insulating bases 51 and 61 and the sealing body 30 are close to those of the metal (Cu) forming the metal bodies 52 , 53 , 62 and 63 .

Metal bodies 52, 53, 62, 63 are provided, for example, as metal plates or metal foils. The metal bodies 52, 53, 62, and 63 are made of a metal such as Cu or Al that has good electrical and thermal conductivity. The thickness of each of the metal bodies 52, 53, 62, 63 is, for example, approximately 0.1 mm to 3 mm. The surface metal body 52 is arranged on the surface of the insulating base material 51 in the Z direction. The back metal body 53 is arranged on the back surface of the insulating base material 51 . Similarly, the surface metal body 62 is arranged on the surface of the insulating base material 61 in the Z direction. The back metal body 63 is arranged on the back surface of the insulating base material 61 . The insulating base materials 51 and 61 are surfaces facing the semiconductor element 40 in the Z direction. As shown in FIGS. 5 to 9 and the like, the front metal body 52 is thicker than the back metal body 53 in this embodiment. The front metal body 62 is thicker than the back metal body 63 . The surface metal body 52 on the drain electrode 40D side is thicker than the surface metal body 62 on the source electrode 40S side. Alternatively, the back metal bodies 53 and 63 may be thicker than the corresponding front metal bodies 52 and 62 . The thickness of the surface metal body 52 and the back metal body 53 may be substantially equal, or the thickness of the surface metal body 62 and the back metal body 63 may be substantially equal.

The surface metal bodies 52, 62 are patterned. The surface metallurgy 52, 62 provides wiring or circuitry. For this reason, the surface metal bodies 52 and 62 are sometimes referred to as circuit patterns, wiring layers, and circuit conductors. The surface metal bodies 52 and 62 may have a plating film of Ni or Au on the metal surface. Below, the pattern of the surface metal bodies 52 and 62 may be referred to as a circuit pattern. The surface metal body 52 and the non-arranged area of the surface metal body 52 on the surface of the insulating base material 51 constitute the facing surface 50 a of the substrate 50 . Similarly, the surface metal body 62 and the non-arranged area of the surface metal body 62 on the surface of the insulating base material 61 form the facing surface 60 a of the substrate 60 .

For example, surface metal bodies 52 and 62 patterned into a predetermined shape by press working, etching, or the like are prepared and adhered to a laminate having a two-layer structure of insulating base materials 51 and 61 and back metal bodies 53 and 63 to form a substrate. 50, 60 may be formed. The surface metal bodies 52 and 62 may be patterned by cutting or etching after forming a three-layer laminate of the surface metal bodies 52 and 62, the insulating substrates 51 and 61, and the back metal bodies 53 and 63.

The surface metal body 52 has a P wiring 54 and a relay wiring 55 as shown in FIG. 11 and the like. The P wiring 54 and the relay wiring 55 are electrically separated by a predetermined interval (gap). This gap is filled with a sealing body 30 .

The P wiring 54 is connected to a P terminal 91P and a drain electrode 40D of the semiconductor element 40H, which will be described later. The P wiring 54 electrically connects the P terminal 91P and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 is sometimes called a positive wiring or a high-potential power wiring. The relay wiring 55 is connected to the drain electrode 40</b>D of the semiconductor element 40</b>L, the arm connecting portion 80 and the output terminal 92 . The relay wiring 55 electrically connects the arm connecting portion 80 and the drain electrode 40D of the semiconductor element 40L. The relay wiring 55 electrically connects the source electrode 40S of the semiconductor element 40H and the drain electrode of the semiconductor element 40L to the output terminal 92 . In the surface metal body 52 (first surface metal body), the P wiring 54 is the first power supply wiring, and the relay wiring 55 is the first relay wiring.

The P wiring 54 and the relay wiring 55 are arranged side by side in the Y direction. In the Y direction, the P wiring 54 is arranged on the power supply terminal 91 side, and the relay wiring 55 is arranged on the output terminal 92 side. In other words, the P wiring 54 is arranged close to the side surface 30c of the sealing body 30, and the relay wiring 55 is arranged close to the side surface 30d.

The P wiring 54 has a notch 540 . The notch 540 is open on one of four sides of a substantially rectangular plane having the X direction as the longitudinal direction. The notch 540 is provided substantially in the center in the X direction on the side facing the side surface 30c. The P wiring 54 has a base portion 541 and a pair of extension portions 542 . A base 541 and a pair of extensions 542 define a notch 540 . The P-wiring 54 has a substantially U-shaped (concave-shaped) plane shape.

The base portion 541 is a portion closer to the relay wiring 55 than the notch 540 and the extension portion 542, and has a substantially rectangular planar shape. The base 541 overlaps the semiconductor element 40H in plan view. That is, the semiconductor element 40H is arranged on the base portion 541 . A drain electrode 40D of the semiconductor element 40H is connected to the base portion 541 .

The two extending portions 542 extend from the base portion 541 in the same direction, specifically the Y direction, toward the side surface 30c of the sealing body 30 . One of the extended portions 542 is continuous with one end of the base portion 541 in the X direction, and the other is continuous with the other end of the base portion 541 . Both ends of the U-shape of the P wiring 54, that is, the ends of the two extended portions 542 on the side opposite to the base portion 541 are substantially at the same position in the Y direction. A pair of extending portions 542 sandwich the notch 540 in the X direction. As for the length in the Y direction, the base portion 541 is longer than the depth of the notch 540 and the extending portion 542 .

The relay wiring 55 also has a notch 550 . The notch 550 is open on one of the four sides of the substantially rectangular plane. The notch 550 is provided substantially in the center in the X direction on the side facing the side surface 30d. That is, the surface metal body 52 has a notch 540 at one end in the Y direction and a notch 550 at the other end.

The relay wiring 55 has a base portion 551 and a pair of extension portions 552 . A base 551 and a pair of extensions 552 define a notch 550 . The relay wiring 55 has a substantially U-shaped (concave-shaped) plane shape. The base portion 551 is a portion closer to the P wiring 54 than the notch 550 and the extended portion 552, and has a substantially rectangular planar shape. The base 551 overlaps the semiconductor element 40L in plan view. That is, the semiconductor element 40L is arranged on the base portion 551 . A drain electrode 40</b>D of the semiconductor element 40</b>L is connected to the base portion 551 .

The two extending portions 552 extend from the base portion 551 in the same direction, specifically the Y direction, toward the side surface 30 d of the sealing body 30 . One of the extended portions 552 continues near one end of the base portion 551 in the X direction, and the other extends near the other end of the base portion 551 . Both ends of the U-shape of the relay wiring 55, that is, the ends of the two extended portions 552 on the side opposite to the base portion 551 are substantially at the same position in the Y direction. The pair of extensions 552 sandwich the notch 550 in the X direction. As for the length in the Y direction, the base portion 551 is longer than the depth of the notch 550 and the extending portion 552 .

On the other hand, the surface metal body 62 has an N wiring 64 and a relay wiring 65, as shown in FIGS. The N wiring 64 and the relay wiring 65 are electrically separated by a predetermined interval (gap). This gap is filled with a sealing body 30 .

The N wiring 64 is connected to an N terminal 91N and a source electrode 40S of the semiconductor element 40L, which will be described later. The N wiring 64 electrically connects the N terminal 91N and the source electrode 40S of the semiconductor element 40L. N wiring 64 may be referred to as N wiring. The relay wiring 65 is connected to the source electrode 40S and the arm connecting portion 80 of the semiconductor element 40H. The relay wiring 65 electrically connects the source electrode 40S of the semiconductor element 40H and the arm connection portion 80 . In the surface metal body 62 (second surface metal body), the N wiring 64 is the second power supply wiring, and the relay wiring 65 is the second relay wiring.

The N wiring 64 has a base portion 640 and a pair of extension portions 641 . The N wiring 64 has a substantially U-shaped plane. The base 640 is arranged side by side with the relay wiring 65 in the Y direction. The base 640 is arranged on the side 30d in the Y direction. The base 640 has a substantially rectangular planar shape whose longitudinal direction is the X direction. As shown in FIG. 15, the base 640 overlaps the semiconductor element 40L in plan view. That is, the semiconductor element 40L is arranged on the base portion 640 . A source electrode 40S of the semiconductor element 40L is connected to the base 640. As shown in FIG.

The two extending portions 641 extend from the base portion 640 in the same direction, specifically the Y direction, toward the side surface 30c of the sealing body 30 . One of the extended portions 641 is connected to the vicinity of one end of the base portion 640 in the X direction, and the other is connected to the vicinity of the other end of the base portion 640 . Both ends of the U-shape of the N-wiring 64, that is, the ends of the two extended portions 641 opposite to the base portion 640 are positioned substantially at the same position in the Y direction.

The pair of extensions 641 form both ends of the surface metal body 62 in the X direction. The pair of extensions 641 are arranged near the edge of the substrate 60 . A part of each of the pair of extended portions 641 overlaps the P wiring 54 in plan view. As for the length in the Y direction, the extended portion 641 is longer than the base portion 640 . The N wiring 64 also has a notch 642 . The notch 642 is open on one of the four sides of a substantially rectangular plane having the Y direction as the longitudinal direction. The notch 642 is provided substantially in the center in the X direction on the side facing the side surface 30c. A base 640 and a pair of extensions 641 define a notch 642 .

As described above, the relay wiring 65 is arranged side by side with the N wiring 64, specifically the base 640, in the Y direction. In the Y direction, the relay wiring 65 is arranged at a position close to the side surface 30c of the sealing body 30, and the base portion 640 is arranged at a position close to the side surface 30d. The relay wiring 65 is arranged between the pair of extension portions 641 in the X direction. The relay wiring 65 is sandwiched between a pair of extension portions 641 . The relay wiring 65 is arranged in the notch 642 . The relay wiring 65 is arranged with a predetermined interval (gap) from the N wiring 64 . A part of the relay wiring 65 overlaps the P wiring 54 and another part of the relay wiring 65 overlaps the relay wiring 55 in plan view.

As shown in FIG. 15, the relay wiring 65 overlaps the semiconductor element 40H in plan view. That is, the semiconductor element 40H is arranged on the relay wiring 65 . A source electrode 40</b>S of the semiconductor element 40</b>H is connected to the relay wiring 65 . A more detailed example of the circuit pattern of the surface metal body 62 will be described later.

The backside metal bodies 53 and 63 are electrically separated from the circuit including the semiconductor element 40 by the insulating substrates 51 and 61 . The back metal bodies 53 and 63 are sometimes referred to as metal base substrates. Heat generated by the semiconductor element 40 is transmitted to the back metal bodies 53 and 63 via the front metal bodies 52 and 62 and the insulating base materials 51 and 61 . The back metal bodies 53, 63 provide a heat dissipation function. The back metal bodies 53 and 63 of the present embodiment are substantially rectangular in plan view, and the outer contour thereof substantially matches the outer contour of the front metal bodies 52 and 62 . The back metal bodies 53 and 63 are so-called solid conductors that are arranged on almost the entire back surface of the insulating substrates 51 and 61 . As described above, since the linear expansion coefficients of the insulating base materials 51 and 61 are adjusted by adding the filler, warping can be suppressed even if the patterns are changed on the front and back sides. Of course, the back metal bodies 53 and 63 may be patterned so as to match the front metal bodies 52 and 62 in plan view.

The back surface metal bodies 53 and 63 of the present embodiment are arranged over substantially the entire back surfaces of the corresponding insulating base materials 51 and 61 . At least one of the back metal bodies 53 and 63 may be exposed from the sealing body 30 in order to further enhance the heat dissipation effect. In this embodiment, the back metal body 53 is exposed from the one surface 30a of the sealing body 30, and the back metal body 63 is exposed from the back surface 30b. The exposed surface of the back metal body 53 is substantially flush with the one surface 30a. The exposed surface of the back metal body 63 is substantially flush with the back surface 30b. Backside metal bodies 53 and 63 form backside surfaces 50b and 60b of substrates 50 and 60, respectively.

The conductive spacer 70 provides a spacer function to secure a predetermined distance between the semiconductor element 40 and the substrate 60 . For example, conductive spacer 70 secures a height for electrically connecting corresponding signal terminal 93 to pad 40P of semiconductor element 40 . The conductive spacer 70 is located in the middle of the electrical and thermal conduction path between the source electrode 40S of the semiconductor element 40 and the substrate 60, and provides wiring and heat dissipation functions. The conductive spacer 70 contains a metal material such as Cu that has good electrical and thermal conductivity. The conductive spacer 70 may have a plated film on its surface. The conductive spacer 70 is a substantially rectangular columnar body having substantially the same size as the source electrode 40S in plan view.

Conductive spacers 70 are sometimes referred to as terminals, terminal blocks, and metal block bodies. The semiconductor device 20 includes the same number of conductive spacers 70 as the semiconductor elements 40 . Specifically, four conductive spacers 70 are provided. Conductive spacers 70 are individually connected to semiconductor elements 40 .

The arm connecting portion 80 electrically connects the relay wirings 55 and 65 . That is, the arm connecting portion 80 electrically connects the upper arm 9H and the lower arm 9L. The arm connecting portion 80 is provided between the semiconductor element 40H and the semiconductor element 40L in the Y direction. The arm connecting portion 80 is provided in an overlapping region between the relay wiring 55 and the relay wiring 65 in plan view. The arm connecting portion 80 of the present embodiment includes a joint portion 81 and a bonding material 103 which will be described later.

The joint portion 81 is a metal columnar body provided separately from the surface metal bodies 52 and 62 . Such a joint portion 81 is sometimes called a joint terminal. In the Z direction, a bonding material 103 is interposed between one end of the joint portion 81 and the relay wiring 55 , and a bonding material 103 is interposed between the other end and the relay wiring 65 .

Alternatively, the joint portion 81 may be integrally connected to at least one of the surface metal bodies 52 and 62 . In other words, the joint portion 81 may be provided integrally with the surface metal bodies 52 and 62 as part of the substrates 50 and 60 . The arm connecting portion 80 may be configured without the joint portion 81 . In other words, the arm connecting portion 80 may be configured to include only the bonding material 103 .

The external connection terminal 90 is a terminal for electrically connecting the semiconductor device 20 to an external device. The external connection terminal 90 is formed using a metal material with good conductivity such as copper. The external connection terminal 90 is, for example, a plate material. The external connection terminals 90 are sometimes called leads. The external connection terminal 90 includes a power terminal 91 , an output terminal 92 and a signal terminal 93 . The power terminal 91 has a P terminal 91P and an N terminal 91N. P-terminal 91P, N-terminal 91N, and output terminal 92 are main terminals electrically connected to the main electrode of semiconductor element 40 . The signal terminals 93 include a signal terminal 93H on the upper arm 9H side and a signal terminal 93L on the lower arm 9L side.

The power terminal 91 is an external connection terminal 90 electrically connected to the power lines 7 and 8 described above. P terminal 91P is electrically connected to the positive terminal of smoothing capacitor 5 . The P terminal 91P is sometimes referred to as a positive electrode terminal and a high potential power supply terminal. The P terminal 91P is connected to the P wiring 54 of the surface metal body 52 . In other words, the P terminal 91P is connected to the drain electrode 40D of the semiconductor element 40H forming the upper arm 9H.

The P terminal 91P is connected near one end of the P wiring 54 in the Y direction. The P terminal 91P extends in the Y direction from a connection portion (joint portion) with the P wiring 54, and protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30c. The semiconductor device 20 of this embodiment has two P terminals 91P. As shown in FIG. 11, one of the P terminals 91P is connected to one of the pair of extensions 542, and the other is connected to the other one of the pair of extensions 542. As shown in FIG. The P terminal 91P is arranged at a position close to the notch 540 in each of the extended portions 542, that is, inward, so as to be adjacent to the N terminal 91N in plan view. The two P terminals 91P are arranged side by side in the X direction. The two P terminals 91P are arranged at substantially the same position in the Z direction.

N terminal 91N is electrically connected to the negative terminal of smoothing capacitor 5 . The N terminal 91N is sometimes called a negative terminal or a low potential power supply terminal. The N terminal 91N is connected to the N wiring 64 of the surface metal body 62 . In other words, the N terminal 91N is connected to the source electrode 40S of the semiconductor element 40L forming the lower arm 9L.

The N terminal 91N is connected near one end of the N wiring 64 in the Y direction. The N terminal 91N extends in the Y direction from the junction with the N wiring 64, and protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30c. The semiconductor device 20 has two N terminals 91N. As shown in FIG. 15 and the like, one of the N terminals 91N is connected to one of the pair of extensions 641, and the other is connected to the other one of the pair of extensions 641. As shown in FIG. The two N terminals 91N are arranged side by side in the Y direction. The two N terminals 91N are arranged at substantially the same position in the Z direction.

The two N terminals 91N are arranged outside the two P terminals 91P in the X direction. In plan view, one of the N terminals 91N is arranged near one of the P terminals 91P, and the other one of the N terminals 91N is arranged near the other one of the P terminals 91P. The N terminal 91N and the P terminal 91P, which are adjacent in the X direction, face each other at a portion including a portion protruding from the sealing body 30 at their sides.

Output terminal 92 is electrically connected to corresponding phase winding 3 a (stator coil) of motor generator 3 . The output terminal 92 is sometimes called an O terminal, an AC terminal, or the like. As shown in FIGS. 3 and 7 , the output terminal 92 is connected to the relay wiring 55 of the surface metal body 52 on the substrate 50 . That is, the output terminal 92 is connected to the connection point between the upper arm 9H and the lower arm 9L.

The output terminal 92 is connected near one end of the relay wiring 55 in the Y direction. The output terminal 92 extends in the Y direction from the junction with the relay wiring 55 and protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30d. The semiconductor device 20 has two output terminals 92 . One of the output terminals 92 is connected to one of the pair of extensions 552 and the other is connected to the other one of the pair of extensions 552 . The two output terminals 92 are arranged side by side in the X direction. The two output terminals 92 are arranged at substantially the same position in the Z direction.

The signal terminal 93 is electrically connected to a drive circuit (driver) not shown. The signal terminal 93H is electrically connected to the pad 40P of the semiconductor element 40H through a connecting member such as a bonding wire 110. As shown in FIG. The number of signal terminals 93H is not particularly limited. The signal terminal 93H may include at least a terminal for applying a drive voltage to the gate electrode of the semiconductor element 40H. The semiconductor device 20 of this embodiment has two signal terminals 93H. One of the signal terminals 93H is a terminal for a gate electrode. The gate electrode pads 40P of the two semiconductor elements 40H are electrically connected to the gate electrode signal terminal 93H. The signal terminal 93H is arranged at a position overlapping the notch 540 of the P wiring 54 in plan view. In the signal terminal 93</b>H, the joint with the bonding wire 110 faces the insulating base material 51 instead of the surface metal body 52 . The two signal terminals 93H are arranged side by side in the X direction.

The signal terminal 93H extends in the Y direction from the joint with the bonding wire 110, and protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30c. At least part of the projecting portion of the signal terminal 93</b>H extends in the same direction as the power terminal 91 . The signal terminal 93H is arranged between the two P terminals 91P in the X direction. That is, the external connection terminals 90 protruding from the side surface 30c are arranged in the order of the N terminal 91N, the P terminal 91P, the two signal terminals 93H, the P terminal 91P, and the N terminal 91N in the X direction.

The signal terminal 93L is electrically connected to the pad 40P of the semiconductor element 40L through a connecting member such as a bonding wire 110. As shown in FIG. The number of signal terminals 93L is not particularly limited. The signal terminal 93L may include at least a terminal for applying a driving voltage to the gate electrode of the semiconductor element 40L. The semiconductor device 20 of this embodiment has four signal terminals 93L. One of the signal terminals 93L is a terminal for a gate electrode. The gate electrode pads 40P of the two semiconductor elements 40L are electrically connected to the gate electrode signal terminal 93L. The signal terminal 93L is arranged at a position overlapping the notch 550 of the relay wiring 55 in plan view. In the signal terminal 93</b>L, the joint with the bonding wire 110 faces the insulating base material 51 instead of the surface metal body 52 . The four signal terminals 93L are arranged side by side in the X direction.

The signal terminal 93L extends in the Y direction from the joint with the bonding wire 110, and protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30d. At least part of the projecting portion of the signal terminal 93L extends in the same direction as the output terminal 92 . The signal terminal 93L is arranged between the two output terminals 92 in the X direction. That is, the external connection terminals 90 projecting from the side surface 30d are arranged in the order of the output terminal 92, the four signal terminals 93L, and the output terminal 92 in the X direction.

A drain electrode 40</b>D of the semiconductor element 40 is bonded to the surface metal body 52 via a bonding material 100 . A source electrode 40</b>S of the semiconductor element 40 is bonded to the conductive spacer 70 via a bonding material 101 . The conductive spacer 70 is bonded to the surface metal body 62 via the bonding material 102 . The joint portion 81 is joined to the metal bodies 52 and 62 via the joining material 103 . Among the external connection terminals 90 , the P terminal 91 P, the N terminal 91 N, and the output terminal 92 which are the main terminals are joined to the corresponding surface metal bodies 52 and 62 via the joining material 104 .

The bonding materials 100 to 104 are conductive bonding materials. For example, solder can be used as the bonding materials 100-104. An example of solder is multicomponent lead-free solder containing Cu, Ni, etc., in addition to Sn. A sintered bonding material such as sintered silver may be used instead of solder. The P terminal 91P, the N terminal 91N, and the output terminal 92 may be directly bonded to the corresponding surface metal bodies 52 and 62 without the bonding material 104 interposed therebetween. P terminal 91P, N terminal 91N, and output terminal 92 may be directly joined to surface metal bodies 52 and 62 by, for example, ultrasonic welding, friction stir welding, laser welding, or the like. If joint portion 81 is provided separately from substrates 50 and 60 , joint portion 81 may be directly bonded to surface metal bodies 52 and 62 .

As described above, in the semiconductor device 20 , the plurality of semiconductor elements 40 forming the upper and lower arm circuits 9 for one phase are sealed with the sealing body 30 . The sealing body 30 integrally seals the plurality of semiconductor elements 40 , a portion of the substrate 50 , a portion of the substrate 60 , a plurality of conductive spacers 70 , arm connection portions 80 , and portions of the external connection terminals 90 . is stopping. The sealing body 30 seals the insulating substrates 51 , 61 and the surface metal bodies 52 , 62 in the substrates 50 , 60 .

The semiconductor element 40 is arranged between the substrates 50, 60 in the Z direction. The semiconductor element 40 is sandwiched between the substrates 50 and 60 arranged opposite to each other. Thereby, the heat of the semiconductor element 40 can be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50 b of the substrate 50 is substantially flush with the one surface 30 a of the sealing body 30 . The back surface 60 b of the substrate 60 is substantially flush with the back surface 30 b of the sealing body 30 . Since the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be enhanced.

<Manufacturing method>
Next, an example of a method for manufacturing the semiconductor device 20 will be described with reference to FIG. In FIG. 10, the board 50 and the board 60 are shown facing each other so that subsequent assembly can be easily understood.

First, the semiconductor element 40, the substrates 50 and 60, the conductive spacer 70, the joint portion 81, and the lead frame 94 are respectively prepared. The lead frame 94 has external connection terminals 90 as shown in FIG. The lead frame 94 is formed by subjecting a metal plate to processing such as pressing. The external connection terminals 90 are supported by the outer frame 94b via tie bars 94a.

Next, the semiconductor element 40 , the joint portion 81 , and the external connection terminals 90 are joined (connected) to the substrate 50 . Also, a conductive spacer 70 is bonded to the semiconductor element 40 .

At this time, the lead frame 94 and the semiconductor element 40 are arranged on the substrate 50 . Also, a conductive spacer 70 is arranged on the source electrode 40S of the semiconductor element 40 . The lead frame 94 is arranged such that a portion of each of the external connection terminals 90 overlaps the substrate 50 in plan view. Specifically, the P terminal 91 P and the N terminal 91 N are arranged so as to overlap the P wiring 54 of the surface metal body 52 , and the output terminal 92 is arranged so as to overlap the relay wiring 55 . In addition, the signal terminals 93H are arranged so as to overlap the insulating base material 51 exposed through the cutout 540, and the signal terminals 93L are arranged so as to overlap the insulating base material 51 exposed through the cutout 550. FIG.

Then, the drain electrode 40</b>D of the semiconductor element 40 and the surface metal body 52 are bonded with the bonding material 100 . The bonding material 101 bonds the source electrode 40S and the conductive spacer 70 together. The joint portion 81 and the surface metal body 52 are joined by the joining material 103 . The bonding material 104 bonds the P terminal 91</b>P and the output terminal 92 to the surface metal body 52 . For example, in the case of solder, reflow can be used to join together. FIG. 10 shows this joining state.

Next, the pads 40P of the semiconductor element 40H and the signal terminals 93H are electrically connected by bonding wires 110. Next, as shown in FIG. Similarly, the bonding wire 110 electrically connects the pad 40P of the semiconductor element 40L and the signal terminal 93L.

Next, the substrate 60 is bonded (connected). The source electrode 40</b>S of the semiconductor element 40 and the surface metal body 62 are bonded via the bonding material 102 . The joint portion 81 and the surface metal body 62 are joined via the joining material 103 . The N terminal 91N and the surface metal body 62 are joined via the joining material 104 . For example, in the case of solder, reflow can be used to join together.

Next, molding of the sealing body 30 is performed by a transfer molding method. Although illustration is omitted, in the present embodiment, the sealing body 30 is molded so as to completely cover the substrates 50 and 60, and is cut after molding. The sealing body 30 is cut together with part of the backside metal bodies 53 and 63 of the substrates 50 and 60 . Thereby, the rear surfaces 50b and 60b are exposed. The back surface 50b is substantially flush with one surface 30a of the sealing body 30, and the back surface 60b is substantially flush with the back surface 30b. Note that the sealing body 30 may be molded in a state in which the back surfaces 50b and 60b are pressed against the wall surface of the cavity of the molding die so as to be in close contact with each other. In this case, the rear surfaces 50b and 60b are exposed from the sealing body 30 when the sealing body 30 is molded. This eliminates the need for cutting after molding.

Next, in the lead frame 94, unnecessary portions such as the tie bars 94a and the outer peripheral frame 94b are removed. As described above, the semiconductor device 20 can be obtained.

<Positional relationship>
14 and 15, the positional relationship among the semiconductor element 40, the circuit patterns of the surface metal bodies 52 and 62, the arm connecting portions 80, and the external connection terminals 90 connected to the circuit patterns will be described. FIG. 14 is a diagram showing the arrangement of the circuit pattern of the surface metal body 52, the semiconductor element 40, and the terminals. FIG. 15 is a diagram showing the layout of the circuit pattern of the surface metal body 62, the semiconductor element 40, and the terminals. 14 and 15 show only the external connection terminals 90 connected to the circuit pattern for convenience. In FIG. 14, the area where the semiconductor element 40 is arranged is denoted by D so that the main electrode (drain electrode 40D) connected to the surface metal body 52 is easily understood. Similarly, in FIG. 15, the arrangement region of the semiconductor element 40 is denoted by S so that the main electrode (source electrode 40S) connected to the surface metal body 62 is easily understood.

A virtual line CL1 shown in FIG. 14 is a virtual line passing through the midpoints of the two semiconductor elements 40 forming one arm. The virtual line CL1 extends in the Y direction through the midpoint (center) of the two semiconductor elements 40 in the alignment direction. Virtual line CL1 is, for example, a line passing through the midpoints of two semiconductor elements 40H. A line passing through the midpoint of the semiconductor element 40L may be used instead of the semiconductor element 40H.

As shown in FIG. 14, the arrangement of the two semiconductor elements 40H is substantially symmetrical with respect to the virtual line CL1. Similarly, the arrangement of the two semiconductor elements 40L is also substantially symmetrical with respect to the virtual line CL1. Here, substantially line symmetry can allow an error of the order of manufacturing variation. The circuit pattern of the surface metal body 52 is also substantially symmetrical with respect to the virtual line CL1. That is, each of P wiring 54 and relay wiring 55 is substantially line symmetrical with respect to imaginary line CL1.

The arrangement of the arm connecting portion 80 connected to the relay wiring 55 is also substantially symmetrical with respect to the virtual line CL1. The arrangement of the external connection terminals 90 connected to the surface metal body 52 is also substantially symmetrical with respect to the virtual line CL1. In other words, the arrangement of the two P terminals 91P is also substantially symmetrical with respect to the virtual line CL1. The arrangement of the two output terminals 92 is also substantially symmetrical with respect to the virtual line CL1.

As in FIG. 14, FIG. 15 also shows a virtual line CL1. The arrangement of the semiconductor elements 40H and 40L is the same as in FIG. As shown in FIG. 15, the circuit pattern of the surface metal body 62 is also substantially line-symmetrical with respect to the virtual line CL1. That is, each of N wiring 64 and relay wiring 65 is substantially line-symmetrical with respect to imaginary line CL1. The arrangement of the arm connecting portion 80 connected to the relay wiring 65 is also substantially line symmetrical with respect to the imaginary line CL1, as in FIG. The arrangement of the two N terminals 91N, which are the external connection terminals 90 connected to the surface metal body 62, is also substantially symmetrical with respect to the virtual line CL1.

<Circuit pattern>
Next, based on FIG. 15, the circuit pattern of the surface metal body 62 will be described in more detail. The dashed-dotted lines shown in FIG. 15 indicate the boundaries of the respective regions.

As described above, the surface metal body 62 of the substrate 60 has the N wiring 64 and the relay wiring 65 . The N wiring 64 has a base portion 640 and a pair of extension portions 641 . The pair of extending portions 641 extends from the base portion 640 toward the side surface 30c of the sealing body 30 in the Y direction. The N wiring 64 defines the outline of the surface metal body 62 . The relay wiring 65 is sandwiched between a pair of extension portions 641 . The relay wiring 65 is arranged in the notch 642 of the N wiring 64 .

As shown in FIG. 15, the relay wiring 65 has an end portion 650 as one end in the Y direction. The end portion 650 is the end portion on the base portion 640 side in the Y direction. On the other hand, the base portion 640 of the N wiring 64 has a side 640 a facing the end portion 650 . The opposing side 640 a is a portion between the pair of extension portions 641 in the base portion 640 . Also, the base 640 has an arrangement region 640b for the semiconductor element 40L. The placement region 640b is defined by the outline of the semiconductor element 40L, as indicated by the two-dot chain line in FIG. The arrangement region 640b includes a region that overlaps the semiconductor elements 40L in plan view, and also includes regions between the semiconductor elements 40L when a plurality of semiconductor elements 40L are included. The region between elements is a region where the semiconductor elements 40L face each other in the direction in which the semiconductor elements 40L are arranged.

Here, the X-direction lengths L1, L2, and L3 are defined as follows. The length L1 is the length of the end portion 650 of the relay wiring 65 as shown in FIG. Length L2 is the length of opposing side 640a of base 640 . Length L3 is the length of placement region 640b at base 640 . In this embodiment, the relationship of L1<L2<L3 is satisfied.

The relay wiring 65 of this embodiment has a reduced width portion 651a. The reduced width portion 651 a includes an end portion 650 . The reduced width portion 651a is a portion within a predetermined range from the end portion 650 in the Y direction. The length in the X direction, that is, the width of the narrowed portion 651 a is the smallest at the end portion 650 . In the reduced-width portion 651a, the width W1 at any first position is less than or equal to the width W2 at a second position farther from the end portion 650 than the first position.

The width of the reduced-width portion 651a may be reduced stepwise by a predetermined length in the Y direction, for example. In other words, the X-direction end of the reduced-width portion 651a may change stepwise. In this embodiment, the length in the X direction of the narrowed width portion 651a is shorter as it is closer to the base portion 640 . In other words, the width of the narrowed portion 651 a continuously decreases toward the base portion 640 . The arm connecting portion 80 is arranged at the reduced width portion 651a.

The relay wiring 65 may have only the narrowed width portion 651 a including the end portion 650 . In this case, the semiconductor element 40H is also arranged in the reduced width portion 651a. The relay wiring 65 of this embodiment has a constant width portion 651b. The constant-width portion 651b is continuous with the reduced-width portion 651a and has a constant width over a predetermined range in the Y direction. The semiconductor element 40H is arranged in the constant width portion 651b.

The relay wiring 65 of this embodiment further has a reduced width portion 651c. The narrowed portion 651 c includes an end portion 652 opposite the end portion 650 . The reduced-width portion 651c is opposite to the reduced-width portion 651a and continues to the constant-width portion 651b. The width of the narrowed portion 651c is the smallest at the end 652 . In the reduced-width portion 651c, the width at any first position is less than or equal to the width at a second position farther from the end portion 652 than the first position. In this embodiment, the width of the reduced-width portion 651 c is continuously reduced toward the end portion 652 . In the relay wiring 65, the reduced-width portions 651a and 651c become narrower with increasing distance from the constant-width portion 651b.

In this embodiment, the distance between the N wiring 64 and the relay wiring 65 is substantially constant over the entire facing area. The extended portion 641 of the N wiring 64 is patterned so that the distance from the relay wiring 65 is substantially constant. Each extension portion 641 has a widened portion 641a, a constant width portion 641b, and a widened portion 641c.

The widened portion 641a continues to the base portion 640 and is a portion within a predetermined range in the Y direction from the boundary with the base portion 640 . The length of the widened portion 641 a in the X direction, that is, the width, is maximum at the boundary with the base portion 640 . In the widened portion 641a, the width at an arbitrary first position is greater than or equal to the width at a second position that is farther from the base 640 than the first position. The width of the widened portion 641a of this embodiment is continuously expanded toward the base portion 640. As shown in FIG. The constant width portion 641b is a portion that continues to the widened portion 641a and has a constant width over a predetermined range in the Y direction. The constant width portion 641 b faces the constant width portion 651 b of the relay wiring 65 .

The widened portion 641c is opposite to the widened portion 641a and continues to the constant width portion 641b. The widened portion 641a extends to a position closer to the side surface 30c than the narrowed portion 651c. The widened portion 641 c includes a distal end portion 641 d of the extended portion 641 . The width of the widened portion 641c is maximum at the tip portion 641d. In the widened portion 641c, the width at an arbitrary first position is greater than or equal to the width at a second position that is farther from the distal end portion 641d than the first position. In this embodiment, the width of the widened portion 641c is continuously enlarged toward the distal end portion 641d at the portion facing the narrowed portion 651c. In the widened portion 641c, the portion closer to the tip portion 641d than the opposing portion has a constant width. In the N wiring 64, the width of a part of the widened portion 641c and the widened portion 641a increases with increasing distance from the constant width portion 641b.

<Current path>
Next, current paths will be described with reference to FIGS. 16 to 20. FIG. FIG. 16 is a diagram showing a PN current loop of a reference example. In the reference example, the code of each element is the code of the related element of the semiconductor device 20 with r added to the end. The configuration of the reference example is substantially the same as that of the semiconductor device 20 except that the number of signal terminals 93Lr and the patterns of N wiring 64r and relay wiring 65r are different. FIG. 17 is a diagram showing a PN current loop in the semiconductor device 20 of this embodiment. FIG. 18 is a diagram showing a PN current loop in a side view of the semiconductor device 20 viewed from the X direction. A PN current loop refers to a loop shape of a current path from the P terminal 91P to the N terminal 91N.

In considering the inductance, the PN current loop of P terminal 91P→P wiring 54→semiconductor element 40H→relay wiring 65→arm connecting portion 80→relay wiring 55→semiconductor element 40L→N wiring 64→N terminal 91N is considered. . For this reason, the continuous solid line from the P terminal 91P to the N terminal 91N is shown so that the PN current loop can be easily understood. Actually, the semiconductor elements 40H and 40L are controlled so as not to be turned on at the same time. For convenience, only one of the semiconductor elements 40H and one of the semiconductor elements 40L is shown, but the same applies to the other semiconductor elements 40H and 40L.

19 and 20 show the results of the electromagnetic field simulation. FIG. 19 shows the current density of the reference example shown in FIG. FIG. 20 shows the current density for the configuration of this embodiment shown in FIG. The electromagnetic field simulation conditions were common to each other, except that the circuit pattern of the surface metal body 62 was different. In FIGS. 19 and 20, the lower the current density, the coarser (lighter color), and the higher the current density, the denser (darker color).

As shown in FIG. 16, in the semiconductor device 20r of the reference example, the relay wiring 65r has a substantially rectangular planar shape. The length of the end portion 650r of the relay wiring 65r is approximately equal to the length of the arrangement region 640br of the semiconductor element 40Lr in the base portion 640r. The length of the opposing side 640ar in the base 640r is longer than the placement region 640br. Therefore, as indicated by solid arrows in FIG. 16, a current enters from one side 400r of the substantially rectangular planar semiconductor element 40Lr and exits from another side 401r. The side 400r is a side facing the relay wiring 65r. The side 401r is the side opposite to the side where the two semiconductor elements 40Lr face each other. Thus, the current flows outward in the X direction from the semiconductor element 40Lr, so the PN current loop is large. Also from the simulation results shown in FIG. 19, it is clear that the current flows outward in the X direction from the semiconductor element 40Lr through the base 640r.

On the other hand, in the semiconductor device 20 of the present embodiment, as described above, the N wiring 64 and the relay wiring 65 are patterned and satisfy the predetermined positional relationship with the semiconductor element 40L. Due to this positional relationship, as shown in FIG. 17, the N wiring 64 (extended portion 641) also exists above one side 400 of the semiconductor element 40L in plan view. A side 400 is a side facing the relay wiring 65 . Therefore, current enters from the side 400 of the semiconductor element 40L and current exits from the same side 400. FIG. Of the current flowing from the semiconductor element 40L to the N terminal 91N, the Y-direction component increases particularly in the vicinity of the semiconductor element 40L. Also from the simulation results shown in FIG. 20, it is clear that the current flows from the semiconductor element 40L with a Y-direction component.

Thus, the current flowing through N wiring 64 approaches relay wiring 65, and the current path by N wiring 64, ie, the current path between semiconductor element 40L and N terminal 91N, is shortened. Therefore, the PN current loop is smaller than that of the reference example. As shown in Figure 18, the PN current loop is also small in the Z direction. The P wiring 54 and the N wiring 64 face each other in the Z direction. Also, the relay wiring 55 and the N wiring 64 face each other in the Z direction.

<Summary of the first embodiment>
If the inductance of the main circuit wiring is large, the surge voltage will be large. If the thickness of the semiconductor element is increased in order to secure the withstand voltage, the steady loss increases. In order to reduce the steady-state loss, it is necessary to increase the element area. Also, by suppressing the switching speed, the surge voltage can be reduced. In this case, the output to the motor generator becomes small. As described above, when the inductance is large, the size of the semiconductor element becomes large, or the output becomes small.

When members through which currents flow in opposite directions are arranged to face each other, the inductance can be reduced due to the effect of canceling the magnetic flux generated by the currents. If the PN current loop of the main circuit wiring is smaller, the members through which the currents flow in opposite directions are brought closer to each other, and the effect of canceling the magnetic flux is enhanced, so that the inductance can be reduced.

In this embodiment, the semiconductor elements 40H and 40L are arranged side by side in the Y direction, and the arm connecting portion 80 is arranged between the semiconductor elements 40H and 40L. Among the main terminals, the power supply terminals 91 (91P, 91N) are pulled out in the same direction. In the Y direction, the P wiring 54 is arranged on the power terminal 91 side, and the relay wiring 55 is arranged on the opposite side. In the Y direction, the relay wiring 65 is arranged on the power terminal 91 side, and the base 640 of the N wiring 64 is arranged on the opposite side. The extended portion 641 of the N wiring 64 is extended toward the power terminal 91 so as to sandwich the relay wiring 65 .

Such a configuration reduces the PN current loop. Thereby, the inductance of the main circuit wiring can be reduced. For example, parallel arrangement of the P terminal 91P and the N terminal 91N can reduce the inductance. The relay wiring 65 and the N wiring 64 are also arranged (arranged in parallel) with a predetermined interval. Thereby, inductance can be reduced. Further, the extended portion 641 of the N wiring 64 faces the P wiring 54 . Thereby, inductance can be reduced.

In this embodiment, surface metallurgy 52 of substrate 50 and surface metallurgy 62 of substrate 60 provide wiring functions for semiconductor device 40 . The surface metal bodies 52 , 62 are sealed with a sealing body 30 . Since it is not necessary to secure a creepage distance as in the conventional case, the N wiring 64 and the relay wiring 65 can be arranged close to each other. As a result, the effect of canceling the magnetic flux is enhanced, and the inductance can be further reduced.

Further, as shown in FIG. 15, the length L1 of the end portion 650 of the relay wiring 65, the length L2 of the opposing side 640a of the base portion 640, and the length L3 of the arrangement region 640b of the semiconductor element 40L in the base portion 640 are L1 It satisfies the relationship <L2<L3. By satisfying this dimensional relationship, current enters from one side 400 of the semiconductor element 40L and exits from the same side 400, as described above. Of the current flowing from the semiconductor element 40L to the N terminal 91N, the Y-direction component increases particularly in the vicinity of the semiconductor element 40L. This shortens the current path through the N wiring 64, that is, the current path between the semiconductor element 40L and the N terminal 91N, and reduces the PN current loop. Therefore, the inductance of the main circuit wiring can be further reduced.

Also, the higher the frequency of the current, the more the current concentrates on the opposing side between the extended portion 641 of the N wiring 64 and the relay wiring 65 due to the skin effect. This allows the PN current loop to be made even smaller and thus the inductance to be made even smaller.

In this embodiment, as shown in FIG. 15, the relay wiring 65 has a reduced width portion 651a. As a result, the width of the portion of the extended portion 641 facing the reduced width portion 651a can be increased. Therefore, heat generation due to energization can be suppressed without changing the size of the surface metal body 62 and thus the substrate 60 . That is, heat generation can be suppressed while reducing inductance.

In particular, in this embodiment, the length of the reduced width portion 651a in the X direction is shorter toward the base portion 640. As shown in FIG. In other words, the width of the narrowed portion 651 a continuously decreases toward the base portion 640 . A reduced-width portion 651a of the relay wiring 65 has a tapered shape. This makes it easy to keep the distance between the relay wiring 65 and the extended portion 641 constant. That is, the extended portion 641 can be brought closer to the relay wiring 65 to reduce the PN current loop. In addition, the width of the extended portion 641 can be increased to suppress heat generation.

In this embodiment, the relay wiring 65 has a constant width portion 651b. The semiconductor element 40H is arranged in the constant width portion 651b. The relay wiring 65 having the reduced-width portion 651a and the constant-width portion 651b has a shape identical to or similar to that of a baseball home plate in plan view. According to this, the width of the extended portion 641 can be increased compared to the configuration in which the semiconductor element 40H is arranged in the reduced width portion 651a. Therefore, heat generation due to energization can be suppressed without changing the size of the surface metal body 62 and thus the substrate 60 . That is, heat generation can be suppressed while reducing inductance.

In this embodiment, the semiconductor device 20 includes two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are arranged side by side in the X direction. Similarly, two semiconductor elements 40L are arranged side by side in the X direction. In this manner, the semiconductor elements 40 forming one arm are arranged side by side in a direction (X direction) perpendicular to the direction in which the semiconductor elements 40H and 40L are arranged (Y direction). A pair of extension portions 641 sandwich the relay wiring 65 in the X direction. Thereby, current imbalance can be suppressed.

The semiconductor device 20 may include one N terminal 91N whose tip is branched into two so as to be individually connected to the pair of extended portions 641 . In this embodiment, the semiconductor device 20 has two N terminals 91N, and the N terminals 91N are individually connected to the pair of extended portions 641 . This makes it easy to arrange another external connection terminal 90 between the two N terminals 91N. Since it is not necessary to avoid the external connection terminals 90 arranged between them, the physical size can be reduced.

The semiconductor device 20 may have only one P terminal 91P. In this embodiment, the semiconductor device 20 has two P terminals 91P. In the X direction, the N terminal 91N, the P terminal 91P, the signal terminal 93H, the P terminal 91P, and the N terminal 91N are arranged in this order. A P terminal 91P and an N terminal 91N are arranged side by side at both ends in the X direction. Therefore, it is easy to reduce the PN current loop. In addition, since the external connection terminals 90 are arranged with regularity in the X direction, line symmetry is ensured for the semiconductor element 40, the circuit patterns of the surface metal bodies 52 and 62, and the external connection terminals 90, as described above. easier to do. Thereby, current imbalance can be suppressed.

In this embodiment, the P terminal 91P and the N terminal 91N protrude from the side surface 30c of the sealing body 30, and the output terminal 92 protrudes from the side surface 30d. Thus, the P terminal 91P and the N terminal 91N connected to the smoothing capacitor 5 are led out in the same direction, and the output terminal 92 is led out in the opposite direction. Thereby, the connectivity with the smoothing capacitor 5 and the connectivity with the motor generator 3 can be improved. Also, the parallel arrangement of the P terminal 91P and the N terminal 91N can reduce the inductance. Such a terminal arrangement makes it easy to reduce the PN current loop.

<Modification>
As an example in which a plurality of semiconductor elements 40H and 40L are provided, an example in which two semiconductor elements 40H and 40L are provided has been shown, but the present invention is not limited to this. You may provide three or more. For example, three semiconductor elements 40H may be arranged side by side in the X direction, and three semiconductor elements 40L may be arranged side by side in the X direction. The circuit pattern of the surface metal body 62 and the arrangement of the semiconductor elements 40 are not limited to the above examples. For example, FIGS. 21 and 22 may be used. 21 and 22, for the sake of convenience, the sealing body 30 on the back surface 30b side of the insulating base material 51 is omitted. Also, the insulating base material 61 and the back surface metal body 63 of the substrate 60 are omitted in the illustration. As in FIG. 17, the PN current loop is indicated by solid arrows. 21 and 22, the semiconductor device 20 has two signal terminals 93L.

In FIG. 21 , the semiconductor device 20 has two arm connecting portions 80 . The relay wiring 65 has a substantially rectangular planar shape. The two arm connecting portions 80 are arranged side by side in the X direction near the end portion 650 . The distance between the two semiconductor elements 40L is larger than in the example described above (see FIG. 17). The length of the placement region 640b of the semiconductor element 40L is longer than in the above example. This satisfies the relationship of L1<L2<L3. Therefore, current enters from the side 400 of the semiconductor element 40L and current exits from the same side 400. FIG. Even with such a configuration, the current path by the N wiring 64 is shortened, and the PN current loop can be reduced. However, the configuration shown in FIG. 17 can increase the width of the N wiring 64, particularly the width of the extended portion 641. In FIG. Further, in the case of the configuration shown in FIG. 17, only one arm connecting portion 80 is required.

In FIG. 22, the semiconductor device 20 includes only one each of the semiconductor elements 40H and 40L. In this example, the placement region 640b matches the outline of the semiconductor element 40L. The length of one semiconductor element 40H, 40L in the X direction is longer than the above example (see FIG. 17). This satisfies the relationship of L1<L2<L3. Therefore, current enters from the side 400 of the semiconductor element 40L and current exits from the same side 400. FIG. Even with such a configuration, the current path by the N wiring 64 is shortened, and the PN current loop can be reduced.

The arrangement of the external connection terminals 90 is not limited to the above example. For example, the P terminal 91P may be arranged on the outside in the X direction, and the N terminal 91N may be arranged on the inside. In this case, as shown in FIGS. 23 and 24, the semiconductor element 40 and the circuit pattern are also reversed. FIG. 23 shows the substrate 50. As shown in FIG. FIG. 24 shows the substrate 60. As shown in FIG.

As shown in FIG. 23, the circuit pattern of the surface metal body 52 of the substrate 50 is the same as the circuit pattern of the surface metal body 62 of the substrate 60 shown in FIG. The P wiring 54 has the same pattern as the N wiring 64 shown in FIG. A semiconductor element 40</b>H is arranged on the N wiring 64 . The relay wiring 55 has the same pattern as the relay wiring 65 shown in FIG. Semiconductor element 40</b>L and arm connecting portion 80 are arranged on relay wiring 55 .

As shown in FIG. 24, the circuit pattern of the surface metal body 62 of the substrate 60 is the same as the circuit pattern of the surface metal body 52 of the substrate 50 shown in FIG. The N wiring 64 has the same pattern as the P wiring 54 shown in FIG. A semiconductor element 40L is arranged on the N wiring 64 . The relay wiring 65 has the same pattern as the relay wiring 55 shown in FIG. Semiconductor element 40</b>H and arm connecting portion 80 are arranged on relay wiring 65 .

In the case of the configurations shown in FIGS. 23 and 24, the above first and second relationships are reversed. The semiconductor element 40L is the first element, and the semiconductor element 40H is the second element. The source electrode 40S is the first main electrode, and the drain electrode 40D is the second main electrode. The substrate 60 is the first substrate, and the substrate 50 is the second substrate. The insulating base material 61 is the first insulating base material, the front metal body 62 is the first front metal body, and the back metal body 63 is the first back metal body. The insulating base material 51 is the second insulating base material, the surface metal body 52 is the second surface metal body, and the back metal body 53 is the second back metal body.

(Second embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to suppress the transient current imbalance at the time of switching, the surface metal body in which a plurality of semiconductor elements are connected in parallel may have a predetermined structure as described in this embodiment.

<Semiconductor device>
First, based on FIG. 25, the semiconductor device 20 of this embodiment will be described. FIG. 25 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. FIG. 25 corresponds to FIG.

The semiconductor device 20 of this embodiment has the same configuration as the configuration described in the previous embodiment (see FIGS. 2 to 15). The semiconductor device 20 constitutes the upper and lower arm circuits 9 for one phase. As shown in FIG. 25, a semiconductor device 20 includes a plurality of semiconductor elements 40 including two semiconductor elements 40H that are upper arm elements, substrates 50 and 60 arranged to sandwich the semiconductor elements 40 in the Z direction, A sealing body 30 is provided. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the first main electrode of the semiconductor element 40 on the high potential side. The surface metal body 62 of the substrate 60 is connected to the source electrode 40S, which is the second main electrode of the semiconductor element 40 on the low potential side. Although not shown, the semiconductor device 20 includes two semiconductor elements 40L that are lower arm elements.

The surface metal body 62 is substantially line-symmetrical with respect to the imaginary line CL1, as in the preceding embodiment. As shown in FIG. 25, in this embodiment, the relay wiring 65 of the surface metal body 62 has a slit 653 . As will be described later, the N wiring 64 has slits 643 .

<Effect of suppressing transient current imbalance>
Next, the effect of suppressing transient current imbalance during switching will be described with reference to FIGS. 26 and 27. FIG. FIG. 26 is an equivalent circuit diagram of two semiconductor elements 40 (MOSFETs 11) forming one arm. FIG. 27 is an image diagram (potential diagram) showing the potential in an easy-to-understand manner.

26 and 27, one of the MOSFETs 11 connected in parallel is indicated as MOSFET1, and the other one is indicated as MOSFET2. The inductance of the wiring on the drain electrode side (hereinafter referred to as drain wiring) is indicated by Ld, and the inductance of the wiring on the source electrode side (hereinafter referred to as source wiring) is indicated by Ls. The gate potential is indicated by Vg, the potential of the source electrode of MOSFET1 is indicated by Vks1, the potential of the source electrode of MOSFET2 is indicated by Vks1, and the common source potential is indicated by Vs. A midpoint potential between the potential Vks1 and the potential Vks2 is indicated as Vm. The midpoint potential Vm is constant.
Vm=(Vks1+Vks2)/2.

Also, the gate voltage of MOSFET1 is indicated as Vgs1, and the gate voltage of MOSFET2 is indicated as Vgs2. A current flowing through the MOSFET 1 when it is turned on is denoted by I1, and a voltage generated across the inductance Ls when the current I1 flows is denoted by ΔVs1. Similarly, the current flowing through the MOSFET 2 upon turn-on is denoted by I2, and the voltage generated across the inductance Ls when the current I2 flows is denoted by ΔVs2.
ΔVs1=Ls×dI1/dt.
ΔVs2=Ls×dI2/dt.

Assume that a current I2 (I2>I1) larger than the current I1 flows as shown in FIG. 26 due to variations in the characteristics of the MOSFET 11 . At this time, the voltage ΔVs generated in the inductance Ls is ΔVs1<ΔVs2. That is, as shown in FIG. 27, the source electrode potential Vks2 rises and the potential Vks1 falls with respect to the midpoint potential Vm. Therefore, gate voltage Vgs1>gate voltage Vgs2. Since the gate voltage Vgs2 is reduced, the current I2 is reduced. In this way, the inductance Ls of the source wiring has a function of suppressing transient current imbalance during switching caused by characteristic variations of the semiconductor element 40 (MOSFET 11) connected in parallel.

However, when the inductance Ls of the source wiring is small, the function of suppressing the transient current imbalance described above is impaired. As a result, the switching loss becomes biased, and it becomes necessary to take a margin in the thermal design.

<Circuit pattern of substrate>
Next, the circuit pattern of the surface metal body 62 in the semiconductor device 20 of this embodiment will be described with reference to FIG. FIG. 28 corresponds to FIG. In FIG. 28, as in FIG. 15, the source electrode 40S is denoted by S in order to clarify the connected main electrode.

The N wiring 64 and the relay wiring 65 are source wirings to which the source electrode 40S of the semiconductor element 40 is connected. The N wiring 64 differs from the pattern of the preceding embodiment in that it has a slit 643 . Similarly, the relay wiring 65 differs from the pattern of the preceding embodiment by having a slit 653 . Except for having slits 643 and 653, the configuration is the same as that described in the preceding embodiment.

The slit 643 penetrates the N wiring 64 in its thickness direction (Z direction). The slit 643 is provided in the base portion 640 at a position overlapping the opposed regions of the two semiconductor elements 40L. The facing region is a region where the semiconductor elements 40L are opposed to each other in the direction in which the semiconductor elements 40L are arranged. In other words, the slit 643 is provided between the semiconductor elements 40L, which are the lower arm elements, in a plan view in the Z direction. The slit 643 is provided in the base 640 between the electrical connections with the semiconductor element 40L. The slit 643 extends from between the semiconductor elements 40L in the Y direction, which is the direction in which the semiconductor elements 40H and 40L are arranged. The slit 643 is open on the opposing side 640a of the base 640 . The slit 643 is provided substantially in the center of the N wiring 64 in the X direction.

In this manner, the slit 643 extends from the source electrode 40S of the semiconductor element 40L to the side where the N terminal 91N, which is the main terminal, is arranged in the Y direction, that is, the current flowing side. The slit 643 does not open at the end 640 c of the base 640 . The slit 643 is provided up to the vicinity of the lower end of the opposing region of the semiconductor element 40L. The slit 643 divides the N wiring 64 into a region to which one of the semiconductor elements 40L is connected and a region to which the other one is connected. The slit 643 separates the current path of the source electrode 40S of the semiconductor element 40L, that is, the source current path.

The slit 653 penetrates the relay wiring 65 in its thickness direction (Z direction). The slit 653 is provided in the relay wiring 65 at a position overlapping the opposing regions of the two semiconductor elements 40H. That is, the slit 653 is provided between the semiconductor elements 40H in plan view. The slit 653 is provided between the electrical connections with the semiconductor element 40H in the relay wiring 65 . The slit 653 extends in the Y direction from between the semiconductor elements 40H. The slit 653 opens at the end 652 . The slit 653 extends from the end portion 652 to the vicinity of the arm connecting portion 80 across the space between the semiconductor elements 40H (opposing region). The slit 653 is provided at a substantially central position of the relay wiring 65 in the X direction.

Thus, the slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the arm connecting portion 80 in the Y direction. The slit 653 extends from the source electrode 40S of the semiconductor element 40H to the current flowing side. Slit 653 does not open at end 650 . The slit 643 is provided up to this side of the arm connecting portion 80 . The slit 653 divides the relay wiring 65 into a region to which one of the semiconductor elements 40H is connected and a region to which the other one is connected. The slit 653 separates the current path of the source electrode 40S of the semiconductor element 40H, that is, the source current path.

<Summary of Second Embodiment>
FIG. 29 shows the source current paths. A solid arrow indicates a source current path on the semiconductor element 40H side, and a broken arrow indicates a source current path on the semiconductor element 40L side. As described above, in this embodiment, the slits 643 and 653 are provided in the surface metal body 62 to which the source electrode 40S, which is the main electrode on the low potential side, is connected.

The slit 643 is provided between the adjacent semiconductor elements 40L in the N wiring 64 to which the semiconductor elements 40L are connected in parallel. The slit 643 partitions the N wiring 64 and separates the source current path of each semiconductor element 40L. As a result, it is possible to prevent the current (source current) from the source electrode 40S of the semiconductor element 40L from merging in the vicinity of the source electrode 40S. That is, the confluence point of the source currents moves away from the source electrode 40S in plan view. Therefore, in the parallel circuit of the two semiconductor elements 40L (MOSFETs 11), the inductance Ls of the source wiring can be increased compared to the configuration without the slit 643. FIG. Since the inductance Ls is large, even if the characteristics of the two semiconductor elements 40L vary (deviation), transient current imbalance during switching can be suppressed. By providing the slit 643, the transient current imbalance can be suppressed while maintaining the high integration of the semiconductor element 40L.

Similarly, the relay wiring 65 has a slit 653 . The slit 653 is provided between the two semiconductor elements 40H. The slit 653 partitions the relay wiring 65 and separates the source current path of each semiconductor element 40H. As a result, the current (source current) emitted from the source electrode 40S of the semiconductor element 40H can be prevented from merging in the vicinity of the source electrode 40S. That is, the confluence point of the source currents moves away from the source electrode 40S in plan view. Therefore, in the parallel circuit of the two semiconductor elements 40H, the inductance Ls of the source wiring can be increased compared to the configuration without the slit 653. FIG. Since the inductance Ls is large, even if there is variation (deviation) in the characteristics of the two semiconductor elements 40H, transient current imbalance during switching can be suppressed. By providing the slit 653, the transient current imbalance can be suppressed while maintaining the high integration of the semiconductor element 40H.

In this embodiment, the slit 643 extends from between the adjacent semiconductor elements 40L toward the N terminal 91N in the Y direction. The slit 643 extends from the source electrode 40S of the semiconductor element 40L to the current flowing side. Thereby, the source current path of each semiconductor element 40L can be separated by a longer distance. Therefore, in the parallel circuit of the semiconductor element 40L, the inductance Ls of the source wiring can be increased. That is, the effect of suppressing transient current imbalance can be enhanced.

Similarly, a slit 653 extends from between the adjacent semiconductor elements 40H toward the arm connecting portion 80 in the Y direction. The slit 653 extends from the source electrode 40S of the semiconductor element 40H to the current flowing side. Thereby, the source current path of each semiconductor element 40L can be separated by a longer distance. Therefore, in the parallel circuit of the semiconductor element 40H, the inductance Ls of the source wiring can be increased. That is, the effect of suppressing transient current imbalance can be enhanced.

30 is a cross-sectional view taken along line XXX-XXX in FIG. 29. FIG. In the present embodiment, the joint portion 81 , the joint member 103 connecting the joint portion 81 and the relay wiring 55 , and the joint member 103 connecting the joint portion 81 and the relay wiring 65 are arms for electrically connecting the relay wirings 55 and 65 . A connecting portion 80 is configured. The joint portion 81 is a separate member from the substrates 50 and 60 . The arm connecting portion 80 electrically connects the relay wiring 65 connected to the source electrode 40S of the semiconductor element 40H and the relay wiring 55 connected to the drain electrode 40D of the semiconductor element 40L.

<Modification>
In the above example, the plurality of semiconductor elements 40 includes two each of the semiconductor elements 40H and 40L, but the present invention is not limited to this. A configuration including two of one of the semiconductor elements 40H and 40L and one other of the semiconductor elements 40H and 40L may be employed. In this case, of the two wirings (64, 65) of the surface metal body 62, a slit may be provided in the wiring that constitutes one arm in which a plurality of semiconductor elements 40 are connected in parallel. For example, in a configuration including two semiconductor elements 40H and one semiconductor element 40L, the slit 643 may not be provided in the N wiring 64, and the slit 653 may be provided in the relay wiring 65 to which the semiconductor element 40H is connected. Thus, the plurality of semiconductor elements 40 may include two arm elements of at least one of the semiconductor elements 40H and 40L.

The number of semiconductor elements 40 connected in parallel is not limited to two. Three or more semiconductor elements 40 may be connected in parallel to form one arm. For example, in the case of a configuration including three semiconductor elements 40H, slits 653 may be provided between the semiconductor elements 40H adjacent to each other in plan view for the three semiconductor elements 40H arranged side by side in the X direction. The plurality of semiconductor elements 40 may include a plurality of arm elements of at least one of the semiconductor elements 40H and 40L. A plurality of both arm elements may be included, that is, a plurality of semiconductor elements 40H and a plurality of semiconductor elements 40L may be included.

The arrangement of the N terminal 91N is not limited to the above example. For example, the P terminal 91P may protrude from the side surface 30c of the sealing body 30, and the N terminal 91N may protrude from the side surface 30d. In this case, the pattern of the N wiring 64 has a shape similar to that of the P wiring 54 and the relay wiring 55, for example. That is, the extended portion 641 extends from the base portion 640 toward the side surface 30 d of the sealing body 30 . Also in this configuration, the slits 643 may be provided at least between the semiconductor elements 40L. Further, by configuring the slit 643 to extend from the facing region of the semiconductor element 40L to the outside of the facing region and toward the N terminal 91N side, the inductance Ls can be further increased.

Although the number of slits 643 and 653 provided between the semiconductor elements 40 is one, it is not limited to this. At least one of the slits 643 and 653 may be plural.

Although an example in which the slits 643 and 653 are opened at one of the ends of the surface metal body 62 has been shown, the present invention is not limited to this. For example, in the example shown in FIGS. 31 and 32, slit 643 extends in the Y direction from opposing side 640a of base 640 to end 640c. The slit 643 divides the base 640 and thus the N wiring 64 into two. The slit 643 crosses the opposing region of the semiconductor element 40L. One of the semiconductor elements 40L is arranged on one of the divided N wirings 64, and another one of the semiconductor elements 40L is arranged on the other one of the N wirings 64. FIG. Similarly, the slit 653 extends in the Y direction from the end 652 to the end 650 of the relay wiring 65 . The slit 653 divides the relay wiring 65 into two. One of the semiconductor elements 40H is arranged on one of the divided relay wirings 65, and another one of the semiconductor elements 40H is arranged on the other one of the relay wirings 65. FIG.

The slits 643 and 653 are connected to each other to form one slit extending in the Y direction. The surface metal body 62 is substantially line-symmetrical with respect to the virtual line CL1. FIG. 33 shows the source current paths. A solid line arrow indicates the source current path of the semiconductor element 40H, and a broken line arrow indicates the source current path of the semiconductor element 40L. As described above, the slit 643 divides the N wiring 64 into two. As a result, one source current of the semiconductor element 40L and another source current do not merge on the substrate 60 . Since the confluence point of the source currents is farther away, the inductance Ls of the source wiring can be further increased.

Similarly, a slit 653 divides the relay wiring 65 into two. As a result, the source current of the semiconductor element 40</b>H and the other source current do not join on the substrate 60 . Since the confluence point of the source currents is farther away, the inductance Ls of the source wiring can be further increased. As described above, the effect of suppressing transient current imbalance can be enhanced. 31, 32, and 33 are diagrams showing modifications. FIG. 31 corresponds to FIG. FIG. 32 corresponds to FIG. FIG. 33 corresponds to FIG.

In the examples shown in FIGS. 31 to 33 , the arm connecting portions 80 are divided into the same number as the relay wirings 65 in accordance with the division of the relay wirings 65 . The arm connecting portion 80 is individually connected to the relay wiring 65 . According to this, since the source currents do not merge at the arm connecting portion 80 as well, the inductance Ls can be increased.

In the configuration of the modified example described above, a slit may be further provided in the surface metal body 52 of the substrate 50 . As shown in FIGS. 34 and 35 , the relay wiring 55 of the surface metal body 52 has slits 553 . The slit 553 opens at the end 551 a of the relay wiring 55 . The end portion 551a faces the P wiring 54 in the Y direction. The slit 553 extends in the Y direction, traverses the arm connecting portion 80 divided into two, and reaches the opposing region (between) the semiconductor elements 40L. The slit 553 is provided up to the vicinity of the lower end of the opposing region of the semiconductor element 40L.

When such a configuration is adopted, as shown in FIG. 35, a first current path formed by one set of semiconductor elements 40H and 40L and a second current path formed by another set of semiconductor elements 40H and 40L are formed by semiconductor devices. Within the device 20 there is almost complete isolation. The junction of the currents is provided outside the N terminal 91N. Therefore, the inductance Ls of the source wiring can be further increased. 34 and 35 are diagrams showing modifications. FIG. 34 corresponds to FIG. FIG. 35 corresponds to FIG. In addition, the semiconductor device 20 may include an N bus bar that connects the plurality of N terminals 91N. In this case, the currents merge at the N busbar. An N bus bar connecting N terminal 91N may be provided, for example, on smoothing capacitor 5 side.

Although an example in which the arm connection portion 80 is configured by the joint portion 81 and the joint material 103 arranged on both end sides of the joint portion 81 has been shown, the present invention is not limited to this. In the example shown in FIG. 36, the joint portion 81 is provided integrally with the substrate 60 . The joint portion 81 is provided as a protrusion extending in the Z direction from the relay wiring 65 . The conductive spacer 70 is also provided integrally with the surface metal body 62 as a protrusion, similar to the joint portion 81 .

The surface metal body 62 having protrusions may be formed by, for example, patterning a multi-gauge strip metal plate by press working and attaching it to the insulating base material 61 . The surface metal body 62 having protrusions may be formed by etching thick Cu. It may be formed by directly bonding a metal body, which is a separate member from the substrate 60 , to the surface metal body 62 . In the configuration shown in FIG. 36 , joint portion 81 , which is a protrusion of relay wiring 65 , and bonding material 103 interposed between the tip of joint portion 81 and relay wiring 55 constitute arm connecting portion 80 . FIG. 36 is a diagram corresponding to FIG.

The example shown in FIG. 37 has a configuration in which the joint portion 81 is eliminated. A bonding material 103 electrically connects the relay wirings 55 and 65 . The joint material 103 constitutes the arm connecting portion 80 . In FIG. 37, the conductive spacer 70 is also eliminated, and the source electrode 40S of the semiconductor element 40 is connected to the surface metal body 62 via the bonding material 101. FIG. Although illustration is omitted, the arm connecting portion 80 may be configured to include only the joint portion 81 without the bonding material 103 . In this case, the joint portion 81 is directly joined to the relay wirings 55 and 65 .

The circuit patterns of the substrates 50 and 60 are not limited to the examples described above. A substrate 60 shown in FIG. 38 shows an example in which slits 643 and 653 are applied to the circuit pattern shown in FIG. In the example shown in FIG. 38, slits 643 are provided between adjacent semiconductor elements 40L. The slit 643 extends from between the semiconductor elements 40L in the Y direction toward the N terminal 91N side, that is, the side through which the source current flows. The slit 653 is provided between adjacent semiconductor elements 40H. The slit 653 extends from between the semiconductor elements 40H toward the arm connecting portion 80 in the Y direction.

In this embodiment, the arrangement of the external connection terminals 90 is not limited to the illustrated example. The P terminal 91P may be connected to the P wiring 54 at both ends in the X direction, for example. N terminal 91N may be connected to N wiring 64 at both ends in the X direction, for example. In this case, the N terminal 91N may be connected to the extended portion 641 . The extended portion 641 may be removed from the N wiring 64 and connected to the base portion 640 . The output terminal 92 may be connected to the relay wiring 55 at both ends in the X direction, for example.

The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment and its modifications.

(Third embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to effectively release the heat of the semiconductor element, the thickness above and below the semiconductor element may satisfy a predetermined relationship, as described in this embodiment.

<Warpage at high temperature>
As a result of intensive studies, the semiconductor device 20 as shown in FIG. It has become clear that warping can occur in FIG. 39 shows the state of the semiconductor device 20 during operation of the semiconductor element 40, that is, at a high temperature. The dashed-dotted line in the drawing is a reference line indicating the direction of warpage.

The configuration shown in FIG. 39 is similar to the configuration described in the preceding embodiment (see FIG. 5). In FIG. 39, the external connection terminals 90 are omitted for the sake of convenience. In FIG. 39, the semiconductor device 20 and the heat exchange section 121 of the cooler 120 are arranged side by side in the Z direction, which is the predetermined direction. The heat exchange units 121 are arranged on both sides of the semiconductor device 20 in the Z direction so as to sandwich the semiconductor device. A thermally conductive member 130 such as silicone gel is arranged between each of the heat exchange portions 121 and the semiconductor device 20 . The cooler 120 cools the semiconductor device 20 by allowing the coolant to flow through the flow path of the heat exchange portion 121 . As the refrigerant to be flowed through the flow path, a phase-change refrigerant such as water or ammonia, or a phase-invariant refrigerant such as ethylene glycol-based refrigerant can be used. Thermally conductive member 130 is sometimes referred to as a thermal interface material (TIM). The heat conducting member 130 follows the opposing surfaces of the heat exchanging portion 121 and the semiconductor device 20 and fills the gap between the opposing surfaces.

As described above, in the semiconductor element 40, the drain electrode 40D, which is the main electrode on the high potential side, has a larger electrode area than the source electrode 40S, which is the main electrode on the low potential side. Also, the conductive spacer 70 is interposed between the source electrode 40S and the substrate 60, whereas the conductive spacer 70 is not interposed between the drain electrode 40D and the substrate 50. FIG. That is, the heat transfer path from the semiconductor element 40 to the substrate 50 has a smaller thermal resistance than the heat transfer path from the semiconductor element 40 to the substrate 60 . In the semiconductor device 20 having such a configuration, it is required to effectively dissipate heat to the substrate 50 side.

As shown in FIG. 39, when the substrate 50 side is concave and the substrate 60 side is convex, the warp occurs, the distance between the back surface 50b of the substrate 50, which is the exposed surface, and the heat exchanging portion 121 is increased, and the intervening heat conducting member 130 is increased. becomes thicker. As a result, the thermal resistance between the substrate 50 and the heat exchange portion 121 increases, and heat transfer (heat exchange) between the semiconductor device 20 and the cooler 120 (heat exchange portion 121) becomes difficult. The warped state shown in FIG. 39 is not preferable for effectively releasing the heat of the semiconductor element 40, that is, for cooling the semiconductor device 20 efficiently. FIG. 39 shows an example of a double-sided cooling structure in which the coolers 120 (heat exchange units 121) are arranged on both sides of the semiconductor device 20. FIG. However, the single-sided cooling structure in which the cooler 120 is arranged only on the substrate 50 side in the Z direction also has the same problem.

<Structure of semiconductor device>
As a result of intensive studies, it has been found that the warping of the semiconductor device 20 can be controlled by adjusting the magnitude relationship between the thickness of the portion of the semiconductor device 20 closer to the substrate 50 than the semiconductor element 40 and the thickness of the portion closer to the substrate 60 . The semiconductor device 20 of this embodiment has a configuration based on this knowledge. FIG. 40 is a cross-sectional view showing the semiconductor device 20 of this embodiment. FIG. 40 shows an ideal state in which the semiconductor device 20 has no warp.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the previous embodiment (see FIGS. 2 to 13). FIG. 40 shows the semiconductor device 20 as well as the heat exchanging portion 121 of the cooler 120 and the heat conducting member 130, as in FIG. 40 shows a semiconductor module 140 including semiconductor devices 20, coolers 120, and heat conducting members 130. FIG. As an example, the semiconductor module 140 has a double-sided cooling structure in which the semiconductor device 20 is sandwiched between a pair of heat exchange portions 121 . The semiconductor device 20 is arranged side by side with the cooler 120 (heat exchange section 121) in the Z direction, which is a predetermined direction. The coolers 120 are arranged on both sides of the semiconductor device 20 .

The back metal bodies 53 and 63 are exposed from the sealing body 30 as back surfaces 50b and 60b of the substrates 50 and 60, respectively. One of the heat exchanging parts 121 of the cooler 120 is arranged to face the one surface 30a and the back surface 50b of the sealing body 30, and the other one of the heat exchanging parts 121 is arranged to face the back surface 30b and the back surface 60b of the sealing body 30. ing. Between the facing surfaces of the semiconductor device 20 and the heat exchanging portion 121, a heat conducting member 130 is arranged. The heat conducting member 130 is in close contact with the semiconductor device 20 and the heat exchanging portion 121 .

The semiconductor device 20 is configured such that the thickness T1 on the substrate 50 side of the semiconductor element 40 and the thickness T2 on the substrate 60 side of the semiconductor element 40 satisfy the relationship of T1≧T2. Other configurations are the same as those described in the preceding embodiment (see FIG. 5). The thickness T1 is the total thickness of the bonding material 101 , the conductive spacer 70 , the bonding material 102 and the substrate 60 . The thickness T2 is the total thickness of the bonding material 100 and the substrate 50 . The substrate 50 is thicker than the substrate 60 in order to satisfy the relationship T1≧T2. Substrate 50 is thicker than conductive spacers 70 . In substrate 50 , metal bodies 52 and 53 are thicker than insulating base material 51 . In substrate 60 , metal bodies 62 and 63 are thicker than insulating base material 61 . The configuration of the portions other than the relationship of thickness is the same as the configuration described in the first embodiment.

<Simulation result>
41 to 43 show the results of thermal stress simulations. FIG. 41 shows the state of the semiconductor device 20 shown in FIG. 40 at room temperature (RT). FIG. 42 shows the state of the semiconductor device 20 shown in FIG. 40 at a high temperature. The term "high temperature" means that the semiconductor element 40 is generating heat due to energization, that is, the semiconductor element 40 is in operation. As shown in FIGS. 41 and 42, semiconductor device 20 warps at high temperatures. In this embodiment, the relationship T1≧T2 is satisfied as described above, so the amount of expansion on the substrate 50 side is larger than that on the substrate 60 side, as indicated by the dashed arrow in FIG. This is because the coefficient of linear expansion of Cu constituting the metal bodies 52, 53, 62, 63 is the largest, and the substrate 50 is thick. As a result, a convex warp is generated on the side of the substrate 50, which is the first substrate, and a concave warp is generated on the side of the substrate 60, which is the second substrate. A dashed-dotted line in FIG. 42 is a reference line indicating the direction of warpage.

FIG. 43 shows the relationship between the ratio of thicknesses T1 and T2 and the amount of warpage at high temperatures. In this simulation, the semiconductor element 40, the conductive spacer 70, and the bonding materials 100, 101, and 102 are the same (common), and the thicknesses of the substrate 50 and the substrate 60 are adjusted so that the thickness ratio T1:T2 becomes a predetermined value. adjusted to The material composition was the same (common). The vertical axis shown in FIG. 43 indicates the amount of warpage in arbitrary units (a.u.). When the amount of warp is above 0 (zero), it indicates that the warp is convex toward the substrate 50 side and concave toward the substrate 60 side. It shows that the warp is convex on the 60 side. T1:T2 was set to 4 levels of 1:2, 1:1.3, 1:1 and 1.5:1.

As shown in FIG. 43, in the case of T1:T2=1:2, there is a concave warp on the substrate 50 side and a convex warp on the substrate 60 side, and the amount of convex warp on the substrate 60 side is the largest among the four levels. rice field. In the case of T1:T2=1:1.3, concave warpage occurred on the substrate 50 side and convex warpage occurred on the substrate 60 side. When T1:T2=1:1, the warpage turned into convex on the substrate 50 side and concave on the substrate 60 side. When T1:T2=1.5:1, a convex warp occurred on the substrate 50 side and a concave warp occurred on the substrate 60 side, and the warp amount of the convex warp on the substrate 50 side was the largest among the four levels.

Thus, when T1<T2, the substrate 50 side is concave and the substrate 60 side is warped, and when T1≧T2, the substrate 50 side is convex and the substrate 60 side is concave. was revealed to occur. In other words, by satisfying the relationship of T1≧T2, it is possible to control the warpage that occurs at high temperatures to be convex on the substrate 50 side and concave on the substrate 60 side. Further, it was found that the larger the T2 with respect to T1, the larger the amount of warp protruding toward the substrate 60 side, and the larger the T1 with respect to T2, the greater the amount of protruding warp toward the substrate 50 side.

<Summary of Third Embodiment>
In this embodiment, the semiconductor device 20 satisfies the relationship of thickness T1≧thickness T2. The thickness T1 on the side where the conductive spacer 70 is not interposed between the semiconductor element 40 and the substrate 50 is greater than or equal to the thickness T2 on the side where the conductive spacer 70 is interposed between the semiconductor element 40 and the substrate 60 . As a result, when the semiconductor element 40 is in operation (at high temperatures), the semiconductor device 20 is warped in such a manner that the semiconductor device 20 is convex toward the substrate 50 side and concave toward the substrate 60 side. Therefore, the opposing distance between the semiconductor device 20 and the cooler 120 (heat exchange portion 121) on the side of the substrate 50 that contributes greatly to the heat dissipation can be made narrower than in a configuration that satisfies the relationship of thickness T1<thickness T2. . Since the opposing distance is narrowed, the thermal resistance between the semiconductor device 20 and the cooler 120 is reduced. Thereby, the heat generated by the semiconductor element 40 can be efficiently released to the outside of the semiconductor device 20 . In other words, the cooling efficiency of the semiconductor device 20 can be enhanced.

Specifically, the thickness of the thermally conductive member 130 interposed between the semiconductor device 20 and the cooler 120 is thinner than in the configuration satisfying the relationship of thickness T1<thickness T2. As a result, thermal resistance between the semiconductor device 20 and the cooler 120 is reduced, and heat exchange between the semiconductor device 20 and the cooler 120 is facilitated. Therefore, heat generated by the semiconductor element 40 can be efficiently released to the outside of the semiconductor device 20 .

In this embodiment, the back metal body 53 is exposed from the sealing body 30 . Compared to the configuration in which the back metal body 53 is covered with the sealing body 30, heat dissipation can be enhanced. Similarly, the back metal body 63 is exposed from the sealing body 30 . Compared to the configuration in which the back surface metal body 63 is covered with the sealing body 30, heat dissipation can be enhanced.

<Modification>
Although an example of a double-sided heat dissipation structure has been shown, it is not limited to this. The semiconductor device 20 needs to efficiently release heat mainly from the substrate 50 side. Therefore, the cooler 120 (heat exchange unit 121) may be arranged only on the substrate 50 side in the Z direction with respect to the semiconductor device 20 . Even in such a single-sided heat dissipation structure, when the relationship T1≧T2 is satisfied, the warp is convex toward the substrate 50 at high temperatures. This reduces the thermal resistance between the semiconductor device 20 and the cooler 120 . Therefore, the heat generated by the semiconductor element 40 can be released efficiently.

Although both of the back metal bodies 53 and 63 have shown the example exposed from the sealing body 30, it is not limited to this. For example, a configuration in which only the back surface metal body 53 is exposed may be employed.

Although an example in which the semiconductor device 20 includes the semiconductor element 40H forming the upper arm 9H and the semiconductor element 40 forming the lower arm 9L is shown, the present invention is not limited to this. Only the semiconductor element 40 forming one of the arms may be provided. The semiconductor device 20 may include only one semiconductor element 40, for example. The semiconductor device 20 may include a semiconductor element 40 , a pair of substrates 50 and 60 sandwiching the semiconductor element 40 , and a conductive spacer 70 interposed between the semiconductor element 40 and the substrate 60 .

In the substrate 50, no particular mention was made of the relationship between the thicknesses of the metal bodies 52 and 53. FIG. For example, as shown in FIG. 44, the front metal body 52 may be thicker than the back metal body 53 . A drain electrode 40</b>D, which is the first main electrode of the semiconductor element 40 , is joined to the surface metal body 52 . Thermal resistance between the surface metal body 52 and the semiconductor element 40 is small. By thickening the surface metal body 52 near the semiconductor element 40, the heat generated by the semiconductor element 40 can be effectively diffused. That is, the heat of the semiconductor element 40 can be released efficiently. FIG. 44 is a cross-sectional view showing a modification. FIG. 44 corresponds to FIG.

As shown in FIG. 44, the front metal body 62 may be thicker than the back metal body 63 . By thickening the surface metal body 62 near the semiconductor element 40, the heat generated by the semiconductor element 40 can be effectively diffused.

As described above, the heat of the semiconductor element 40 having the main electrodes on both sides is transmitted mainly to the substrate 50 side with low thermal resistance. Therefore, as shown in FIG. 45, the front metal body 62 may be made thinner than the back metal body 63 . As a result, the thickness of the substrate 60 can be reduced, and thus the size of the semiconductor device 20 can be reduced. Since a thick metal body is not required, costs can also be reduced. FIG. 45 is a cross-sectional view showing a modification. FIG. 45 corresponds to FIG. In FIG. 45, the front metal body 52 is thicker than the back metal body 53 and the front metal body 62 is thinner than the back metal body 63 . Therefore, the heat of the semiconductor element 40 can be efficiently released, and the size and cost can be reduced.

The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, the second embodiment, and the modifications.

(Fourth embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve the connection reliability, the substrate and the signal terminal may satisfy a predetermined positional relationship as described in this embodiment.

<Semiconductor device>
First, the semiconductor device 20 of this embodiment will be described with reference to FIGS. 46 and 47. FIG. FIG. 46 shows the periphery of the signal terminal 93 in the semiconductor device 20 according to this embodiment. In FIG. 46, in order to show the positional relationship between the substrate 50 and the signal terminals 93, some elements of the semiconductor device 20 are omitted. 47 is a cross-sectional view taken along line XLVII-XLVII in FIG. 46. FIG. 46 and 47, the signal terminal 93L on the lower arm 9L side will be described as an example.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the previous embodiment (see FIGS. 2 to 13). As shown in FIG. 46, the semiconductor device 20 includes two semiconductor elements 40L. The semiconductor element 40L has a drain electrode 40D as a first main electrode on one surface and a source electrode 40S as a second main electrode and a signal pad 40P on the back surface. The semiconductor device 20 has four signal terminals 93L. Each signal terminal 93L extends in the Y direction and protrudes from the side surface 30d of the sealing body 30 to the outside. The four signal terminals 93L are arranged side by side in the X direction between the output terminals 92 in plan view in the Z direction.

<Shape and arrangement of signal terminals>
Next, the shape and arrangement of the signal terminal 93 will be described with reference to FIGS. 46 and 47. FIG.

As shown in FIG. 46, each signal terminal 93L has an overlapping portion 930 that overlaps the substrate 50 and a non-overlapping portion 931 that does not overlap the substrate 50 in plan view. The overlapping portion 930 faces the substrate 50 in the Z direction.

The overlapping portion 930 is a portion within a predetermined range from the end of the signal terminal 93L on the semiconductor element 40L side. A non-overlapping portion 931 is a portion other than the overlapping portion 930 . The overlapping portion 930 overlaps the insulating base material 51 of the substrate 50 to which the drain electrode 40D is electrically connected. The entire overlapping portion 930 overlaps the insulating base material 51 . The overlapping portion 930 overlaps the exposed portion 510 exposed from the surface metal body 52 in the insulating base material 51 . In this manner, the signal terminal 93L extends onto the substrate 50. As shown in FIG. That is, the signal terminal 93L is inserted to a position overlapping the substrate 50 in plan view.

Two of the four signal terminals 93L have a main portion 930a and a projecting portion 930b. The other two signal terminals 93L do not have protrusions 930b. The main portion 930a extends in the Y direction, which is the main extending direction of the signal terminals 93L. The protruding portion 930b is continuous with the main portion 930a and protrudes from the main portion 930a. The projecting portion 930b extends in a direction different from that of the main portion 930a. Projection 930b may be referred to as a branch. The planar shape of the main portion 930a can adopt various shapes such as a substantially L-shape, a substantially Y-shape, and a substantially T-shape. In the example shown in FIG. 46, one of the signal terminals 93L has a substantially L-shaped plane, and the other one of the signal terminals 93L has a substantially T-shaped plane.

As described in the previous embodiment (see FIG. 11), the relay wiring 55 of the surface metal body 52 has the notch 550 . The overlapping portion 930 of the signal terminal 93L overlaps the portion exposed from the notch 550 in the insulating base material 51 . The four signal terminals 93L are arranged side by side in the X direction between the output terminals 92 in plan view. Each signal terminal 93L has tie bar marks 93a. The tie bar trace 93a is a trace left on the side surface of the signal terminal 93L when the tie bar 94a of the lead frame 94 is removed, as described in the previous embodiment (see FIG. 10). The tie bar marks 93a are sometimes referred to as cutting marks. Each signal terminal 93L has tie bar marks 93a on both sides in the X direction. The tie bar mark 93 a is provided at a position outside the sealing body 30 in the non-overlapping portion 931 .

Each signal terminal 93L, as shown in FIG. 47, has a joint portion 93b, a tip portion 93c, a bent portion 93d, and an extended portion 93e. The joint portion 93b is a portion to which a bonding wire 110, which is a connection member, is joined. The joint portion 93b preferably includes a portion substantially parallel to the XY plane. The joint portion 93b is the portion closest to the surface of the insulating base material 51 (exposed portion 510) in the signal terminal 93L. The joint portion 93 b of this embodiment is floating with respect to the surface of the insulating base material 51 . The joint portion 93b is not in contact with the insulating base material 51, and the sealant 30 enters the gap between the lower surface of the joint portion 93b and the surface of the insulating base material 51 to fill the gap. The bonding wire 110 electrically connects the pad 40P formed on the same surface as the source electrode 40S and the signal terminal 93L.

The tip portion 93c is a portion closer to the tip side than the joint portion 93b, that is, the semiconductor element 40 (40L) side. The tip portion 93c is arranged above the joint portion 93b, that is, at a position away from the surface of the insulating base material 51 in the Z direction. The distal end portion 93c is lifted upward with distance from the joint portion 93b. The tip portion 93c has an R shape in the ZY cross section. The bent portion 93d is provided between the joint portion 93b and the extension portion 93e, which is a portion on the rear end side of the joint portion 93b. The bent portion 93 d is bent such that the extended portion 93 e is located above the joint portion 93 b , that is, at a position away from the surface of the insulating base material 51 . The bent portion 93d is bent to have a smaller cross-sectional area than other portions of the signal terminal 93, specifically, the joint portion 93b, the tip portion 93c, and the extension portion 93e. In other words, thin. The extension portion 93e is a portion closer to the rear end than the joint portion 93b. The extension part 93 e extends in the Y direction and is arranged inside and outside the sealing body 30 .

At least part of the joint portion 93b, the tip portion 93c, and the bent portion 93d is included in the overlapping portion 930 described above. At least part of the extended portion 93 e is included in the non-overlapping portion 931 . In the present embodiment, the non-overlapping portion 931 includes the extending portion 93e in its entirety. Each signal terminal 93L is formed by press punching. In the signal terminal 93L, the surface facing the insulating base material 51 is a press R surface 93f, and the back surface of the facing surface is a burr surface 93g where burrs are generated by punching. The configuration other than the above is the same as the configuration described in the first embodiment.

<How to connect bonding wires>
Next, a method of connecting the signal terminal 93 having the structure described above and the bonding wire 110 will be described with reference to FIG. FIG. 48 is a diagram for explaining wire bonding. Reference numeral 111 shown in FIG. 48 is a jig for holding the signal terminal 93L. Reference numeral 112 is a tool for ultrasonic bonding. Tool 112 is sometimes referred to as an ultrasonic bonder. A dashed line shown in FIG. 48 indicates the position of the signal terminal 93L that is pushed by the jig 111 and bent.

As shown in FIG. 48, first, the overlapping portion 930 of the signal terminal 93L is positioned so as to overlap the insulating base material 51, and the wire 110a is set to the portion to be joined. Then, the jig 111 applies pressure in the Z direction to elastically deform the signal terminal 93L and bring the overlapping portion 930 into contact with the surface of the insulating base material 51 . The jig 111 presses the overlapping portion 930 of the signal terminal 93L or its vicinity.

Then, ultrasonic bonding is performed using a tool 112 while the signal terminal 93L is in contact with the insulating base material 51 . Since the signal terminal 93L is received by the insulating base material 51, there is no need to separately prepare a receiving jig. When the ultrasonic bonding is completed and the tool 112 and the jig 111 are separated from the signal terminal 93L, the elastically deformed state is released and returns to the position before pressurization. The signal terminal 93L is part of the lead frame 94. As shown in FIG. Since the signal terminal 93L is supported by the outer frame 94b by the tie bar 94a, it returns to its original position when the pressure is released.

In the above description, the signal terminal 93L has been described as an example. However, the above configuration may be applied to the signal terminal 93H on the upper arm 9H side. Both the signal terminals 93H and 93L may have the above configuration. In the configuration described in the preceding embodiment (see FIG. 11), each of the signal terminals 93H and 93L overlaps the exposed portion of the insulating base material 51 . The P wiring 54 of the surface metal body 52 has a notch 540, and the signal terminal 93H overlaps the surface of the insulating base material 51 exposed from the notch 540. As shown in FIG.

<Summary of the fourth embodiment>
In this embodiment, the signal terminal 93 ( 93 L) overlaps the exposed portion 510 of the insulating base material 51 . However, the signal terminal 93 is non-bonded to the exposed portion 510 . In other words, the signal terminal 93 is not fixed to the insulating base material 51 and thus to the substrate 50 . As a result, the signal terminal 93 can absorb dimensional variation within the tolerance of each element constituting the semiconductor device 20, assembly variation when assembling each element, and the like. Therefore, when the sealing body 30 is molded, it is possible to suppress the concentration of stress on the electrical connections (joints) between the signal terminals 93 and the semiconductor element 40 . As a result, the semiconductor device 20 with high connection reliability can be provided.

In the present embodiment, the signal terminal 93 is inserted to a position overlapping the board 50 , that is, to the top of the board 50 . By adopting such an arrangement, the signal terminal 93 approaches the pad 40P of the semiconductor element 40 (40L) in the Y direction. Therefore, the length of the bonding wire 110, which is a connecting member, can be shortened compared to the configuration in which the signal terminals 93 are arranged only at positions that do not overlap with the substrate 50. FIG. Since the length of the bonding wire 110 can be shortened, it is possible to suppress the occurrence of wire sweep, short circuit due to wire sweep, wire disconnection, and the like during molding of the sealing body 30 by a transfer molding method or the like.

In this embodiment, the overlapping portion 930 of the signal terminal 93 is floating with respect to the surface of the exposed portion 510 of the insulating base material 51 . Sealing body 30 is interposed between the lower surface of overlapping portion 930 and the surface of exposed portion 510 . The sealing body 30 is also interposed between the joint portion 93 b and the exposed portion 510 . According to this, even if manufacturing variations are large in the plate thickness direction, the variations can be absorbed. In addition, since the signal terminal 93 is positioned above the insulating base material 51, it becomes easier to secure an insulating distance from the back surface metal body 53. FIG.

In this embodiment, the surface metal body 52 has a notch 550 (540). The notch 550 opens at the end in the Y direction, which is one direction perpendicular to the Z direction. The overlapping portion 930 of the signal terminal 93 overlaps the surface of the exposed portion 510 exposed from the notch 550 . By providing the notch 550 in the surface metal body 52 of the substrate 50 in this way, it is possible to suppress an increase in the physical size of the substrate 50 while ensuring an insulation distance between the surface metal body 52 and the signal terminal 93 .

In this embodiment, the non-overlapping portion 931 of the signal terminal 93 has tie bar marks 93a. As described above, the signal terminal 93L is a part of the lead frame 94 and is supported by the outer frame 94b by the tie bars 94a. Therefore, the signal terminal 93 can be bent by applying pressure and brought into contact with the exposed portion 510 of the insulating base material 51, and the bonding wire 110 can be bonded by ultrasonic bonding in this contact state. By releasing the pressurizing force after the completion of the bonding, it returns to its original position.

In this embodiment, the signal terminal 93 has a bent portion 93d between the joint portion 93b and the extended portion 93e. Due to the bent portion 93d, the extended portion 93e is arranged at a position farther from the exposed portion 510 (insulating base material 51) than the joint portion 93b in the Z direction. By having the bent portion 93d in this way, it is possible to secure an insulating distance between the signal terminal 93 and the back surface metal body 53 while suppressing an increase in size in the Z direction.

In this embodiment, the signal terminal 93 has a tip portion 93c. The tip portion 93c is farther from the exposed portion 510 (insulating base material 51) than the joint portion 93b in the Z direction. As a result, it is possible to prevent the tip of the signal terminal 93 from scratching the insulating base material 51 during the above-described bonding (during ultrasonic bonding) or the like. That is, it is possible to suppress the deterioration of insulation performance. Particularly in the present embodiment, the distal end portion 93c is lifted upwardly away from the joint portion 93b, so that the distal end portion 93c is less likely to come into contact with the insulating base material 51. As shown in FIG. In addition, since the tip portion 93c has an R shape in the ZY cross section, even if the tip portion 93c comes into contact with the tip portion 93c, the insulating base material 51 can be prevented from being damaged.

If the facing surface is the burr surface 93g, the insulating base material 51 may be scratched and the insulating performance may deteriorate. In this embodiment, the signal terminal 93 is configured such that the surface facing the exposed portion 510 is the pressed R surface 93f and the rear surface of the facing surface is the burr surface 93g. Thereby, it is possible to suppress the deterioration of the insulating performance of the insulating base material 51 .

<Modification>
The non-bonded configuration between the signal terminal 93 and the exposed portion 510 is not limited to the above example. For example, in FIG. 49, the overlapped portion 930 of the signal terminal 93 floats on the insulating base material 51 with a slight height gap between the surface of the exposed portion 510 and the surface of the exposed portion 510 to prevent the encapsulant from entering. there is Sealing body 30 has gap 31 between the lower surface of overlapping portion 930 and the surface of exposed portion 510 . The signal terminal 93 is not fixed to the insulating base material 51 (exposed portion 510). Therefore, an effect equivalent to that of the configuration shown in FIG. 47 can be obtained. FIG. 49 is a cross-sectional view showing a modification, and corresponds to FIG.

50, the overlapping portion 930 of the signal terminal 93 is in contact with the surface of the exposed portion 510. In FIG. Although the signal terminal 93 is in contact with the insulating base material 51 (exposed portion 510), it is not fixed. Therefore, an effect equivalent to that of the configuration shown in FIG. 47 can be obtained. FIG. 50 is a cross-sectional view showing a modification, and corresponds to FIG. A part of the lower surface of the joint portion 93b may be in contact with the insulating base material 51, and the other part may be arranged in a non-contact manner.

In the example shown in FIG. 47, the substrate 60 is arranged so as not to overlap the signal terminals 93 in plan view. In other words, the substrate 60 was not arranged above the signal terminals 93 . By adopting such an arrangement, the physical size of the substrate 60 can be reduced. In addition, it becomes easier to secure an insulating distance between the surface metal body 62 and the signal terminal 93 . However, the positional relationship between the signal terminal 93 and the substrate 60 is not limited to the example shown in FIG. For example, as shown in FIG. 51, the overlapping portion 930 of the signal terminal 93 also overlaps with the substrate 60 . The surface metal body 62 of the substrate 60 overlaps the overlapping portion 930 and the exposed portion 510 of the insulating base material 51 in plan view. According to this, heat dissipation can be improved. FIG. 51 is a cross-sectional view showing a modification, and corresponds to FIG.

52, unlike FIG. 51, the surface metal body 62 is patterned so as not to overlap the overlapping portion 930 of the signal terminal 93. In FIG. The insulating base material 61 and the back metal body 63 are positioned above the overlapping portion 930 . According to this, by making the surface metal body 62 small, it becomes easy to secure the insulation distance between the surface metal body 62 and the signal terminal 93 . Since the back surface metal body 63 is large, heat dissipation can be improved. FIG. 52 is a cross-sectional view showing a modification, and corresponds to FIG.

An example has been shown in which the length of the bonding wire 110 (connecting member) can be shortened by inserting the signal terminal 93 onto the substrate 50 . Alternatively, the length of the bonding wire 110 may be shortened by using the relay board 150 shown in FIGS. FIG. 53 is a plan view showing a modification, and corresponds to FIG. In FIG. 53, some elements of the semiconductor device 20 are omitted in order to show the positional relationship among the substrate 50, the signal terminals 93, and the relay substrate 150. As shown in FIG. FIG. 54 is a cross-sectional view showing a relay board. 55 is a cross-sectional view along line LV-LV in FIG. 53. FIG. Although the relay wiring 55 and the signal terminal 93L are shown here as an example, the same configuration can be adopted for the P wiring 54 and the signal terminal 93H.

The semiconductor device 20 further includes a relay board 150 . As shown in FIGS. 53 and 55 , the relay board 150 is arranged on the surface metal body 52 (relay wiring 55 ) of the board 50 . As shown in FIG. 54 , the relay board 150 has an insulating base material 151 and a conductor portion 152 arranged on the insulating base material 151 . A portion of conductor portion 152 provides a wiring function. The relay board 150 is sometimes called a printed board or wiring board.

The conductor portion 152 has lands 152a and 152b. Lands 152 a and 152 b are exposed on one surface of relay board 150 . Specifically, it is exposed from the solder resist 153 provided on one surface 151 a of the insulating base material 151 . The land 152a is electrically connected to the pad 40P via the bonding wire 110. As shown in FIG. The signal terminal 93 overlaps the substrate 50 in plan view. The signal terminal 93 is connected to the land 152b.

Conductor portion 152 has wiring 152c and via conductor 152d other than lands 152a and 152b. At least part of the wiring 152 c is an inner layer wiring arranged inside the insulating base material 151 . Land 152a and land 152b are electrically connected via wiring 152c and via conductor 152d. The plurality of lands 152a includes two lands 152a individually connected to the gate electrode pads 40P of the two semiconductor elements 40 . The two lands 152a for the gate electrode are electrically connected to one land 152b for the gate electrode through the wiring 152c and the via conductor 152d.

Using the relay substrate 150 in this manner allows the connection target (land 152a) of the bonding wire 110 to be brought closer to the pad 40P. Thereby, the length of the bonding wire 110 electrically connecting the pad 40P and the signal terminal 93 can be shortened. In addition, the wiring 152c can be freely routed within the relay substrate 150. FIG. This can prevent the bonding wires 110 from crossing in a configuration in which the semiconductor elements 40 are connected in parallel. Therefore, it is possible to suppress contact between the wires when molding the sealing body 30 . In addition, it is possible to reduce the physical size to the same extent as the configuration shown in FIG. 47 by the fine wiring technology of the printed circuit board.

The conductor portion 152 further has a fixing land 152e. The fixing land 152 e is a land for fixing the relay board 150 to the board 50 . The fixing land 152e does not provide an electrical connection function, that is, a wiring function. The fixing land 152 e is arranged on the back surface 151 b of the insulating base material 151 . The fixing land 152 e (relay board 150 ) is joined to the surface metal body 52 via the joining material 154 . Solder, for example, can be used as the bonding material 154 .

Since the relay substrate 150 is fixed to the surface metal body 52 in this manner, wire bonding can be performed stably. Solder containing Ni balls may be used as the bonding material 154 . In this case, the Ni balls can control the thickness of the bonding material 154 . In addition, tilting of the relay board 150 can be suppressed.

The wiring function provided by the conductor portion 152 is electrically separated from the surface metal body 52 by the insulating base material 151 . For example, the insulating base material 151 may have, in the Z direction, a non-arrangement area 151c where the conductor part 152 is not arranged and an arrangement area 151d where the conductor part 152 is arranged. In the Z direction, the non-arrangement area 151c is provided in the center of the insulating base material 151, and the arrangement areas 151d are provided on both surface layers. The non-placement region 151c is sometimes called a core layer. Since the insulating base material 151 has the non-arrangement area 151c, the conductor part 152 that provides the wiring function and is arranged on the one surface 151a side is electrically connected to the fixing land 152e and thus the surface metal body 52. can be separated.

The solder resist 153 has low adhesion to the sealing body 30 . In addition, peeling of the sealing body 30 due to thermal stress progresses starting from the outer peripheral edge of the relay substrate 150 . For example, insulating base material 151 may have exposed portion 151 e exposed from solder resist 153 . The exposed portion 151 e is provided on the outer peripheral edge portion of the one surface 151 a of the insulating base material 151 . The insulating base material 151 has higher adhesion to the sealing body 30 than the solder resist 153 . The sealing body 30 is in close contact with the relay substrate 150 at the exposed portion 151e. As a result, peeling of the sealing body 30 from the relay substrate 150 can be suppressed. Since the sealant 30 is in close contact with the outer peripheral portion, the conductor portion 152 such as the lands 152a and 152b exposed from the solder resist 153 can be protected.

As shown in FIG. 55, the signal terminal 93 (93L) has a first extension portion 93h, a second extension portion 93i, and a bent portion 93j. The first extending portion 93h and the second extending portion 93i extend in the Y direction. The first extending portion 93 h is arranged inside the sealing body 30 . The second extending portion 93i is arranged inside and outside the sealing body 30 . The bent portion 93j is provided between the first extended portion 93h and the second extended portion 93i. The first extension portion 93h is a portion closer to the front end than the bent portion 93j, and the second extension portion 93i is a portion closer to the rear end than the bent portion 93j.

The signal terminal 93 may have a protrusion 93k. The projecting portion 93 k is provided near the tip of the signal terminal 93 . The protrusion 93k protrudes from the first extension 93h toward the land 152b in the Z direction. The projecting portion 93k is joined to the land 152b. In the signal terminal 93, the tip portion of the first extended portion 93h and the projecting portion 93k overlap the land 152b in a plan view in the Z direction. The portion where the tip portion of the first extension portion 93h and the projecting portion 93k continue is a thick portion, and the other portion of the signal terminal 93 is a thin portion. By providing the projecting portion 93 k in this way, the signal terminal 93 (the first extending portion 93 h ) is kept away from the surface metal body 52 , so that an insulating distance can be easily secured between the signal terminal 93 and the surface metal body 52 .

FIG. 56 shows another example from FIG. FIG. 56 corresponds to FIG. In FIG. 56 , the relay board 150 is fixed to the exposed portion 510 of the insulating base material 51 . In this case, the insulation distance between the signal terminal 93 and the back surface metal body 53 can be ensured by the thickness of the bonding material 154 and the relay board 150 . When the above solder containing Ni balls is used as the bonding material 154, a predetermined thickness can be secured, making it easier to secure the insulating distance. In addition, tilting of the relay board 150 can be suppressed.

Surface metal body 52 (relay wiring 55) exposes insulating base material 51 by having notch 550 as shown in FIG. 46, for example. For example, the surface metal body 52 may have a chamfer 554 . Chamfered portion 554 is provided at least on a surface of end surfaces defining cutout 550 where imaginary straight lines connecting semiconductor element 40 and relay substrate 150 intersect. The chamfered portion 554 is provided at the upper end of the end surface. Thereby, the insulation distance between the bonding wire 110 and the surface metal body 52 can be ensured.

An example is shown in which the semiconductor device 20 includes the substrate 60 electrically connected to the source electrode 40S. That is, an example of the semiconductor device 20 having a double-sided heat dissipation structure including the pair of substrates 50 and 60 is shown. However, it is not limited to this example. It can also be applied to a semiconductor device 20 having a single-sided heat dissipation structure, which includes only a substrate 50 to which a drain electrode 40D (first main electrode) is connected. Although both of the back metal bodies 53 and 63 have shown the example exposed from the sealing body 30, it is not limited to this.

Although an example in which the semiconductor device 20 includes the semiconductor element 40H forming the upper arm 9H and the semiconductor element 40 forming the lower arm 9L is shown, the present invention is not limited to this. Only the semiconductor element 40 forming one of the arms may be provided. The semiconductor device 20 may include only one semiconductor element 40, for example.

The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, second embodiment, third embodiment, and modifications.

(Fifth embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to ensure the insulation reliability and reduce the size of the body, the connecting portion between the metal member and the surface metal body via the bonding material may have a predetermined structure as described in the present embodiment.

<Semiconductor device>
First, based on FIG. 57, the semiconductor device 20 of this embodiment will be described. FIG. 57 corresponds to FIG.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the previous embodiment (see FIGS. 2 to 13). As shown in FIG. 57, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. As shown in FIG. A surface metal body 52 of the substrate 50 is connected to a drain electrode 40</b>D, which is the main electrode of the semiconductor element 40 . The surface metal body 52 is connected to the P terminal 91P and the output terminal 92, which are main terminals, through the bonding material 104. As shown in FIG. The surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. As shown in FIG. The surface metal body 62 is connected via a bonding material 104 to an N terminal 91N (not shown), which is a main terminal. The sealing body 30 seals the semiconductor element 40 , the substrates 50 and 60 , part of each of the main terminals, and the bonding material 104 .

<Joint structure of main terminal>
Next, the joining structure of the main terminals will be described with reference to FIGS. 57 to 60. FIG. 58 is a plan view of the periphery of the output terminal 92 of FIG. 57 viewed from the direction of LVIII. In FIG. 58, it is partially hatched for clarity. FIG. 59 is an enlarged view of the area LVIX indicated by the one-dot chain line in FIG. FIG. 60 is a diagram showing a state in which the bonding material 104 is removed from FIG. 59 and 60, the sealing body 30 is omitted for the sake of convenience.

As shown in FIG. 57, the bonding structure of the P terminal 91P and the output terminal 92, which are main terminals, to the substrate 50 is different from the configuration described in the previous embodiment (see FIG. 5). Although not shown, the junction structure of the N terminal 91N, which is the main terminal, is also different. Other configurations are the same as those described in the preceding embodiments. Below, the output terminal 92 will be described as an example. The bonding material 104 wets and spreads on the metal surface during bonding. As an example, the bonding material 104 is solder.

As shown in FIG. 57, the substrate 50 has ends 50c and 50d in the Y direction. The end portion 50c is the end portion on the side surface 30c side of the sealing body 30, and the end portion 50d is the end portion on the side surface 30d side. The output terminal 92 straddles the end portion 50d of the substrate 50 and extends in the Y direction. In plan view in the Z direction, a portion of the output terminal 92 overlaps the surface metal body 52 (relay wiring 55), and the other portion does not overlap. As shown in FIGS. 58 to 60, the output terminal 92 has a facing surface 920 and a housing portion 921. As shown in FIGS.

The facing surface 920 is a portion of the lower surface of the output terminal 92 that faces the surface metal body 52 (relay wiring 55) of the substrate 50 in the Z direction. The opposing surface 920 is macroscopically a flat surface, and ideally contacts the upper surface 52a of the surface metal body 52 over the entire surface. The facing surface 920 has minute unevenness on the surface microscopically, and at least a portion thereof contacts the upper surface 52a. The facing surface 920 is sometimes referred to as a metal touch surface. The facing surface 920 is a portion within a predetermined range in the Y direction from the position overlapping the end portion 52b of the surface metal body 52 in plan view. The end portion 52b is an end surface (side surface) on the side surface 30d side of the sealing body 30 in the Y direction, and continues to the upper surface 52a. The end portion 52b forms part of the end portion 50d. The facing surface 920 has a substantially rectangular planar shape.

The accommodation portion 921 is provided adjacent to the facing surface 920 and provides an accommodation space for the bonding material 104 . For example, the accommodation portion 921 is a concave portion that is recessed with respect to the opposing surface 920 in a direction away from the upper surface 52a. The accommodating portion 921, which is a concave portion, is a surface including a Z-direction component, and has a side surface 921a connected to the facing surface 920 and a bottom surface 921b connected to the side surface 921a. The side surface 921a is, for example, a surface substantially parallel to the Z direction. The accommodating portion 921 opens in a front end surface 922 that is a side surface of the output terminal 92 on the prior application side in the Y direction. The accommodating portion 921 opens to side surfaces 923 and 924 on both sides of the output terminal 92 in the X direction. The accommodating portion 921 is provided within a predetermined range from the tip surface 922 of the output terminal 92 in the Y direction. The accommodation portion 921 has a substantially rectangular shape in plan view. The housing portion 921 is provided in parallel with the X direction in the Y direction.

The output terminal 92 accommodates the bonding material 104 in the accommodating portion 921 with the opposing surface 920 in contact with the surface metal body 52 . The bonding material 104 may be arranged only inside the accommodating portion 921, or part of the bonding material 104 may be arranged outside the accommodating portion 921 as shown in FIG. In FIG. 59, the bonding material 104 forms a fillet with respect to the distal end surface 922 . The output terminal 92 is connected (bonded) to the surface metal body 52 via the bonding material 104 arranged in the housing portion 921 .

<Method of connecting the main terminal>
A joint structure between the output terminal 92 and the surface metal body 52 is formed, for example, as follows. With the bonding material 104 (solder) placed in the accommodating portion 921, the upper portion of the opposing surface 920 of the output terminal 92 is directed toward the substrate 50 in the Z direction so that the opposing surface 920 strongly contacts the upper surface 52a. pressurize. Reflow is performed while the facing surface 920 is in strong contact with the upper surface 52a. For this reason, the bonding material 104 does not wet and spread on the opposing surface 920 side during reflow, or even if it does wet and spread, it only gets into the recesses of the fine irregularities on the surface of the opposing surface 920 .

<Summary of the fifth embodiment>
In this embodiment, the opposing surface 920 of the output terminal 92 which is a metal member contacts (metal touches) the upper surface 52a of the surface metal body 52 . As a result, overflow of the bonding material 104 from the accommodating portion 921 toward the opposing surface 920 can be suppressed. As a result, it is possible to suppress the wetting and spreading of the bonding material 104 in an unintended direction, thereby ensuring insulation reliability. Also, the output terminal 92, which is a single member, has both the accommodating portion 921 and the facing surface 920. As shown in FIG. As a result, it is possible to provide the semiconductor device 20 that achieves both insulation reliability and size reduction.

In the configuration provided with the substrate 50, when the bonding material 104 wets and spreads over the end portion 52b (end face) of the surface metal body 52 and further on the insulating base material 51, the portion having the same potential as that of the surface metal body 52 spreads, and the back metal body 52 spreads. Closer to 53. The bonding material 104 may come into contact with the back metal body 53 . In this embodiment, the facing surface 920 is provided closer to the end 50 d of the substrate 50 , that is, to the end 52 b of the surface metal body 52 than to the accommodating portion 921 . By arranging the facing surface 920 on the side of the end portion 52b, the bonding material 104 is prevented from spreading over the surface of the output terminal 92 and/or the surface metal body 52 and reaching the end portion 52b and, in turn, the insulating base material 51. can do. Thereby, the insulation reliability can be improved without increasing the size.

As described above, the metal member having the facing surface and the accommodating portion can also be applied to the P terminal 91P and the N terminal 91N, which are other main terminals. The P terminal 91P is connected to the surface metal body 52 (P wiring 54) of the substrate 50 via the bonding material 104. As shown in FIG. Since the facing surface of the P terminal 91P contacts the surface metal body 52, it is possible to suppress the overflow of the bonding material 104 from the receiving portion of the P terminal 91P to the facing surface side. As shown in FIG. 57 , by providing the facing surface on the edge 50 c side of the substrate 50 , the bonding material 104 can be prevented from wetting and spreading on the edge of the surface metal body 52 and the insulating base material 51 .

The N terminal 91N is connected to the surface metal body 62 (N wiring 64) of the substrate 60 via the bonding material 104. As shown in FIG. Since the facing surface of the N terminal 91N is in contact with the surface metal body 62, it is possible to suppress the overflow of the bonding material 104 from the accommodating portion of the N terminal 91N to the facing surface side. 57, the bonding material 104 can be prevented from wetting and spreading over the edge of the surface metal body 62 and the insulating base material 61. FIG. The end portion 60c is an end surface (side surface) on the side surface 30c side of the sealing body 30 in the Y direction.

<Modification>
The arrangement of the facing surface 920 and the accommodating portion 921 is not limited to the above example. For example, the configurations shown in FIGS. 61 and 62 may be employed. FIG. 61 is a plan view showing a modification, and corresponds to FIG. 62 is a plan view seen from the LXII direction shown in FIG. 61. FIG. In this example, the housing portion 921 does not open to the side surfaces 923 and 924 and opens only to the tip surface 922 . The accommodation portion 921 has an opening 921c on a tip surface 922, which is a side surface.

The facing surface 920 has a first facing portion 920a and a second facing portion 920b. The first facing portion 920a is provided on the opposite side of the housing portion 921 from the opening 921c. The first facing portion 920a is adjacent to the accommodating portion 921 in the Y direction, which is the direction in which the output terminal 92 extends. The second facing portion 920b is adjacent to the accommodating portion in the X direction. In the example shown in FIGS. 61 and 62, the facing surface 920 has a pair of second facing portions 920b. The pair of second facing portions 920b sandwich the accommodating portion 921 in the X direction. The facing surface 920 has a planar substantially U-shape (substantially U-shape). Since the facing surface 920 is arranged in three directions with respect to the accommodating portion 921, the overflow direction of the bonding material 104 from the accommodating portion 921 can be restricted to one direction on the opening 921c side. Thereby, insulation reliability can be further improved.

Note that the facing surface 920 may be configured to include only one second facing portion 920b. In this case, the facing surface 920 has a substantially L-shaped plane. Since the opposing surfaces 920 are arranged on two sides with respect to the accommodating portion 921, the direction in which the bonding material 104 overflows from the accommodating portion 921 can be restricted with respect to the arrangement of FIG. Thereby, insulation reliability can be improved.

Although an example in which the accommodating portion 921 opens on the side surface of the output terminal 92 has been shown, the present invention is not limited to this. Moreover, the planar shape of the accommodating portion 921 is not limited to a substantially rectangular shape. For example, as shown in FIG. 63, a housing portion 921 having no side openings may be provided. FIG. 63 is a plan view showing a modification, and corresponds to FIG. In FIG. 63, the accommodating portion 921 has a substantially circular planar shape. The accommodation portion 921 is a hole that opens to the lower surface of the output terminal 92 . The accommodating portion 921 shown in FIG. 63 is a non-through hole. The accommodation portion 921, which is a non-through hole, has a side surface 921a and a bottom surface 921b connected to the opposing surface 920, like the accommodation portion 921 described above. Instead of this, a through hole that opens to the upper surface of the output terminal 92 may be employed. The accommodation portion 921, which is a through hole, does not have a bottom surface 921b and has a side surface 921a.

The metal member having the facing surface and the receiving portion is not limited to the main terminal. For example, as shown in FIGS. 64 and 65, in semiconductor device 20 forming upper and lower arm circuits 9, joint portion 81 may be provided with a facing surface and a housing portion. FIG. 64 is a cross-sectional view showing a modification, and corresponds to FIG. FIG. 65 is an enlarged view of the region LXV indicated by the dashed line in FIG. In FIG. 65, for the sake of convenience, the sealing body 30 is omitted.

As described in the preceding embodiment, the semiconductor device 20 includes a semiconductor element 40H, which is the first semiconductor element forming the upper arm 9H, and a semiconductor element 40L, which is the second semiconductor element forming the lower arm 9L. . The joint portion 81 electrically connects the source electrode 40S of the semiconductor element 40H and the drain electrode 40D of the semiconductor element 40L. The joint portion 81 is a metal columnar body extending in the Z direction. An end portion 81 a of the joint portion 81 is connected to the relay wiring 55 that is the first wiring of the substrate 50 via the bonding material 103 . An end portion 81 b opposite to the end portion 81 a is connected to a relay wiring 65 that is a third wiring of the substrate 60 via a bonding material 103 . The surface metal body 52 has a P wiring 54 which is a second wiring provided with a predetermined gap from the relay wiring 55 . The surface metal body 62 has an N wiring 64 which is a fourth wiring provided with a predetermined gap from the relay wiring 65 .

In the example shown in FIGS. 64 and 65, the end portions 81a and 81b of the joint portion 81 are respectively provided with a facing surface 810 and a housing portion 811. In the example shown in FIGS. The configurations of the facing surface 810 and the housing portion 811 are the same as those of the facing surface 920 and the housing portion 921 described above. At the end portion 81a, the facing surface 810 faces the upper surface 52a of the surface metal body 52 (relay wiring 55). The facing surface 810 is in contact with the upper surface 52a. The accommodating portion 811 is a concave portion recessed with respect to the facing surface 810 . The accommodation portion 811 has a side surface 811a connected to the facing surface 810 and a bottom surface 811b. The containing portion 811 contains the bonding material 103 .

The facing surface 810 and the accommodating portion 811 are provided side by side in the Y direction. The facing surface 810 is provided on the side of the inter-wiring gap 52G separating the relay wiring 55 and the P wiring 54, that is, at a position close to the P wiring 54, which is wiring different from the relay wiring 55 to which the joint portion 81 is connected. The accommodating portion 811 is open to the side surface 812 of the joint portion 81 in the Y direction, and is not open to the side surface 813 opposite to the side surface 812 . The housing portion 811 may be opened only on the side surface 812 or may be opened on three side surfaces including two side surfaces adjacent to the side surface 812 .

Thus, the opposing surface 810 of the joint portion 81 contacts (metal touches) the surface metal body 52 . As a result, overflow of the bonding material 103 from the accommodating portion 811 to the facing surface 810 side can be suppressed. Therefore, it is possible to provide the semiconductor device 20 that achieves both insulation reliability and size reduction.

Further, when the bonding material 103 wets and spreads in the inter-wiring gap 52G of the surface metal body 52, the portion having the same potential as that of the relay wiring 55 expands, and the distance to the P wiring 54 becomes shorter. The bonding material 103 may also come into contact with the P wiring 54 . On the other hand, in the example described above, the facing surface 810 is provided at a position closer to the P wiring 54, that is, the inter-wiring gap 52G, than the accommodation portion 811 is. This can prevent the bonding material 103 from reaching the inter-wiring gap 52G. Therefore, insulation reliability can be improved without increasing the size.

The configuration of the end portion 81b is the same as that of the end portion 81a. At the end portion 81b, the facing surface 810 faces the upper surface 62a of the surface metal body 62 (relay wiring 65). The facing surface 810 is in contact with the upper surface 52a. The accommodation portion 811 is a concave portion. The containing portion 811 contains the bonding material 103 . The facing surface 810 and the accommodating portion 811 are provided side by side in the Y direction. The facing surface 810 is provided on the inter-wiring gap 62G separating the relay wiring 65 and the N wiring 64, that is, at a position close to the N wiring 64, which is a wiring different from the relay wiring 65 to which the joint portion 81 is connected. The accommodating portion 811 opens to the side surface 813 of the joint portion 81 in the Y direction and does not open to the side surface 812 . The housing portion 811 may be opened only on the side surface 813 or may be opened on three side surfaces including two side surfaces adjacent to the side surface 813 .

Thus, the opposing surface 810 of the joint portion 81 contacts (metal touches) the surface metal body 62 . As a result, overflow of the bonding material 103 from the accommodating portion 811 to the facing surface 810 side can be suppressed. Therefore, it is possible to provide the semiconductor device 20 that achieves both insulation reliability and size reduction. In addition, the facing surface 810 is provided at a position closer to the N wiring 64, that is, the inter-wiring gap 62G, than the accommodating portion 811 is. This can prevent the bonding material 103 from reaching the inter-wiring gap 62G. Therefore, insulation reliability can be improved without increasing the size.

In the above example, the overflow of the bonding material is suppressed by the contact of the surface metal body with the facing surface of the metal member. By further adding an uneven oxide film formed by laser irradiation to this structure, the function of suppressing the overflow may be enhanced. An example is shown in FIGS. 66 and 67. FIG. FIG. 66 is a cross-sectional view corresponding to FIG. 65, omitting the sealing body 30 for convenience. FIG. 67 is an enlarged view of the region LXVII indicated by the dashed line in FIG. 66, showing only the surface metal body 52. FIG.

In the example shown in FIG. 66, uneven oxide films 520 and 620 are provided on the surface metal bodies 52 and 62 corresponding to the joint portion 81, respectively. The uneven oxide film 520 will be described below as an example. As shown in FIG. 67, the surface metal body 52 has a base material 521 and a metal film 522 and an uneven oxide film 520 provided on the surface of the base material 521 . The base material 521 constitutes the main portion of the surface metal body 52 . Base material 521 is formed using, for example, a Cu-based material. The metal film 522 is formed containing a material having higher wettability to solder than the base material 521 . The metal film 522 is formed over the entire upper surface 52a. The metal film 522 of this embodiment is formed over the entire surface of the base material 521 . The uneven oxide film 520 is locally formed on the upper surface 52a.

The uneven oxide film 520 is locally formed on the metal film 522 on the upper surface 52a by irradiating the metal film 522 with laser light. The metal film 522 has a base film whose main component is Ni (nickel) and an upper film whose main component is Au (gold). In this embodiment, an electroless Ni plating film containing P (phosphorus) is used as the base film. When the bonding material 103 is solder, of the metal film 522 exposed from the uneven oxide film 520, the overlying film (Au) of the portion in contact with the bonding material 103 diffuses into the solder during reflow. Of the metal film 522 , the overlying film (Au) in the portion where the uneven oxide film 520 is formed is removed by laser light irradiation when the uneven oxide film 520 is formed. The uneven oxide film 520 is an oxide film containing Ni as a main component. For example, of the components forming the uneven oxide film 520, 80% is Ni ₂ O ₃ , 10% is NiO, and 10% is Ni.

A concave portion 523 on the surface of the metal film 522 is formed by irradiating pulsed laser light. One recess 523 is formed for each pulse. The uneven oxide film 520 is formed by melting, vaporizing, and vapor-depositing the surface layer portion of the metal film 522 by laser light irradiation. The uneven oxide film 520 is an oxide film derived from the metal film 522 . The uneven oxide film 520 is an oxide film of metal (Ni), which is the main component of the metal film 522 . The uneven oxide film 520 is formed following the unevenness of the surface of the metal film 522 having the concave portions 523 . On the surface of the uneven oxide film 520, unevenness is formed at a finer pitch than the width of the recesses 523. FIG. That is, very fine unevenness (roughened portion) is formed.

Such an uneven oxide film 520 can be formed by the steps shown below. First, the upper surface 52a of the surface metal body 52 having the metal film 522 formed on the base material 521 is irradiated with pulsed laser light to melt and evaporate the surface of the metal film 522 . The pulse oscillation laser light is adjusted to have an energy density of 0 J/cm ² or more and 100 J/cm ² or less and a pulse width of 1 μsec or less. A YAG laser, a _YVO4 laser, a fiber laser, or the like can be employed to satisfy this condition. For example, in the case of YAG laser, the energy density should be 1 J/cm ² or more. In the case of electroless Ni plating, the metal film 522 can be processed even at about 5 J/cm ² , for example.

At this time, by relatively moving the light source of the laser light and the surface metal body 52, the laser light is scanned and sequentially irradiated to a plurality of positions. A concave portion 523 is formed on the surface of the metal film 522 by irradiating the laser beam to melt and vaporize the surface of the metal film 522 . The average thickness of the portion of the metal film 522 irradiated with laser light is thinner than the average thickness of the portion not irradiated with laser light. In addition, the plurality of recesses 523 formed corresponding to the spots of the laser light are continuous and have a scaly shape, for example. A spot is an irradiation range by one pulse. For example, the laser beams are scanned so that the laser beam spots that are adjacent in the X direction partially overlap and the laser beam spots that are adjacent in the Y direction are partially overlapped.

Then, the melted portion of the metal film 522 is solidified. Specifically, the metal film 522 melted and vaporized is vapor-deposited on the portion irradiated with the laser light and its peripheral portion. By depositing the melted and vaporized metal film 522 in this manner, the uneven oxide film 520 is formed on the surface of the metal film 522 .

In FIG. 66, the uneven oxide film 520 is not provided in the first region 524 of the upper surface 52a of the surface metal body 52, which overlaps with the accommodating portion 811 of the joint portion 81 in plan view. The uneven oxide film 520 is selectively provided in a second region 525 overlapping the facing surface 810 . The structures of the surface metal body 62 and the uneven oxide film 620 are the same as those of the surface metal body 52 and the uneven oxide film 520 . The uneven oxide film 620 is not provided in a first region 624 of the upper surface 62a of the surface metal body 62, which overlaps with the accommodation portion 811 of the joint portion 81 in plan view. The uneven oxide film 620 is selectively provided in a second region 625 overlapping the facing surface 810 .

The oxide films (uneven oxide films 520 and 620) have lower wettability with respect to the bonding material 103 than metal films. Since the uneven oxide films 520 and 620 have fine unevenness on the surface, the contact area with the bonding material 103 becomes small, and a part of the bonding material 103 becomes spherical due to surface tension. That is, the contact angle increases. As a result, wettability with respect to the bonding material 103 is low. Therefore, due to the wettability reduction effect of the uneven oxide films 520 and 620 and the contact effect of the opposing surface 810 , it is difficult for the bonding material 103 to pass between the opposing surface 810 and the second regions 525 and 625 . As a result, overflow of the bonding material 103 can be more effectively suppressed. Since laser light is used to form the uneven oxide films 520 and 620 as described above, patterning is easy.

As shown in FIG. 68, uneven oxide films 520 and 620 may be provided in the peripheral regions 526 and 626 . The peripheral area 526 is an area around the second area 525 in plan view, excluding the first area 524 . The peripheral area 626 is an area around the second area 625 in plan view, excluding the first area 624 . Even if the bonding material 103 passes directly under the facing surface 810 of the joint portion 81 , the irregular oxide films 520 and 620 can block it. In addition, since extremely fine irregularities are formed on the surfaces of the irregular oxide films 520 and 620, the encapsulant 30 is entangled with them, resulting in an anchor effect. Also, the contact area with the sealing body 30 increases. Therefore, the adhesion of the surface metal bodies 52 and 62 to the sealing body 30 can be enhanced.

In addition, the uneven oxide films 520 and 620 may be provided in the second regions 525 and 625 and the peripheral regions 526 and 626 . Only one of the uneven oxide films 520 and 620 may be provided. The uneven oxide films 520 and 620 may be used for joints with the main terminals, ie, the P terminal 91P, the N terminal 91N, and the output terminal 92, which are metal members.

An example is shown in which the semiconductor device 20 includes the substrate 60 electrically connected to the source electrode 40S (second main power station). That is, an example of the semiconductor device 20 having a double-sided heat dissipation structure including the pair of substrates 50 and 60 is shown. However, it is not limited to this example. It can also be applied to a semiconductor device 20 having a single-sided heat dissipation structure, which includes only a substrate 50 to which a drain electrode 40D (first main electrode) is connected. In the semiconductor device 20 having a pair of substrates 50 and 60, the above structure may be applied only to the junction between one of the substrates 50 and 60 and the metal member. Although both of the back metal bodies 53 and 63 have shown the example exposed from the sealing body 30, it is not limited to this.

Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been shown, the present invention is not limited to this. Only the semiconductor element 40 forming one of the arms may be provided. The semiconductor device 20 may include only one semiconductor element 40, for example.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, and modifications.

(Sixth embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve the reliability of the semiconductor device, the physical properties of the sealing body and the physical properties of the insulating base material may satisfy a predetermined relationship, as described in this embodiment.

<Semiconductor device and heat dissipation structure>
Based on FIG. 69, the semiconductor device 20 of this embodiment and its heat dissipation structure will be described. FIG. 69 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. FIG. 69 is an enlarged view of a portion of FIG. In FIG. 69, the external connection terminals 90 are omitted for convenience.

The semiconductor device 20 of this embodiment has a structure similar to that described in the previous embodiment (see FIGS. 2 to 13). As shown in FIG. 69, the semiconductor device 20 includes a semiconductor element 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. As shown in FIG. A surface metal body 52 of the substrate 50 is connected to a drain electrode 40</b>D, which is the main electrode of the semiconductor element 40 . A surface metal body 62 of the substrate 60 is connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. As shown in FIG. The back metal bodies 53 and 63 are exposed from the sealing body 30 . The insulating base materials 51 and 61 contain resin. The sealing body 30 contains resin. Although not shown, the semiconductor device 20 includes a semiconductor element 40L.

FIG. 69 shows the semiconductor device 20 together with the heat exchanging portion 121 of the cooler 120 and the heat conducting member 130 such as heat dissipating gel. 69 shows a semiconductor module 140 including semiconductor devices 20, coolers 120, and heat conducting members 130. FIG. As an example, the semiconductor module 140 has a double-sided cooling structure in which the semiconductor device 20 is sandwiched between a pair of heat exchange portions 121 . The semiconductor device 20 is arranged side by side with the cooler 120 (heat exchange section 121) in the Z direction, which is a predetermined direction. The coolers 120 are arranged on both sides of the semiconductor device 20 .

The back metal bodies 53 and 63 are exposed from the sealing body 30 as back surfaces 50b and 60b of the substrates 50 and 60, respectively. One of the heat exchanging parts 121 of the cooler 120 is arranged to face the one surface 30a and the back surface 50b of the sealing body 30, and the other one of the heat exchanging parts 121 is arranged to face the back surface 30b and the back surface 60b of the sealing body 30. ing. Between the facing surfaces of the semiconductor device 20 and the heat exchanging portion 121, a heat conducting member 130 is arranged. The heat conducting member 130 is in close contact with the semiconductor device 20 and the heat exchanging portion 121 .

<Relationship between glass transition points>
Next, the relationship between the glass transition points of the sealing body 30 and the insulating base materials 51, 61 will be described with reference to FIGS. 69 and 70. FIG.

FIG. 70 is a diagram showing an example of the relationship between the glass transition point Tgs and the linear expansion coefficient αs of the sealing body 30 and the glass transition point Tgi and the linear expansion coefficient αi of the insulating substrates 51 and 61. FIG. In FIG. 70, the vertical axis indicates the linear expansion coefficient α, and the horizontal axis indicates the temperature. 70, the solid line indicates the coefficient of linear expansion αs of the sealing body 30, and the broken line indicates the coefficient of linear expansion αi of the insulating bases 51 and 61. In FIG. Among the coefficients of linear expansion αs, α1s indicates the coefficient of linear expansion at a temperature lower than the glass transition point Tgs, that is, the coefficient of linear expansion in the α1 region. α2s indicates the coefficient of linear expansion at a temperature higher than the glass transition point Tgs, that is, the coefficient of linear expansion in the α2 region. The same applies to the coefficient of linear expansion αi, where α1i indicates the coefficient of linear expansion in the α1 region and α2s indicates the coefficient of linear expansion in the α2 region.

As shown in FIG. 69, the sealing body 30 is in close contact with the semiconductor element 40 . The insulating bases 51 and 61 are thermally connected to the semiconductor element 40 via the bonding materials 100 , 101 and 102 and the surface metal bodies 52 and 62 . Therefore, when the semiconductor element 40 operates (during heat generation), the temperature at the peripheral position MP1 of the semiconductor element 40 in the sealing body 30 is higher than the temperature at the positions MP2 and MP3 of the insulating bases 51 and 61 overlapping the semiconductor element 40. is also expensive. Thus, the temperature of the sealing body 30 is higher than that of the insulating bases 51 and 61 .

When the temperature of the sealing body 30 exceeds the glass transition point Tgs, the Young's modulus decreases and the sealing function of the sealing body 30 deteriorates. Due to deterioration of the sealing function, thermal stress concentrates on the drain electrode 40D, the source electrode 40S, and their joints, which may cause cracks or the like. That is, there is a possibility that the connection reliability may be lowered. On the other hand, in this embodiment, as shown in FIG. 70, the relationship of Tgs>Tgi is satisfied.

<Relationship between coefficients of linear expansion>
Next, the relationship between the linear expansion coefficients of the sealing member 30 and the insulating base materials 51 and 61 will be described with reference to FIGS. 70 to 72. FIG. 71 and 72 are image diagrams showing warping of the semiconductor device 20. FIG. 71 and 72 show only the resin elements that constitute the semiconductor device 20, that is, only the sealing body 30 and the insulating bases 51 and 61. FIG.

When the semiconductor element 40 is in operation (during heat generation), if the linear expansion coefficient αs of the sealing body 30 is greater than the linear expansion coefficient αi of the insulating bases 51 and 61, the sealing is not performed as indicated by the dashed arrows in FIG. The expansion amount of the body 30 becomes larger than the expansion amount of the insulating base materials 51 and 61 . That is, the amount of expansion increases at the center in the Z direction and decreases at both ends. Therefore, it has a concave shape in which both ends in the Z direction are concave.

In this embodiment, as shown in FIG. 70, the relationship αi>αs is satisfied. Specifically, the α1 region satisfies the relationship α1i>α1s, and the α2 region satisfies the relationship α2i>α2s. As described above, since the relationship of Tgs>Tgi is satisfied, the relationship of αi>αs is satisfied throughout the operating temperature range. Therefore, when the semiconductor element 40 is in operation (during heat generation), the amount of expansion of the insulating bases 51 and 61 is greater than the amount of expansion of the sealing body 30, as indicated by the dashed arrows in FIG. That is, the amount of expansion is small at the center in the Z direction, and the amount of expansion is large at both ends. Therefore, as shown in FIG. 72, the shape of the semiconductor device 20 is convex at both ends in the Z direction.

<Summary of the sixth embodiment>
According to this embodiment, the glass transition point Tgs of the sealing body 30 is higher than the glass transition point Tgi of the insulating bases 51 and 61 . This makes it difficult for the temperature of the sealing body 30, which reaches a higher temperature during operation of the semiconductor element 40, to exceed the glass transition point Tgs. The temperature of the sealing body 30 does not exceed the glass transition point Tgs, or slightly exceeds it. Therefore, the Young's modulus of the sealing body 30 becomes small, and deterioration of the sealing function can be suppressed. Since deterioration of the sealing function can be suppressed, it is possible to suppress concentration of stress on the drain electrode 40D and the source electrode 40S, which are the main electrodes, and their junctions. That is, connection reliability can be improved.

The glass transition point Tgs of the sealing body 30 may be substantially equal to the glass transition point Tgi of the insulating substrates 51 and 61 . Compared to Tgs<Tgi, the temperature of the sealing body 30, which becomes higher during heat generation, is less likely to exceed the glass transition point Tgs.

Also, the coefficient of linear expansion αi of the insulating bases 51 and 61 is larger than the coefficient of linear expansion αs of the sealing body 30 . Thereby, the amount of expansion of the insulating bases 51 and 61 becomes larger than the amount of expansion of the sealing body 30 when the semiconductor element 40 operates. That is, the amount of expansion is small at the center in the Z direction, and the amount of expansion is large at both ends. As a result, the semiconductor device 20 is warped outwardly in the Z direction. Therefore, the facing distance between the semiconductor device 20 and the cooler 120 (121) is narrowed, and the thermal resistance between the semiconductor device 20 and the cooler 120 is reduced. Specifically, the thickness of the heat conducting member 130 is reduced, and the heat resistance is reduced. Since the heat of the semiconductor element 40 can be released efficiently, the semiconductor element 40 can be prevented from being overheated. That is, heat dissipation can be improved.

The coefficient of linear expansion αi of the insulating bases 51 and 61 may be substantially equal to the coefficient of linear expansion αs of the sealing body 30 . In this case, the amount of expansion is substantially equal at the center and both ends in the Z direction, and it is possible to suppress the concave shape at both ends in the Z direction. That is, it is possible to suppress an increase in thermal resistance between the semiconductor device 20 and the cooler 120 due to the concave shape.

By satisfying the relationships of Tgs≧Tgi and αi≧αs in this way, a highly reliable semiconductor device 20 can be provided.

<Modification>
Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50 and 60 has been shown, the present invention is not limited to this. It can also be applied to a semiconductor device 20 having a single-sided heat dissipation structure, which includes only a substrate 50 to which a drain electrode 40D (first main electrode) is connected.

Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been shown, the present invention is not limited to this. Only the semiconductor element 40 forming one of the arms may be provided. The semiconductor device 20 may include only one semiconductor element 40, for example.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, and modified examples.

(Seventh embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to suppress peeling of the sealing body, the surface metal body may have a predetermined structure as described in this embodiment.

<Semiconductor device>
FIG. 73 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. FIG. 73 corresponds to FIG.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the previous embodiment (see FIGS. 2 to 13). As shown in FIG. 73, the semiconductor device 20 includes two semiconductor elements 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. As shown in FIG. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40, through the bonding material 100. As shown in FIG. The surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40, through the bonding material 102. As shown in FIG. The sealing body 30 seals the semiconductor element 40 , the substrates 50 and 60 and the bonding materials 100 and 102 . Of the substrates 50 , 60 , the back metal bodies 53 , 63 are exposed from the sealing body 30 . Although not shown, the semiconductor device 20 includes two semiconductor elements 40L.

As shown in FIG. 73, the surface metal bodies 52 and 62 have roughened portions 527 and 627 and non-roughened portions 528 and 628 .

<Uneven oxide film>
Next, the uneven oxide film 520 forming the roughened portion 527 will be described in detail with reference to FIGS. 74 and 75. FIG. 74 is an enlarged view of region LXXIV in FIG. 73. FIG. FIG. 75 is a diagram showing a method of forming a roughened portion.

The surface metal bodies 52, 62 have uneven oxide films 520, 620, similarly to the configuration described in the modification of the fifth embodiment (see FIGS. 66 and 67). The textured oxide films 520 , 620 provide roughened portions 527 , 627 on the surfaces of the surface metal bodies 52 , 62 . The portions of the surfaces of the surface metal bodies 52 and 62 where the uneven oxide films 520 and 620 are not formed provide non-roughened portions 528 and 628 . In the following, the surface metal body 52 will be described as an example.

As shown in FIG. 74, the surface metal body 52 has a base material 521 and a plated film 522p and an uneven oxide film 520 provided on the surface of the base material 521 . The base material 521 constitutes the main portion of the surface metal body 52 . Base material 521 is formed using, for example, a Cu-based material. The plated film 522p is formed containing a material such as solder that has a higher wettability with respect to the bonding material 100 than the base material 521 does. The plated film 522p is formed on the entire upper surface 52a and the side surface 52c of the surface metal body 52 . The side surface 52 c is a surface that connects the upper surface 52 a and the lower surface 52 d facing the insulating base material 51 in the surface metal body 52 .

The uneven oxide film 520 is formed by irradiating the plated film 522p with a laser beam as described in the modified example of the fifth embodiment. In this embodiment, the upper surface 52a and the side surface 52c of the surface metal body 52 are irradiated with laser light. The roughened portion 527 provided by the uneven oxide film 520 is a portion of the upper surface 52a excluding the non-roughened portion 528. As shown in FIG. As an example, the roughened portion 527 is formed over the entire side surface 52c. At the end of the surface metal body 52, the roughened portion 527 is continuously provided from the side surface 52c to the upper surface 52a. The roughened portion 527 is provided on a portion of the upper surface 52a and the side surface 52c. The roughened portion 527 may be provided only on the edge of the upper surface 52a. The non-roughened portion 528 is provided on a portion of the upper surface 52a and includes at least an arrangement region (bonding region) of the bonding material 100 . The non-roughened portion 528 may be provided only in the bonding area, or may include areas other than the bonding area. The roughened portion 527 is provided on at least a portion of the side surface 52c. The roughened portion 527 may be provided only on a portion of the side surface 52c. For example, the roughened portion 527 may be provided only on a portion of the side surface 52 c so that the uneven oxide film 520 does not come into contact with the insulating base material 51 .

The plated film 522p of the present embodiment has a base film containing Ni (nickel) as a main component and an overcoat film containing Au (gold) as a main component. Specifically, an electroless Ni plating film containing P (phosphorus) is used as the base film. When the bonding material 100 is solder, of the plated film 522p exposed from the uneven oxide film 520, the overlying film (Au) of the portion in contact with the bonding material 100 diffuses into the solder during reflow. Of the plated film 522p, the overlying film (Au) of the portion where the uneven oxide film 520 is formed is removed by laser light irradiation when the uneven oxide film 520 is formed. The uneven oxide film 520 is an oxide film containing Ni as a main component. The uneven oxide film 520 is continuously provided at the end of the surface metal body 52 from the side surface 52c to the upper surface 52a.

As described in the modified example of the fifth embodiment, the uneven oxide film 520 is formed by melting, vaporizing, and vapor-depositing the surface layer portion of the plating film 522p by laser light irradiation. The uneven oxide film 520 is an oxide film derived from the plated film 522p. The uneven oxide film 520 is an oxide film of metal (Ni), which is the main component of the plating film 522p. Fine irregularities (roughened portions) are always formed on the surface of the irregular oxide film 520 . The uneven oxide film 520 has a continuous uneven surface.

In this embodiment, the surface metal body 52 has a larger area on the bottom surface 52d than on the top surface 52a. Therefore, as shown in FIG. 74, the lower surface 52d protrudes from the upper surface 52a. That is, at least a portion of the side surface 52c is located outside the upper surface 52a when viewed in plan in the Z direction. Therefore, as shown in FIG. 75, the uneven oxide film 520 can be formed on the upper surface 52a and the side surface 52c by irradiating the laser beam in the Z direction.

<Summary of the seventh embodiment>
In the configuration in which the plating film 522p is provided on the upper surface 52a and the side surface 52c of the surface metal body 52, thermal stress tends to cause peeling of the encapsulant 30 from the end portion of the surface metal body 52, that is, the side surface 52c. On the other hand, in the present embodiment, the roughened portion 527 is provided on the upper surface 52a and the side surface 52c except for the non-roughened portion 528. As shown in FIG. As a result, the adhesion of the side surface 52c of the surface metal body 52 to the sealing body 30 is higher than in a configuration in which the roughened portion 527 is not provided. Therefore, it is possible to suppress peeling of the sealing body 30 on the side surface 52 c of the surface metal body 52 . By suppressing the peeling, it is possible to suppress the concentration of thermal stress on the joining portion of the surface metal body 52 such as the joining material 100 . As a result, a highly reliable semiconductor device 20 can be provided.

The surface metal body 62 has the same configuration as the surface metal body 52 . The surface metal body 62 has a roughened portion 627 on the upper surface 62a except for the non-roughened portion 628 and the side surface 62c. As a result, peeling of the sealing body 30 on the side surface 62 c of the surface metal body 62 can be suppressed.

In this embodiment, the roughened portions 527, 627 are provided continuously over the side surfaces 52c, 62c and the upper surfaces 52a, 62a. As a result, it is possible to prevent the sealant 30 from peeling off in the vicinity of the end portions of the surface metal bodies 52 and 62 .

Roughening treatment for forming the roughened portions 527 and 627 can be roughening plating, sandblasting, chemical treatment, or the like. In this embodiment, laser roughening is employed. The uneven oxide films 520 and 620 are formed by irradiating the plated film with laser light. Surface metal bodies 52 and 62 have uneven oxide films 520 and 620 on roughened portions 527 and 627, respectively.

The surfaces of the uneven oxide films 520 and 620 have continuous unevenness, and the encapsulant 30 is entangled therewith to produce an anchor effect. Also, the contact area with the sealing body 30 increases. Therefore, the adhesion to the sealing body 30 can be enhanced in the roughened portions 527 and 627 . Moreover, the uneven oxide films 520 and 620 have lower wettability with respect to the bonding materials 100 and 102 than the plated film (the plated film 522p). Since the uneven oxide films 520 and 620 have fine unevenness on the surface, the contact area with the bonding materials 100 and 102 is small, and some of the bonding materials 100 and 102 become spherical due to surface tension. That is, the contact angle increases. Therefore, overflow of the bonding materials 100 and 102 can be suppressed. By adopting the uneven oxide films 520 and 620 in this way, it is possible to increase the adhesion to the sealing body 30 and to suppress the overflow of the bonding materials 100 and 102 from the bonding portion.

In this embodiment, the area of the surface metal bodies 52, 62 is larger at the lower surfaces 52d, 62d than at the upper surfaces 52a, 62a. The lower surfaces 52d and 62d protrude with respect to the upper surfaces 52a and 62a. Therefore, it is easy to physically roughen the side surfaces 52c and 62c from the Z direction. In the case of the above-described laser roughening, the uneven oxide films 520 and 620 can be formed not only on the upper surfaces 52a and 62a but also on the side surfaces 52c and 62c by irradiating the laser beam in the Z direction.

<Modification>
The side shapes of the surface metal bodies 52 and 62 are not limited to the above examples. When patterning the surface metal bodies 52 and 62 by pressing, etching, cutting, or the like, the side surfaces can be processed into a predetermined shape. FIG. 76 is a cross-sectional view showing a modification of the side shape. In FIG. 76, the surface metal body 52 is shown as an example, and the plated film 522p is omitted for the sake of convenience. Although illustration is omitted, a similar configuration can be adopted for the surface metal body 62 as well.

In the example shown in FIG. 76, the surface metal body 52 has side surfaces 52c substantially parallel to the Z direction. That is, the area of the surface metal body 52 is substantially constant in the Z direction. In order to physically roughen such surface metal body 52, for example, roughening may be performed separately for upper surface 52a and side surface 52c. In the case of laser roughening, the side surface 52c is irradiated with a laser beam from a direction different from the irradiation direction of the laser beam on the upper surface 52a, for example, from a direction inclined with respect to the Z direction. Thereby, the uneven oxide film 520 can be provided on the side surface 52c.

FIG. 77 is a sectional view showing a modification of the side shape, and corresponds to FIG. In the example shown in FIG. 77, the area of the surface metal body 52 perpendicular to the Z direction increases as it approaches the lower surface 52d. The side surface 52c has an R shape. In this case, the entire side surface 52c is located outside the upper surface 52a in plan view. Therefore, it is easier to physically roughen the side surface 52c from the Z direction, such as laser roughening, than the configuration shown in FIG.

FIG. 78 is a cross-sectional view showing a modification of the side shape, and corresponds to FIG. In the example shown in FIG. 78 as well, the area of the surface metal body 52 perpendicular to the Z direction increases as it approaches the lower surface 52d. The surface metal body 52 has, for example, a substantially trapezoidal shape on the ZY plane. Also in this case, since the entire area of the side surface 52c is positioned outside the upper surface 52a in plan view, the side surface 52c is likely to be physically roughened in the Z direction.

Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50 and 60 has been shown, the present invention is not limited to this. It can also be applied to a semiconductor device 20 having a single-sided heat dissipation structure, which includes only a substrate 50 to which a drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50 and 60 , the structure of the roughened portion including the side surfaces described above may be applied to only one of the substrates 50 and 60 . All sides 52, 62 are roughened

Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been shown, the present invention is not limited to this. Only the semiconductor element 40 forming one of the arms may be provided. The semiconductor device 20 may include only one semiconductor element 40, for example.

The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, and modification examples. is possible.

(Eighth embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to reduce the inductance, the thickness of the surface metal body and the distance between the wirings may satisfy a predetermined relationship, as described in this embodiment.

<Semiconductor device>
First, based on FIG. 79, the circuit pattern of the semiconductor device 20 according to the present embodiment, particularly the surface metal bodies 52 and 62 will be described. FIG. 79 is a cross-sectional view showing a semiconductor device 20 according to this embodiment. FIG. 79 illustrates part of the configuration described in the previous embodiment (see FIG. 8).

The semiconductor device 20 of this embodiment has a configuration similar to that described in the previous embodiment (see FIGS. 2 to 13). As shown in FIG. 79, the semiconductor device 20 includes a semiconductor element 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. As shown in FIG. A surface metal body 52 of the substrate 50 is electrically connected to a drain electrode 40</b>D that is the main electrode of the semiconductor element 40 . The surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. As shown in FIG. The sealing body 30 seals the semiconductor element 40 , the substrates 50 and 60 and the bonding materials 100 and 102 . Of the substrates 50 , 60 , the back metal bodies 53 , 63 are exposed from the sealing body 30 . Although not shown, the semiconductor device 20 includes a semiconductor element 40L forming the lower arm 9L.

<Relationship between wiring spacing and thickness>
Next, the relationship between wiring spacing and thickness will be described with reference to FIGS. 79 and 80. FIG. FIG. 80 is an enlarged view of region LXXX in FIG. In FIG. 80, only the substrate 60 is illustrated.

The surface metal bodies 52, 62 have inter-wiring gaps 52G, 62G as in the configuration described in the previous embodiment (see FIG. 65). As shown in FIGS. 79 and 80, the inter-wiring gap 62G separates the adjacent N wiring 64 and relay wiring 65 from each other. The inter-wiring gap 62G is a predetermined gap provided between wirings having different potentials in the surface metal body 62 .

As shown in FIG. 80, in this embodiment, the distance L10 between the N wiring 64 and the relay wiring 65 is equal to or less than the thickness T10 of the surface metal body 62 (L10≦T10). The interval L10 is the length of the inter-wiring gap 62G, that is, the inter-pattern distance between the N wiring 64 and the relay wiring 65 . 79 and 80, the distance L10 and the thickness T10 of the surface metal body 62 satisfy the relation of L10<T10. Although illustration is omitted, the substrate 50 having the surface metal body 52 has the same configuration as the substrate 60 . In the surface metal body 52, the distance L10 between the P wiring 54 and the relay wiring 55 is equal to or less than the thickness T10 of the surface metal body 52 (L10≤T10).

<Simulation result>
81 to 83 show the results of electromagnetic field simulation. FIG. 81 is a diagram summarizing simulation results as a relationship between length (interval, thickness) and inductance. Circles (○) of measurement points indicate the results of three levels of thickness T10 (0.3 mm, 1.5 mm, and 2.5 mm) when the interval L10 is fixed at 1.5 mm. A solid line in the figure indicates a change in inductance with a change in the thickness T10 when the interval L10 is fixed. Squares (□) of measurement points show the results for three levels (0.5 mm, 1.5 mm, and 2.5 mm) of the interval L10 when the thickness T10 is fixed at 1.5 mm. A dashed line in the figure indicates a change in inductance with a change in the interval L10 when the thickness T10 is fixed. The length of the horizontal axis shown in FIG. 81 indicates the length of the thickness T10 when the interval L10 is fixed, and indicates the length of the interval L10 when the thickness T10 is fixed.

FIG. 82 is a diagram showing a simulation result when L10>T10. FIG. 82 shows simulation results for the first condition C1 shown in FIG. 81, specifically, the interval L10=1.5 mm and the thickness T10=0.3 mm. FIG. 83 is a diagram showing a simulation result when L10<T10. FIG. 83 shows simulation results for the second condition C2 shown in FIG. 81, specifically, the interval L10=1.5 mm and the thickness T10=2.5 mm. In the simulation, conditions other than the interval L10 and the thickness T10 are common.

From the results shown in FIG. 81, it is clear that the inductance can be reduced within a range that satisfies the relationship of L10≦T10. In particular, it is clear that the inductance can be effectively reduced within a range that satisfies the relationship of L10<T10.

As shown in FIG. 82, in the case of L10>T10, the current is distributed in the width direction in the extended portion 641 of the N wiring 64, but flows biased toward the end portion side of the surface metal body 62 (substrate 60). . Therefore, the PN current loop (see FIG. 17) described in the previous embodiment is large. Since the current path flowing through the extended portion 421 is far from the relay wiring 65, the effect of canceling the magnetic flux due to the reverse component current is weakened. FIG. 82 shows that the inductance increases compared to when the relationship L10≦T10 is satisfied.

As shown in FIG. 83, when L10<T10, the current flows biased toward the end portion of the extension portion 641 on the side of the relay wiring 65 in the width direction. Therefore, the PN current loop is small. Since the current path flowing through the extended portion 421 is close to the relay wiring 65, the effect of canceling the magnetic flux due to the reverse component of the current is enhanced. FIG. 83 shows that the inductance becomes smaller than when the relationship of L10>T10 is satisfied.

<Summary of the eighth embodiment>
In this embodiment, the surface metal body 52 has the P wiring 54 which is the first wiring and the relay wiring 55 which is the second wiring having a potential different from that of the first wiring. The distance L10 between the P wiring 54 and the relay wiring 55 and the thickness T1 of the surface metal body 52 satisfy the relationship of L10≦T10. Similarly, the surface metal body 62 has an N wiring 64 which is a first wiring and a relay wiring 65 which is a second wiring having a potential different from that of the first wiring. The distance L10 between the N wiring 64 and the relay wiring 65 and the thickness T1 of the surface metal body 62 satisfy the relation of L10≦T10.

When the relationship L10≦T10 is satisfied, the distance between the adjacent wirings is narrow, so that the effect of canceling out the magnetic flux due to the current flowing through the first wiring and the magnetic flux due to the current flowing through the second wiring increases, and the inductance can be reduced. . Moreover, since the surface metal body is thick, the cross-sectional area of the current path is increased, and the inductance can be reduced. As described above, the semiconductor device 20 of the present embodiment can reduce the inductance. In particular, when the relationship of L1<T10 is satisfied, the above effect is enhanced, and the inductance can be reduced more effectively.

<Modification>
Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50 and 60 has been shown, the present invention is not limited to this. It can also be applied to a semiconductor device 20 having a single-sided heat dissipation structure, which includes only a substrate 50 to which a drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50 and 60, only one of the surface metal bodies 52 and 62 may satisfy the relationship of L10≦T10 described above. That is, in at least one substrate electrically connected to the main electrode of the semiconductor element, the surface metal body should have the first wiring and the second wiring and satisfy the relationship of L10≦T10. In addition, an example has been shown in which the relation L10≦T10 is satisfied in the entire opposing region between the N wiring 64 which is the first wiring and the relay wiring 65 which is the second wiring having a potential different from that of the first wiring. is not limited to At least a part of the opposing region should satisfy the relationship of L10≦T10. The same applies to the opposing region between the P wiring 54 which is the first wiring and the relay wiring 55 which is the second wiring having a potential different from that of the first wiring.

Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been shown, the present invention is not limited to this. Only the semiconductor element 40 forming one of the arms may be provided. The semiconductor device 20 may include only one semiconductor element 40, for example.

The configuration described in this embodiment is the same as that described in the first, second, third, fourth, fifth, sixth, seventh, and modification examples. Combinations with any of the configurations are possible.

(Ninth embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve heat dissipation and reliability, the side surface of the substrate may have a predetermined shape as described in this embodiment.

<Semiconductor device>
First, based on FIG. 84, the semiconductor device 20 according to this embodiment will be described. FIG. 84 is a cross-sectional view corresponding to FIG. In FIG. 84, illustration of the external connection terminal 90 is omitted for the sake of convenience.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the previous embodiment (see FIGS. 2 to 13). As shown in FIG. 84, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. As shown in FIG. A surface metal body 52 of the substrate 50 is electrically connected to a drain electrode 40</b>D that is the main electrode of the semiconductor element 40 . The surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. As shown in FIG. The sealing body 30 seals the semiconductor element 40 , the substrates 50 and 60 and the bonding materials 100 and 102 .

<Substrate>
Next, the substrates 50 and 60 will be described with reference to FIGS. 84 to 86. FIG. FIG. 85 is a plan view showing the center of the substrate. FIG. 85 corresponds to FIG. FIG. 86 is an enlarged view of the area LXXXVI indicated by the dashed line in FIG. Hereinafter, the terms “inner” and “outer” refer to relative positional relationships with the centers 50sc and 60sc of the substrates 50 and 60 in plan view in the Z direction as reference positions. The side closer to the center is the inner side, and the farther side is the outer side. FIG. 85 shows the center 50sc of the substrate 50 as an example. Although FIG. 84 is a sectional view, it shows the centers 50sc and 60sc for convenience of explanation.

In the substrates 50 and 60 of this embodiment, the insulating base materials 51 and 61 contain resin. The surface metal bodies 52 and 62 are arranged on the surfaces 51a and 61a of the insulating substrates 51 and 61, respectively. The surface metallization 52, 62 is patterned as described in previous embodiments. Thereby, the insulating base materials 51 and 61 have exposed portions 510 and 610 exposed from the surface metal bodies 52 and 62 . The exposed portion 510 of the insulating base material 51 that is the first exposed portion and the exposed portion 610 of the insulating base material 61 that is the second exposed portion at least partially overlap with each other in plan view in the Z direction. The exposed portions 510, 610 overlap. That is, at least part of the exposed portion 510 faces the exposed portion 610 in the Z direction.

The back metal bodies 53 and 63 are arranged on the back surfaces 51b and 61b of the insulating substrates 51 and 61, respectively. The back metal bodies 53 and 63 are exposed from the sealing body 30 . In the back metal bodies 53 and 63, the surfaces opposite to the surfaces 53a and 63a facing the insulating base material 51 are exposed surfaces 53b and 63b. The exposed surface 53 b is exposed substantially flush with the one surface 30 a of the sealing body 30 . The exposed surface 63b is exposed substantially flush with the rear surface 30b of the sealing body 30 . The exposed surfaces 53b, 63b form back surfaces 50b, 60b of the substrates 50, 60, respectively. The encapsulant 30 has a side surface 30e as a second surface continuous with one surface 30a as a first surface and a back surface 30b. The side surface 30e includes the side surfaces 30c and 30d in the Y direction and also the side surface in the X direction. Sides 30e include all sides. The side surface 30e, which is the second surface, is a tapered surface that is inclined with respect to the Z direction for die-cutting during molding. The side surface 30e has a draft angle. In the preceding embodiment, for the sake of convenience, the drawing is omitted. The side surface 30e has a bent portion near the center in the Z direction, and the closer the side surface 30a and the back surface 30b are from the bent portion, the closer the side surface 30e is to the semiconductor element 40 in plan view in the Z direction. That is, in plan view, the positional relationship is such that the bent portion is on the outside, and the one surface 30a and the back surface 30b are on the inside. Below, the one surface 30a and the back surface 30b of the sealing body 30 may be referred to as first surfaces 30a and 30b.

As shown in FIGS. 84 and 86, substrates 50 and 60 have laminates 500 and 600. FIG. A laminated body 500 is a laminated body having a two-layer structure of an insulating base material 51 and a back metal body 53 . Similarly, the laminated body 600 is a laminated body having a two-layer structure of an insulating base material 61 and a back metal body 63 . In the laminates 500 and 600, the side surfaces connecting the surfaces 51a and 61a of the insulating substrates 51 and 61 and the exposed surfaces 53b and 63b of the backside metal bodies 53 and 63 form a so-called V-cut shape. The side surfaces of the laminates 500 and 600 have central portions convex outward with respect to the upper surfaces 51a and 61a and the lower exposed surfaces 53b and 63b.

The side surfaces of the laminates 500 and 600 have first inclined portions 501 and 601 , second inclined portions 502 and 602 and intermediate portions 503 and 603 . First, the laminate 500 will be described.

The first inclined portion 501 is a portion within a predetermined range from the surface 51a. The first inclined portion 501 has a slope where the distance from the center 50sc is the shortest at the upper end on the surface 51a side in a plan view, and the lower end is farther from the upper end side. That is, the lower end of the first inclined portion 501 is located outside the upper end. As shown in FIG. 85 , the first inclined portion 501 is provided at the edge of the substrate 50 . The first inclined portion 501 has an annular shape so as to surround the surface metal body 52 .

In the present embodiment, the first inclined portion 501 has an inclination that the farther away from the surface 51a in the Z direction, the farther away from the center 50sc in plan view. That is, in the laminated body 500, in the upper portion including the first inclined portion 501, the surface 51a has the smallest area orthogonal to the Z direction, and the area increases with increasing distance from the surface 51a. The inclination of the first inclined portion 501 allows for manufacturing variations. The first inclined portion 501 macroscopically has the above-described inclination. The first inclined portion 501 is a tapered surface.

The second inclined portion 502 is a portion within a predetermined range from the exposed surface 53b. The second inclined portion 502 has a slope where the distance from the center 50sc in a plan view is the shortest at the lower end on the side of the exposed surface 53b, and the upper end is further away from the lower end. That is, the upper end of the second inclined portion 502 is located outside the lower end. The second inclined portion 502 is provided at the edge of the substrate 50, like the first inclined portion 501. As shown in FIG. The second inclined portion 502 has an annular shape so as to surround the back metal body 53 .

In the present embodiment, the second inclined portion 502 is inclined away from the center 50sc in plan view as the distance from the exposed surface 53b in the Z direction increases. In other words, in the laminate 500, in the lower portion including the second inclined portion 502, the exposed surface 53b has the smallest area, and the area increases with distance from the exposed surface 53b. The inclination of the second inclined portion 502 allows for manufacturing variations. The second inclined portion 502 macroscopically has the above-described inclination. The second inclined portion 502 is a tapered surface. If the first inclined portion 501 is forward tapered, the second inclined portion 502 is reverse tapered.

The intermediate portion 503 continues to the first inclined portion 501 and the second inclined portion 502 . The intermediate portion 503 is a portion connecting the first inclined portion 501 and the second inclined portion 502 and has a predetermined length in the Z direction. The intermediate portion 503 is the vertex portion of the side surface of the laminate 500 . The sides of the stack 500 are furthest from the center 50sc at the intermediate portion 503 . The intermediate portion 503 is the outermost portion of the laminate 500 in plan view. The laminate 500 has the largest area perpendicular to the Z direction in the intermediate portion 503 . In the intermediate portion 503, the area of the laminate 500 is substantially constant. The distance between the first inclined portion 501 and the center 50sc in a plan view decreases as the distance from the intermediate portion 503 increases. The distance between the second inclined portion 502 and the center 50sc in a plan view decreases as the distance from the intermediate portion 503 increases.

The layered body 600 has the same configuration as the layered body 500 . The first inclined portion 601 is a portion within a predetermined range from the surface 61a. The first inclined portion 601 has a slope where the distance from the center 60sc is the shortest at the upper end on the surface 61a side in a plan view, and the lower end is farther from the upper end. That is, the lower end of the first inclined portion 601 is located outside the upper end. The first inclined portion 601 is provided at the edge of the substrate 60 . The first inclined portion 601 has an annular shape so as to surround the surface metal body 62 .

In the present embodiment, the first inclined portion 601 has an inclination such that the farther away from the surface 61a in the Z direction, the farther away from the center 60sc in plan view. In other words, in the laminate 600, the area perpendicular to the Z direction on the surface 61a is the smallest in the upper portion including the first inclined portion 601, and the area increases with increasing distance from the surface 61a. The inclination of the first inclined portion 601 allows for manufacturing variations. The first inclined portion 601 macroscopically has the above-described inclination. The first inclined portion 601 is a tapered surface.

The second inclined portion 602 is a portion within a predetermined range from the exposed surface 63b. The second inclined portion 602 has the closest distance to the center 60sc in a plan view at the lower end on the side of the exposed surface 63b, and the upper end is inclined farther from the lower end. That is, the upper end of the second inclined portion 602 is positioned outside the lower end. The second slanted portion 602 is provided at the edge of the substrate 60 like the first slanted portion 501 . The second inclined portion 602 is annular so as to surround the back metal body 63 .

In the present embodiment, the second inclined portion 602 is inclined away from the center 60sc in plan view as the distance from the exposed surface 63b in the Z direction increases. That is, in the laminate 600, in the lower portion including the second inclined portion 602, the exposed surface 63b has the smallest area, and the area increases with distance from the exposed surface 63b. The slope of the second sloped portion 602 may allow for manufacturing variations. The second inclined portion 602 macroscopically has the above-described inclination. The second inclined portion 602 is a tapered surface. If the first inclined portion 601 is forward tapered, the second inclined portion 602 is reverse tapered.

The intermediate portion 603 continues to the first inclined portion 601 and the second inclined portion 602 . The intermediate portion 603 is a portion connecting the first inclined portion 601 and the second inclined portion 602 and has a predetermined length in the Z direction. The intermediate portion 603 is the vertex portion of the side surface of the laminate 600 . The sides of the laminate 600 are furthest from the center 60sc at the intermediate portion 603 . The intermediate portion 603 is the outermost portion of the laminate 600 in plan view. The laminate 600 has the largest area in the intermediate portion 603 . In the intermediate portion 603, the area of the laminate 600 is substantially constant. The distance between the first inclined portion 601 and the center 60sc in a plan view decreases as the distance from the intermediate portion 603 increases. The distance between the second inclined portion 602 and the center 60sc in a plan view decreases as the distance from the intermediate portion 603 increases.

<Dimensions and angles>
Next, the dimensions and angles of the laminates 500 and 600 will be described with reference to FIG. FIG. 87 is a diagram corresponding to FIG. 86, showing dimensions and angles. The laminate 500 will be described below as an example.

A length L11 shown in FIG. 87 is the length of the first inclined portion 501 in plan view, that is, the width of the annular first inclined portion 501 . The length L12 is the length of the second inclined portion 502 in plan view, that is, the width of the annular second inclined portion 502 . The length L21 is the length of the first inclined portion 501 in the Z direction, that is, the height of the first inclined portion 501 . The length L22 is the length of the second inclined portion 502 in the Z direction, that is, the height of the second inclined portion 502 . A length L23 is the length of the intermediate portion 503 in the Z direction, that is, the height of the intermediate portion 503 . The length L24 is the length of the insulating base 51 in the Z direction, that is, the thickness of the insulating base 51 . The length L25 is the length of the back metal body 53 in the Z direction, that is, the thickness of the back metal body 53 .

The angle R1 is the inclination angle of the back metal body 53 with respect to the Z direction, which is the plate thickness direction of the semiconductor element 40, at the first inclined portion 501. As shown in FIG. The angle R2 is the inclination angle of the back metal body 53 with respect to the Z direction at the second inclined portion 502 . An angle R3 is the inclination angle of the insulating base material 51 with respect to the Z direction at the first inclined portion 501 . An angle R4 is an inclination angle of the second inclined portion 502 with respect to the exposed surface 53b of the back metal body 53. As shown in FIG. An angle R5 is an inclination angle of the side surface 30e with respect to the one surface 30a of the sealing body 30. As shown in FIG.

As shown in FIG. 87, in this embodiment, the length of the second inclined portion 502 is shorter than the length of the first inclined portion 501 . That is, the relationship of L11>L12 is satisfied. The angle R1 satisfies the relationship of 0°<R1≦45°, and the angle R2 satisfies the relationship of 0°<R2<45°. The closer the angle R1 is to 45°, the more effectively the heat generated by the semiconductor element 40 can be diffused. The closer the angle R2 is to 45°, the smaller the thermal resistance can be, as will be described later.

Furthermore, a first inclined portion 501 is provided from the insulating base material 51 to the back metal body 53 , and a second inclined portion 502 is provided on the back metal body 53 . That is, the relationships of L21>L24 and L22<L25 are satisfied. In the configuration including the intermediate portion 503 , the intermediate portion 503 is provided on the back metal body 53 . That is, it satisfies the relationship of L24<(L24+L25-L23)/2.

Furthermore, in the configuration in which the first inclined portion 501 is provided from the insulating base material 51 to the back metal body 53 , the inclination angle of the back metal body 53 and the inclination angle of the insulating base material 51 are substantially equal. That is, the relationship of R1=R3 is satisfied.

Furthermore, the inclination angle of the second inclined portion 502 with respect to the exposed surface 53b of the back metal body 53 is smaller than the inclination angle of the side surface 30e (second surface) with respect to the one surface 30a (first surface) of the sealing body 30 . That is, it satisfies the relationship of R4<R5. Although description is omitted, the laminate 600 also has the same configuration as the laminate 500 .

<Method for manufacturing laminate>
Next, an example of a method for manufacturing the laminate 500 described above will be described. First, a mother substrate having a two-layer structure of an insulating base material 51 containing resin and a back surface metal body 53 is formed. Next, a blade is used to simultaneously cut (V-cut) the surface 51a and the exposed surface 53b of the insulating base material 51 from both sides. In this cutting, the first inclined portion 501 and the second inclined portion 502 are formed without completely separating the mother substrate. Adjacent laminates 500 on the mother substrate are connected at an intermediate portion 503 . By separating (separating) adjacent laminates 500 at intermediate portions 503, laminates 500 having V-cut side surfaces can be obtained.

FIG. 88 is a side view of a laminate 500 obtained by the manufacturing method described above. By cutting (cutting) using a blade, the first inclined portion 501 has a cut mark 501a along the circumferential direction. Similarly, the second inclined portion 502 has cutting marks 502a along the circumferential direction. In order to separate adjacent laminates 500 at the intermediate portion 503, the intermediate portion 503 has uneven portions 503a. Although description is omitted, the laminated body 600 is also formed by the same method as the laminated body 500 .

<Summary of the ninth embodiment>
In this embodiment, the side surfaces of the laminates 500 and 600 have first inclined portions 501 and 601 and second inclined portions 502 and 602 . That is, the side surface has a curved shape (substantially V-shaped). As a result, even if delamination that occurs in the sealing body 30 starting from the interface with the exposed surfaces 53b and 63b and progresses along the second inclined portions 502 and 602, the bending shape causes the peeling to proceed to the first inclined portions 501 and 601. progress can be restrained. Therefore, it is possible to suppress the progress of delamination to the surface metal bodies 52 and 62, the semiconductor element 40, and the joints between the surface metal bodies 52 and 62 and the semiconductor element 40 and the like. In other words, it is possible to prevent the thermal stress from concentrating on the surface metal bodies 52 and 62, the semiconductor element 40, and the like, thereby reducing the connection reliability and the like. Therefore, reliability can be ensured.

Since the second inclined portions 502 and 602 are provided, it is possible to prevent the backside metal bodies 53 and 63 from coming off (dropping) from the sealing body 30 when the peeling described above occurs.

Heat ideally spreads at an angle of 45 degrees. In this embodiment, the laminates 500 and 600 have first inclined portions 501 and 601 on the semiconductor element 40 side in the Z direction. As a result, the heat generated by the semiconductor element 40 is diffused above the bent portion, that is, in the portion corresponding to the first inclined portions 501 and 601 . On the other hand, since the second inclined portions 502 and 602 are provided, the heat transfer paths in the portions corresponding to the second inclined portions 502 and 602 are narrower than the heat transfer paths in the portions corresponding to the first inclined portions 501 and 601 . Narrow heat transfer paths increase thermal resistance. In this embodiment, the length L12 of the second inclined portions 502 and 602 is made shorter than the length L11 of the first inclined portions 501 and 601 (L11>L12). As a result, the Z-direction length L22 of the second inclined portions 502 and 602 can be shortened compared to the configuration satisfying L11≦L12, and thus the heat resistance below the bent portion can be reduced. That is, the heat diffused in the upper portions of the laminates 500 and 600 can be efficiently radiated from the exposed surfaces 53b and 63b. As described above, the semiconductor device 20 of the present embodiment can ensure reliability while improving heat dissipation.

The first inclined portions 501 , 601 may be provided on the insulating substrates 51 , 61 and the second inclined portions 502 , 602 may be provided on the back metal bodies 53 , 63 . The first inclined portions 501 , 601 may be provided on the insulating substrates 51 , 61 and the second inclined portions 502 , 602 may be provided over the insulating substrates 51 , 61 and the backside metal bodies 53 , 63 . In this embodiment, the first inclined portions 501 and 601 are provided over the insulating substrates 51 and 61 and the back metal bodies 53 and 63 , and the second inclined portions 502 and 602 are provided on the back metal bodies 53 and 63 . In other words, the bent portions exist within the back metal bodies 53 and 63 . Therefore, even if delamination that occurs in the sealing body 30 from the interfaces with the exposed surfaces 53b and 63b and progresses along the second inclined portions 502 and 602, the delamination progresses to the interfaces with the insulating base materials 51 and 61. can be suppressed. As a result, it is possible to prevent the thermal stress from concentrating on the insulating bases 51 and 61 and lowering the insulation reliability. That is, reliability can be further improved.

A configuration in which the first inclined portions 501 and 601 and the second inclined portions 502 and 602 are connected may be adopted. In this embodiment, intermediate portions 503 and 603 are provided between the first inclined portions 501 and 601 and the second inclined portions 502 and 602 . In this configuration, the intermediate portions 503, 603 form the bent portion. By providing the intermediate portions 503 and 603, as described above, both the surfaces 51a and 61a of the insulating substrates 51 and 61 and the exposed surfaces 53b and 63b of the back metal bodies 53 and 63 are simultaneously cut (cut). can also avoid blade-to-blade contact. In addition, since the intermediate portions 503 and 603 are provided on the back metal bodies 53 and 63, it is possible to prevent the delamination from progressing to the interfaces with the insulating base materials 51 and 61, as described above.

In the configuration in which the first inclined portions 501 and 601 are provided from the insulating base materials 51 and 61 to the back metal bodies 53 and 63, the angle of inclination R1 of the back metal bodies 53 and 63 and the angle of inclination R3 of the insulating base materials 51 and 61 are can be different. For example, if R1<R3, the thermal stress concentrates on the ends of the insulating substrates 51 and 61 containing resin, which may reduce the insulating performance. In the case of R1>R3, thermal stress concentrates on the interface between the insulating base material 51, 61 and the backside metal body 53, 63, which may cause interfacial peeling. In the present embodiment, the tilt angle R1 and the tilt angle R3 are made substantially equal (R1=R3). That is, in the first inclined portions 501 and 601, the inclined surfaces of the insulating substrates 51 and 61 and the inclined surfaces of the back metal bodies 53 and 63 are substantially flush with each other. The inclined surfaces of the insulating substrates 51 and 61 and the inclined surfaces of the back metal bodies 53 and 63 are continuous to form one flat surface. As a result, concentration of thermal stress on the triple points of the sealing body 30 , the insulating bases 51 and 61 , and the backside metal bodies 53 and 63 can be suppressed.

The inclination angle R4 of the second inclined portions 502 and 602 with respect to the exposed surfaces 53b and 63b may be greater than or equal to the inclination angle R5 of the side surface 30e (second surface) with respect to the first surfaces 30a and 30b of the sealing body 30. In this embodiment, the tilt angle R4 is made smaller than the tilt angle R5 (R4<R5). As described in the preceding embodiment (for example, see FIG. 72), semiconductor device 20 warps when semiconductor element 40 heats up. As described above, when a configuration having a warped shape with high heat dissipation is adopted, peeling is likely to occur at the interface between the back metal bodies 53 and 63 and the sealing body 30 due to the convex warp in the Z direction. By adopting a configuration that satisfies the relationship of R4<R5, it is possible to prevent the back metal bodies 53 and 63 from coming off from the sealing body 30 even if peeling occurs.

In this embodiment, the exposed portion 510 of the insulating base material 51, which is the first exposed portion, and the exposed portion 610 of the insulating base material 61, which is the second exposed portion, overlap each other in plan view in the Z direction. As a result, the imbalance in arrangement between the surface metal bodies 52 of the substrate 50 as the first substrate and the surface metal bodies 62 of the substrate 60 as the second substrate is suppressed, and the imbalance in the warpage of the semiconductor device 20 is suppressed. be able to. It is possible to prevent interfacial peeling between the back metal bodies 53 and 63 and the sealing body 30 from easily occurring on the side where deformation is large due to uneven warpage.

In this embodiment, the first inclined portion 501 and the second inclined portion 502 have cutting marks 501a and 502a along the circumferential direction. The presence of cutting marks 501a and 502a produces an anchor effect, and the adhesion to the sealing body 30 is enhanced. This can prevent the sealing body 30 from peeling off from the laminates 500 and 600 . It should be noted that only one of the first inclined portion 501 and the second inclined portion 502 may be provided with cutting marks along the circumferential direction. In the present embodiment, since the intermediate portion 503 also has the uneven portion 503a, it can be expected that peeling will be suppressed by the anchor effect.

<Modification>
Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50 and 60 has been shown, the present invention is not limited to this. It can also be applied to a semiconductor device 20 having a single-sided heat dissipation structure, which includes only a substrate 50 to which a drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50 and 60, the above-described structure (V-cut shape) may be applied to only one of the substrates 50 and 60. FIG.

Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been shown, the present invention is not limited to this. Only the semiconductor element 40 forming one of the arms may be provided. The semiconductor device 20 may include only one semiconductor element 40, for example.

The configurations described in this embodiment are the first, second, third, fourth, fifth, sixth, seventh, eighth, and Combinations with any of the configurations described in the variants are possible.

(Tenth embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve the connection reliability, the sintered members, which are the bonding materials, may be arranged in a predetermined manner as described in this embodiment.

<Semiconductor device>
First, based on FIG. 89, the semiconductor device 20 according to this embodiment will be described. FIG. 89 is a cross-sectional view corresponding to FIG. In FIG. 89, illustration of the external connection terminal 90 is omitted for the sake of convenience.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the previous embodiment (see FIGS. 2 to 13). As shown in FIG. 89, a semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 as wiring members arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. I have. The surface metal body 52 of the substrate 50, which is the first wiring member, is connected to the drain electrode 40D, which is the first main electrode of the semiconductor element 40. As shown in FIG. The surface metal body 62 of the substrate 60, which is the second wiring member, is connected to the source electrode 40S, which is the second main electrode of the semiconductor element 40, via the conductive spacer 70 which is the second wiring member. The encapsulant 30 encapsulates the semiconductor element 40 , the substrates 50 and 60 and the conductive spacers 70 . The source electrode 40S and the conductive spacer 70 are joined by a sintered member 101A, which is a joining material 101. As shown in FIG.

<Semiconductor element>
Next, the semiconductor element 40 will be described with reference to FIGS. 90 and 91. FIG. FIG. 90 is a plan view showing the semiconductor element 40 (40H). FIG. 91 is an enlarged view of region XCI in FIG. 91 is a cross-sectional view corresponding to the XCI-XCI line of FIG. 90. FIG. Although the semiconductor element 40H is shown as an example in FIG. 91, the semiconductor element 40L also has the same configuration, so that it will be described as the semiconductor element 40 below.

The semiconductor element 40 has a semiconductor substrate 41 on which switching elements are formed, as described above. The semiconductor substrate 41 has a substantially rectangular planar shape. A drain electrode is provided on one surface of the semiconductor substrate 41 , and a source electrode 40S and a pad 40P are provided on the back surface of the semiconductor substrate 41 . The source electrode 40S has a multilayer structure. The source electrode 40S has a base electrode 42 and a connection electrode 43 . The pad 40P also has the same configuration as the source electrode 40S.

The semiconductor element 40 further has a protective film 44 . The protective film 44 is an insulating film provided on the back surface of the semiconductor substrate 41 so as to cover the peripheral portion of the source electrode 40S. As a material for the insulating film, for example, polyimide, silicon nitride film, or the like can be used. The protective film 44 has an opening 440 that defines a connection region in the source electrode 40S. The opening 440 exposes the source electrode 40S for bonding. The protective film 44 has an opening 441 that defines a connection region in the pad 40P. Both of the openings 440 and 441 are through holes penetrating the protective film 44 in the Z direction. A portion of the source electrode 40S (connection electrode 43) exposed through the opening 440 of the protective film 44 forms a joint with the sintered member 101A.

The protective film 44 of this embodiment is made of polyimide. The protective film 44 covers a later-described peripheral edge portion 420 of the base electrode 42 . Protective film 44 is not provided, for example, in a scribe region within a predetermined range from the outer peripheral edge of semiconductor substrate 41 . The opening shape of the opening 440, that is, the inner peripheral surface 442 of the protective film 44 defining the opening 440 has a substantially rectangular planar shape. The inner peripheral surface 442 may be referred to as an inner peripheral end or an open end.

The base electrode 42 is a metal layer formed adjacent to the semiconductor substrate 41 in the multilayer source electrode 40S. The base electrode 42 is sometimes called a lower electrode, a lower layer electrode, a wiring electrode, a base layer, a first metal layer, or the like. The underlying electrode 42 is connected to the back surface of the semiconductor substrate 41 . Base electrode 42 is formed using a material containing Al (aluminum) as a main component, for example. In this embodiment, AlSi-based alloys such as AlSi and AlSiCu are used as materials.

The base electrode 42 encloses an element region (active region) (not shown) of the semiconductor substrate 41 in a plan view, and extends to an outer peripheral region surrounding the element region. A peripheral edge portion 420 of the underlying electrode 42 has a substantially rectangular planar annular shape. The peripheral portion 420 is covered with the protective film 44 .

The connection electrode 43 is stacked on the base electrode 42 . The connection electrode 43 is also called an upper electrode, an upper electrode, an upper electrode, an upper layer, or a second metal layer. The connection electrode 43 contains at least noble metals such as Au (gold), Ag (silver), Pt (platinum), and Pd (palladium) for bonding with the sintered member 101A. The connection electrode 43 may contain a base metal as well as a noble metal.

The connection electrode 43 of this embodiment contains Ni (nickel). Ni is harder than the Al alloy forming the base electrode 42 . The connection electrode 43 contains Ni and a noble metal such as Au or Ag. Connection electrode 43 is formed in multiple layers by, for example, a plating method. At least part of the noble metal of the connection electrode 43 diffuses into the sintered member 101A during bonding.

The connection electrode 43 is stacked on the base electrode 42 in the opening 440 of the protective film 44 . The outer peripheral end of the connection electrode 43 is in contact with the inner peripheral surface 442 of the protective film 44 over the entire circumference.

<Joint structure>
Next, the junction structure of the semiconductor element 40 will be described with reference to FIGS. 90 to 92. FIG. In FIG. 90, the outer peripheral edge of the sintered member 101A is indicated by a dashed line, and the outer peripheral edge of the conductive spacer 70 is indicated by a two-dot chain line. FIG. 92 is a cross-sectional view showing the arrangement of the sintered member 101A. FIG. 92 corresponds to FIG. Hereinafter, the terms “inner” and “outer” indicate relative positional relationships with the center of the semiconductor element 40 as a reference position. The side closer to the center is the inner side, and the farther side is the outer side.

In this embodiment, the substrate 60 and the conductive spacer 70 are wiring members (second wiring members) electrically connected to the source electrode 40S. As shown in FIGS. 90 and 91, the sintered member 101A is interposed between the source electrode 40S of the semiconductor element 40 and the conductive spacer . The sintered member 101A joins the source electrode 40S and the conductive spacer 70 together.

The sintered member 101A is made of Ag or Cu. The sintered member 101A is a sintered body of Ag particles or Cu particles. The sintered member 101A can be joined at a lower temperature than solder. As shown in FIG. 92, the sintered member 101A is arranged with a predetermined distance L30 from the inner peripheral surface 442 of the protective film 44. As shown in FIG. As shown in FIGS. 90 to 92, the sintered member 101A is arranged inside the inner peripheral surface 442. As shown in FIGS. The sintered member 101A has, for example, a substantially rectangular planar shape. The outer peripheral edge of the sintered member 101A is not in contact with the protective film 44 over the entire circumference. That is, the inner peripheral surface 442 of the protective film 44 includes the sintered member 101A in plan view.

The conductive spacer 70 has a metal film (not shown) on the joint surface with the sintered member 101A. The metal film contains at least a noble metal, similar to the connection electrode 43 . In this embodiment, the metal film is a plated film containing Ni and a noble metal such as Au or Ag.

As shown in FIGS. 90-92, the conductive spacer 70 is arranged inside the inner peripheral surface 442 . The conductive spacer 70 has, for example, a substantially rectangular planar shape. The outer peripheral edge of the conductive spacer 70 is arranged outside or substantially aligned with the outer peripheral edge of the sintered member 101A in plan view. In other words, the conductive spacer 70 is arranged so as to enclose the sintered member 101A or substantially match the sintered member 101A in plan view. In this embodiment, the conductive spacer 70 encloses the sintered member 101A.

<Joining method>
Next, based on FIG. 93, a method for forming the above-described joining structure, that is, a joining method will be described. FIG. 93 is a cross-sectional view showing a joining method. FIG. 93 corresponds to FIG.

In this embodiment, a sintered sheet 105 is used to form the sintered member 101A. The sintered sheet 105 is sometimes referred to as a sintered film. The sintered sheet 105 contains Ag or Cu. As shown in FIG. 93, the sintered sheet 105 is arranged on the source electrode 40S (connection electrode 43) of the semiconductor element 40. As shown in FIG. The sintered sheet 105 has a predetermined size that does not come into contact with the protective film 44 in plan view.

A conductive spacer 70 is then placed on the sintered sheet 105 . Then, while heating, pressure is applied from the conductive spacer 70 side by a pressure device (not shown). As a result, the sintered sheet 105 is expanded between the facing surfaces of the connection electrode 43 and the conductive spacer 70 to become thin and sintered to form the sintered member 101A. The size of the sintered sheet 105 is determined so that the sintered member 101A has the above-described predetermined positional relationship with respect to the inner peripheral surface 442 of the protective film 44 and the conductive spacer 70 .

<Simulation result>
FIG. 94 shows the results of thermal stress simulation. In this simulation, the strain amplitude generated in the base electrode 42 was measured in a power cycle test in which room temperature and 150° C. were alternately repeated. FIG. 94 shows the relationship between the distance L30 and the strain amplitude. In FIG. 94, the distance L30 of 0 (zero) corresponds to the inner peripheral surface 442 of the protective film 44 in plan view. A negative numerical value of the distance L30 indicates an inward distance from the inner peripheral surface 442, and a positive numerical value indicates an outward numerical value.

As shown in FIG. 94, it has been clarified that the strain amplitude generated in the base electrode 42 is almost 0 (zero) when the distance L30 is 5 μm or more. In this embodiment, based on this knowledge, the predetermined distance L30 is set to 5 μm.

<Summary of the tenth embodiment>
FIG. 95 shows a connection structure using solder 101B as the bonding material 101. FIG. FIG. 95 corresponds to FIG. In the case of solder 101B, the solder 101B is reflowed for joining. At the time of joining, the melted solder 101B wets and spreads over the surface of the connection electrode 43 . Therefore, as indicated by a dashed line in FIG. 95, a triple point of the sealing body 30, the source electrode 40S (connection electrode 43), and the solder 101B (bonding material 101) is formed. Thermal stress based on the difference in coefficient of linear expansion concentrates at the triple point. The thermal stress concentrates on the portion of the base electrode 42 immediately below the outer peripheral edge of the connection electrode 43 . Therefore, cracks may occur in the base electrode 42 , and the semiconductor substrate 41 may be damaged.

In this embodiment, a sintered member 101A is used instead of the solder 101B. The sintered member 101A is formed by heating at a temperature lower than the melting point. Unlike the solder 101B, the sintered member 101A does not melt during bonding. The sintered member 101A has lower wettability with respect to the connection electrodes 43 and the conductive spacers 70 than the solder 101B. Therefore, unlike the solder 101B, the sintered member 101A does not wet and spread on the surfaces of the connection electrodes 43 and the conductive spacers 70 during bonding.

Since the sintered member 101A can be easily held at a predetermined position, the sintered member 101A can be arranged with a predetermined distance L30 from the inner peripheral surface 442 of the protective film 44 . Thereby, the triple point of the sealing body 30, the source electrode 40S (connection electrode 43), and the sintered member 101A (joining material 101) is not formed. Therefore, it is possible to provide the semiconductor device 20 that suppresses the concentration of thermal stress and has high connection reliability. Also, the sintered member 101A has a higher thermal conductivity than the solder 101B. Thereby, heat dissipation can also be improved.

The distance L30 is not particularly limited. The sintered member 101A should be separated from at least the inner peripheral surface 442 . In this embodiment, the distance L30 between the sintered member 101A and the inner peripheral surface 442 of the protective film 44 is set to 5 μm or more. According to this, the strain amplitude of the base electrode 42 due to thermal stress can be effectively reduced. That is, connection reliability can be further improved.

In plan view, the positional relationship between the conductive spacer 70 and the sintered member 101A is not particularly limited. For example, the sintered member 101A may protrude from the conductive spacer 70 in plan view. As described above, the sintered member 101A is formed by sintering Ag particles or Cu particles by heating and pressing. Since the portion protruding from the conductive spacer 70 is not pressurized, it remains without being sintered and may drop as a conductive foreign substance. That is, there is a possibility that a short circuit or the like may occur.

In this embodiment, in plan view, the inner peripheral surface 442 of the protective film 44 includes the conductive spacer 70, and the conductive spacer 70 coincides with the sintered member 101A or includes the sintered member 101A. Thereby, pressure can be applied to the entire area of the sintered member 101A (sintered sheet 105) before sintering through the conductive spacer 70. FIG. Therefore, while avoiding contact between the sintered member 101A and the protective film 44, it is possible to suppress the occurrence of sintered residues.

<Modification>
Although the example of using the sintered sheet 105 to form the sintered member 101A is shown, it is not limited to this. For example, a sintering paste in which Ag particles or Cu particles are dispersed in a solvent may be used. A sintered sheet 105 is easier to hold in place than a sintered paste.

Although an example in which the second wiring member to which the source electrode 40S is connected includes the substrate 60, which is a wiring board, and the conductive spacer 70, the present invention is not limited to this. Instead of the conductive spacer 70, the surface metal body 62 may be provided with a convex portion. In other words, the second wiring member may have only the substrate 60 without the conductive spacer 70 . In this case, the sintered member 101A is interposed between the tip surface of the projection of the surface metal body 62 and the source electrode 40S (connection electrode 43).

Although an example of the substrate 50 is shown as the first wiring member, the present invention is not limited to this. A metal plate (lead frame) may be employed instead of the substrate 50 . Although an example of the substrate 60 is shown as the second wiring member, the present invention is not limited to this. A metal plate (lead frame) may be employed instead of the substrate 60 . The second wiring member may have the metal plate and the conductive spacer 70, or instead of the conductive spacer 70, the metal plate may be provided with a convex portion.

Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been shown, the present invention is not limited to this. Only the semiconductor element 40 forming one of the arms may be provided. The semiconductor device 20 may include only one semiconductor element 40, for example.

The configurations described in this embodiment are the first, second, third, fourth, fifth, sixth, seventh, eighth, and third embodiments. Any of the configurations described in the nine embodiments and modifications can be combined.

(Eleventh embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve heat dissipation, a sintered member may be used in the joint between the main electrode and the wiring member as described in this embodiment.

<Semiconductor device>
First, based on FIG. 96, the semiconductor device 20 according to this embodiment will be described. FIG. 96 is a cross-sectional view corresponding to FIG. In FIG. 96, illustration of the external connection terminals 90 is omitted for convenience.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the previous embodiment (see FIGS. 2 to 13). As shown in FIG. 96, a semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 as wiring members arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. I have. A surface metal body 52 of the substrate 50 is connected to a drain electrode 40</b>D, which is the first main electrode of the semiconductor element 40 . The surface metal body 62 of the substrate 60 is connected to the source electrode 40S, which is the second main electrode of the semiconductor element 40, through the conductive spacer 70. As shown in FIG. The encapsulant 30 encapsulates the semiconductor element 40 , the substrates 50 and 60 and the conductive spacers 70 . The drain electrode 40</b>D and the surface metal body 52 of the substrate 50 are joined by a sintered member 100</b>A, which is a joining material 100 .

<Arrangement of Sintered Member and Concavo-convex Oxide Film>
Next, the arrangement of the sintered member 100A and the uneven oxide film 520 with respect to the semiconductor element 40 will be described with reference to FIGS. 97 to 99. FIG. 97 is an enlarged view of region XCVII in FIG. 96. FIG. 98 is a plan view showing the positional relationship among the semiconductor element 40, the sintered member 100A, and the uneven oxide film 520. FIG. FIG. 99 is an enlarged view of area XCVIX in FIG.

As shown in FIGS. 97 and 98, the upper surface 52a of the surface metal body 52 has a mounting portion 529a, an outer peripheral portion 529b, and an intermediate portion 529c. The uneven oxide film 520 is not provided on the mounting portion 529a, but is provided on the outer peripheral portion 529b and the intermediate portion 529c.

The mounting portion 529a includes a portion that overlaps with the semiconductor element 40 (drain electrode 40D) in plan view in the Z direction, and is a portion to which the drain electrode 40D is joined via the sintered member 100A. The outer peripheral portion 529b is a portion surrounding the semiconductor device 40 including a portion outside the outer peripheral edge 402 of the semiconductor device 40 in plan view. The intermediate portion 529c is a portion between the mounting portion 529a and the outer peripheral portion 529b and surrounds the mounting portion 529a. In this embodiment, the mounting portion 529a substantially matches the semiconductor element 40 (drain electrode 40D) in plan view. The intermediate portion 529 c has a substantially rectangular annular shape in plan view, and the inner peripheral end of the intermediate portion 529 c substantially coincides with the outer peripheral end 402 of the semiconductor element 40 . The intermediate portion 529c is located outside the semiconductor element 40 in plan view.

As shown in FIGS. 97 to 99, the surface metal body 52 of the substrate 50 has an uneven oxide film 520, similar to the structure described in the previous embodiment (see FIGS. 67 and 74). As shown in FIG. 99, the surface metal body 52 has a base material 521 and a metal film 522 and an uneven oxide film 520 provided on the surface of the base material 521 .

The metal film 522 of this embodiment has a base film mainly composed of Ni and a top film mainly composed of a noble metal such as Au or Ag that can be bonded to the sintered member 100A. Specifically, a Ni plating film containing P and an Au plating film are used as the base film. A plurality of recesses 523 are formed in the outer peripheral portion 529b of the upper surface 52a of the metal film 522 . The recess 523 is not formed in the mounting portion 529a and the intermediate portion 529c. The film thickness of the metal film 522 is, for example, about 10 μm in the portion where the concave portion 523 is not formed. That is, the film thickness before laser light irradiation is about 10 μm. The concave portion 523 is formed by irradiating pulsed laser light. One recess 523 is formed for each pulse. In the outer peripheral portion 529b, the surface of the metal film 522 is scale-like with a plurality of recesses 523. As shown in FIG. The outer peripheral portion 529b is a laser beam irradiation area, and the mounting portion 529a and the intermediate portion 529c are non-irradiation areas.

The uneven oxide film 520 is formed on the metal film 522 . The uneven oxide film 520 is not formed on the mounting portion 529a, but is formed on the outer peripheral portion 529b and the intermediate portion 529c, which are the portions surrounding the mounting portion 529a. As described in the preceding embodiment, the uneven oxide film 520 is formed by irradiating the metal film 522 with laser light. The uneven oxide film 520 is a laser irradiation film formed by irradiation with laser light. The main component of the uneven oxide film 520 is an oxide of the main component metal of the metal film 522 .

The average film thickness of the uneven oxide film 520 is set to 10 nm to several hundred nm in the outer peripheral portion 529b, that is, the laser beam irradiation area. The uneven oxide film 520 is formed following the unevenness of the surface of the metal film 522 having the concave portions 523 . Further, the surface of the uneven oxide film 520 is formed with unevenness at a finer pitch than the width of the recessed portions 523 . That is, very fine unevenness (roughened portion) is formed. In other words, a plurality of projections 520a (columns) are formed at fine pitches. For example, the average width of the protrusions 520a is 1 nm to 300 nm, and the average distance between the protrusions 520a is 1 nm to 300 nm. Also, the average height of the projections 520a is 10 nm to several hundred nm.

The uneven oxide film 520 is formed by irradiating the metal film 522 with a laser beam and melting and vaporizing the surface layer of the metal film 522. (neighborhood) is also formed. In this embodiment, the uneven oxide film 520 is formed in the entire intermediate portion 529c of the non-irradiated area of the laser beam, and the uneven oxide film 520 is not formed in the mounting portion 529a. The width of intermediate portion 529c having uneven oxide film 520 over the entire area is, for example, 0.2 mm to 0.3 mm.

The average film thickness of the uneven oxide film 520 in the intermediate portion 529c is not directly irradiated with the laser beam, so it is thinner than the average film thickness of the uneven oxide film 520 in the outer peripheral portion 529b, and is thicker than the natural oxide film. is too thick. Specifically, it is 0.1 nm to 10 nm. Further, the height of the convex portion 520a on the surface of the uneven oxide film 520 is also lower than the outer peripheral portion 529b. Specifically, it is 0.1 nm to 10 nm. It should be noted that the average width and average interval of the convex portions 520a are approximately the same as those of the outer peripheral portion 529b.

Thus, the uneven oxide film 520 has a thick film portion 520X and a thin film portion 520Y. The thick film portion 520X is a portion of the uneven oxide film 520 provided in the laser light irradiation area, that is, the outer peripheral portion 529b. The thin film portion 520Y is a portion of the uneven oxide film 520 provided in the non-irradiated area of the laser beam, that is, the intermediate portion 529c. In the thin film portion 520Y, the thickness of the uneven oxide film 520 is thinner than that of the thick film portion 520X, and the height of the convex portion 520a is lower. The thick film portion 520X is provided on the outer peripheral portion 529b. The thin film portion 520Y is provided in the intermediate portion 529c.

Since the height of the convex portion 520a of the thick film portion 520X is higher than that of the thin film portion 520Y, the encapsulant 30 is entangled with the thick film portion 520X, and an anchor effect is generated. Also, the contact area with the sealing body 30 increases. Thereby, the sealing body 30 is in close contact with the outer peripheral portion 529b. The thick film portion 520X may be referred to as a roughened portion or a close contact portion.

The sintered member 100A is made of Ag or Cu, like the sintered member 101A described in the preceding embodiment. The sintered member 100A is a sintered body of Ag particles or Cu particles. The sintered member 100A can be joined at a lower temperature than solder. The sintered member 100A is formed by heating and pressing a sintered sheet or sintered paste. The sintered member 100A protrudes outside the outer peripheral edge 402 of the semiconductor element 40 in plan view. The sintered member 100A is arranged so as to overlap the mounting portion 529a and the intermediate portion 529c in plan view. In this embodiment, the outer peripheral edge of the sintered member 100A substantially coincides with the outer peripheral edge of the intermediate portion 529c. The sintered member 100A overlaps the entire mounting portion 529a and the intermediate portion 529c in plan view.

<Summary of the eleventh embodiment>
As described above, the intermediate portion 529c has the thin film portion 520Y of the uneven oxide film 520. As shown in FIG. By having the thin film portion 520Y, the wettability of the intermediate portion 529c to solder is lower than that of the mounting portion 529a. This makes it difficult for the solder to wet and spread from the mounting portion 529a toward the intermediate portion 529c.

In this embodiment, a sintered member 100A is used instead of solder. The sintered member 100A is formed by heating at a temperature lower than the melting point. The sintered member 100A does not melt like solder when joined. The sintered member 100A does not wet and spread on the surface of the surface metal body 52 during bonding unlike solder.

The sintered member 100A is spread between the facing surfaces of the drain electrode 40D and the surface metal body 52 during pressure sintering. By being spread, the sintered member 100A is arranged not only on the mounting portion 529a but also on the intermediate portion 529c. The sintered member 100A does not spread by wetting, but is spread by pressure and comes into contact with the thin film portion 520Y. As a result, not only the joint portion between the sintered member 100A and the mounting portion 529a but also the contact portion between the sintered member 100A and the intermediate portion 529c function as heat dissipation paths. As a result, the semiconductor device 20 with high heat dissipation can be provided. Also, the sintered member 100A has higher thermal conductivity than solder. Thereby, heat dissipation can also be improved.

Also, the height of the convex portion 520a of the thin film portion 520Y is lower than that of the thick film portion 520X. That is, the adhesion force of the intermediate portion 529c to the sealing body 30 is lower than that of the outer peripheral portion 529b. This makes it difficult for the sealing body 30 to adhere to the intermediate portion 529c. In this embodiment, the sintered member 100A is in contact with the intermediate portion 529c. The sintered member 100A covers the portion of the upper surface 52a with low adhesion. Therefore, it is possible to suppress peeling of the sealing body 30 from the upper surface 52 a around (near) the semiconductor element 40 . As a result, concentration of thermal stress on the joint portion of the sintered member 100A and the drain electrode 40D can be suppressed, and the connection reliability can be improved.

In the present embodiment, the entire intermediate portion 529c is positioned outside the semiconductor element 40 . According to this, the joint portion between the sintered member 100A and the mounting portion 529a can be enlarged. The contact portion between the sintered member 100A located outside the semiconductor element 40 and the intermediate portion 529c also functions as a heat dissipation path. Therefore, heat dissipation can be further improved.

<Modification>
Although an example in which the sintered member 100A overlaps the entire intermediate portion 529c has been shown, the present invention is not limited to this. The sintered member 100A may overlap at least a portion of the intermediate portion 529c. In other words, the sintered member 100A should be in contact with at least a portion of the thin film portion 520Y of the uneven oxide film 520. As shown in FIG. As a result, the heat dissipation path can be expanded and the heat dissipation can be improved.

The arrangement of the intermediate portion 529c is not limited to the above example. Only a part of the intermediate portion 529 c in the width direction may be located outside the semiconductor element 40 . If at least a portion of the intermediate portion 529c in the width direction is provided outside the semiconductor element 40, the joint portion can be enlarged and the heat dissipation path can be enlarged. Therefore, heat dissipation can be improved.

Further, at least a portion of the intermediate portion 529 c in the width direction may be located inside the outer peripheral edge 402 of the semiconductor element 40 . According to this, the sintered member 100A is brought into contact with the thin film portion 520Y (intermediate portion 529c), so that the outer peripheral portion 529b can be brought closer to the semiconductor element 40 while improving the heat radiation performance. That is, it is possible to suppress the peeling of the sealing body 30 around the semiconductor element 40 .

In the example shown in FIGS. 100 and 101, the intermediate portion 529c straddles the outer peripheral edge 402 of the semiconductor element 40 in plan view. That is, a portion of the intermediate portion 529c in the width direction is located outside the outer peripheral end 402, and the other portion is located inside the outer peripheral end 402. As shown in FIG. The sintered member 100A overlaps the entire mounting portion 529a and the intermediate portion 529c in plan view. According to this, as described above, it is possible to suppress peeling of the encapsulant 30 around the semiconductor element 40 while improving heat dissipation. 100 and 101 are diagrams showing modifications. FIG. 100 corresponds to FIG. 97, and FIG. 101 corresponds to FIG.

In the example shown in FIGS. 102 and 103, the outer peripheral edge of the intermediate portion 529c substantially coincides with the outer peripheral edge 402 of the semiconductor element 40 in plan view. The outer peripheral edge of the sintered member 100A also substantially coincides with the outer peripheral edge 402 of the semiconductor element 40 in plan view. According to this, the outer peripheral portion 529b (the thick film portion 520X) is positioned adjacent to the semiconductor element 40 in plan view. Therefore, the contact of the sintered member 100A with the intermediate portion 529c improves the heat dissipation, and the peeling of the sealing body 30 around the semiconductor element 40 can be suppressed more effectively. 102 and 103 are diagrams showing modifications. FIG. 102 corresponds to FIG. 97, and FIG. 103 corresponds to FIG.

In the example shown in FIG. 104, part of the outer peripheral portion 529b overlaps the semiconductor element 40 in plan view. The intermediate portion 529c is positioned inside the outer peripheral edge 402 of the semiconductor element 40 . FIG. 104 is a diagram showing a modification. FIG. 104 corresponds to FIG. In this case, the sintered member 100A may contact only the thin film portion 520Y. The sintered member 100A may contact the thin film portion 520Y and the portion of the thick film portion 520X directly below the semiconductor element 40 .

Although an example in which the uneven oxide film 520 is provided only on the surface metal body 52 to which the drain electrode 40D is connected has been shown, the present invention is not limited to this. In addition to the surface metallization 52, it may be provided on the side surface of the conductive spacer 70 to which the source electrode 40S is connected and/or on the surface metallization 62 of the substrate 60. FIG. As described above, the thick film portion 520X of the uneven oxide film 520 provides the function of enhancing the adhesion to the sealing body 30 and the function of suppressing the wetting and spreading of the solder, which is the bonding material. The uneven oxide film 520 is preferably provided at a place where overflow of solder is desired to be suppressed or a place where adhesion to the sealing body 30 is desired to be enhanced.

Although an example of the substrate 50 is shown as the wiring member, the wiring member is not limited to this. A metal plate (lead frame) may be employed instead of the substrate 50 . Also, instead of the substrate 60, a metal plate (lead frame) may be employed. Instead of the conductive spacer 70, the metal plate on the side of the source electrode 40S may be provided with a convex portion.

Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been shown, the present invention is not limited to this. Only the semiconductor element 40 forming one of the arms may be provided. The semiconductor device 20 may include only one semiconductor element 40, for example.

The configurations described in this embodiment are the first, second, third, fourth, fifth, sixth, seventh, eighth, and third embodiments. Combinations with any of the configurations described in the ninth embodiment, tenth embodiment, and modifications are possible.

(12th embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to suppress cracks occurring in the main electrode, the sintered member, which is the bonding material, may have a multi-layer structure as described in this embodiment.

<Semiconductor device>
First, based on FIG. 105, the semiconductor device 20 according to this embodiment will be described. FIG. 105 is a cross-sectional view corresponding to (part of) FIG. In FIG. 105, illustration of the external connection terminals 90 and the bonding wires 110 is omitted for the sake of convenience.

The semiconductor device 20 of this embodiment has a configuration similar to that described in the previous embodiment (see FIGS. 2 to 13). As shown in FIG. 105, the semiconductor device 20 includes a semiconductor element 40 (40H), substrates 50 and 60 as wiring members arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. there is The semiconductor element 40 has a drain electrode 40D as a first main electrode on one surface of a semiconductor substrate 41 and a source electrode 40S as a second main electrode on the back surface. The drain electrode 40D is the main electrode on the high potential side, and the source electrode 40S is the main electrode on the low potential side. The source electrode 40S is provided on the same surface as the pad 40P.

The surface metal body 52 of the substrate 50, which is the first wiring member, is connected to the drain electrode 40D. The substrate 60 and the conductive spacer 70, which are the second wiring members, are connected to the source electrode 40S. The encapsulant 30 encapsulates the semiconductor element 40 , the substrates 50 and 60 and the conductive spacers 70 . Although not shown, the semiconductor device 20 includes a semiconductor element 40L.

The drain electrode 40D and the surface metal body 52 of the substrate 50 are joined by a sintered member 100A, which is a joining material 100, similarly to the configuration described in the preceding embodiment (see FIG. 97). The source electrode 40S and the conductive spacer 70 are bonded by a multilayer bonding material 101C, which is the bonding material 101. FIG.

<Multilayer bonding material and its peripheral structure>
Next, the multilayer bonding material 101C and its peripheral structure will be described with reference to FIGS. 106 and 107. FIG. FIG. 106 is an enlarged view of area CVI in FIG. In FIG. 106, illustration of pads is omitted for the sake of convenience. FIG. 107 is a diagram showing the relationship between the Young's modulus and the yield stress of the base electrode 42, the sintered layer 106, and the brittle layer 107. FIG. In the strain-stress diagram shown in FIG. 107, the solid line indicates the fragile layer 107, the dashed line indicates the sintered layer 106, and the one-dot chain line indicates the base electrode .

Similar to the configuration described in the preceding embodiment (see FIG. 91), the source electrode 40S has a base electrode 42 formed on the semiconductor substrate 41 and a connection electrode 43 formed on the base electrode 42. . The base electrode 42 is made of an AlSi-based alloy such as AlSi, AlSiCu, or the like. The connection electrode 43 contains at least a noble metal for bonding with the multilayer bonding material 101C. The connection electrode 43 is a plated film containing Au or Ag and Ni, for example.

The conductive spacer 70 contains a metal such as Cu, and has a base material 71 forming a main portion of the conductive spacer 70 and a metal film 72 formed on the surface of the base material 71 . The metal film 72 contains at least a noble metal for bonding with the multilayer bonding material 101C. The metal film 72 is a plated film containing Au or Ag and Ni, for example. Metal film 72 is provided, for example, on a bonding surface including a surface facing semiconductor element 40 .

The multilayer bonding material 101C has a sintered layer 106 and a fragile layer 107. As shown in FIG. The sintered layer 106 has the same configuration as the sintered member 101A described in the preceding embodiment. The sintered layer 106 is a pressurized sintered body of Ag particles or Cu particles. The strength of the brittle layer 107 is intentionally made low so that cracks will occur before the source electrode 40S, particularly the base electrode 42, when thermal stress acts.

As shown in FIG. 107, the Young's modulus YM2 of the sintered layer 106 is slightly smaller than the Young's modulus YM1 of the underlying electrode . However, the yield stress YS2 of the sintered layer 106 is sufficiently larger than the yield stress YS1 of the base electrode 42. FIG. The yield strain of the sintered layer 106 is larger than the yield strain of the underlying electrode 42 . On the other hand, the Young's modulus YM3 of the fragile layer 107 is smaller than the Young's modulus YM1 of the underlying electrode 42 . Furthermore, the yield stress YS3 of the fragile layer 107 is smaller than the yield stress YS1 of the base electrode 42. FIG. The Young's modulus YM3 of the brittle layer 107 is smaller than the Young's modulus YM2 of the sintered layer 106 . The yield stress YS3 of the brittle layer 107 is smaller than the yield stress YS2 of the sintered layer 106.

The fragile layer 107 of this embodiment is a sintered body made of the same type of particles (for example, Ag particles) as the sintered layer 106 . The brittle layer 107 is a low-pressure sintered body sintered with a pressure lower than that of the sintered layer 106 . The brittle layer 107 is, for example, a pressureless sintered body sintered without pressure. Due to sintering at a lower applied pressure, the brittle layer 107 has more voids between particles than the sintered layer 106 . The brittle layer 107 is sparse compared to the sintered layer 106 .

The fragile layer 107 is a sintered body of Ag particles or Cu particles. The thermal conductivity of the brittle layer 107 is 200 W/m·K or more. The sintered layer 106 , which is denser than the frangible layer 107 , has a higher thermal conductivity than the frangible layer 107 .

As shown in FIG. 106, the multilayer bonding material 101C has sintered layers 106 at both ends and a fragile layer 107 between the sintered layers 106 in the Z direction, which is the plate thickness direction of the semiconductor element 40. have a structure. A brittle layer 107 is laminated on the sintered layer 106 , and the sintered layer 106 is laminated on the brittle layer 107 . One of the sintered layers 106 is joined to the connection electrode 43 of the source electrode 40S, and the other one of the sintered layers 106 is joined to the metal film 72 of the conductive spacer 70 . The brittle layer 107 is sandwiched between the sintered layers 106 in the Z direction. Since the brittle layer 107 is a low-pressure sintered body as described above, the thickness of the brittle layer 107 is greater than the thickness of each of the sintered layers 106, for example.

<Summary of the twelfth embodiment>
As described in the preceding embodiments, thermal stress tends to concentrate on the source electrode 40S, especially on the underlying electrode 42 . In addition, in the bonding structure using the bonding material 101, if only the sintered member is used as the bonding material 101, the sintered member is less likely to reach the yield stress than the source electrode 40S. 42).

In this embodiment, the bonding material 101 that bonds the source electrode 40S and the conductive spacer 70 is the multilayer bonding material 101C. The multilayer bonding material 101</b>C has a sintered layer 106 and a fragile layer 107 . The fragile layer 107 has a smaller Young's modulus and/or yield stress than the source electrode 40S (underlying electrode 42). This concentrates the thermal stress on the fragile layer 107 . For example, cracks are generated in the fragile layer 107 before cracks are generated in the source electrode 40S. Therefore, element damage can be suppressed.

In this embodiment, as shown in FIG. 107, the brittle layer 107 has smaller Young's modulus and yield stress than the source electrode 40S (underlying electrode 42). As a result, element damage can be effectively suppressed.

Also, the multilayer bonding material 101C (bonding material 101) includes a sintered body. The thermal conductivity of the sintered body is sufficiently higher than that of solder. Therefore, heat dissipation can be improved.

In this embodiment, the brittle layer 107 is a sintered body of the same type of particles as the sintered layer 106 . The brittle layer 107 has larger voids between grains than the sintered layer 106 . The fragile layer 107 is a sintered body formed with a pressure lower than that of the sintered layer 106 . By changing the applied pressure, the sintered layer 106 and the fragile layer 107 can be formed. Therefore, the configuration can be simplified.

In this embodiment, the multilayer bonding material 101C has a three-layer structure. The multilayer bonding material 101C has sintered layers 106 at both ends and a fragile layer 107 between the sintered layers 106 . One of the sintered layers 106 forms a joint with the source electrode 40S, and the other one of the sintered layers 106 forms a joint with the conductive spacer 70, which is the second wiring member. Therefore, it is possible to suppress element damage while ensuring the bondability with the source electrode 40S and the conductive spacer 70 .

<Modification>
As the brittle layer, an example of the brittle layer 107 sintered with a pressure lower than that of the sintered layer 106 is shown, but the brittle layer is not limited to this. Instead of the fragile layer 107 which is a sintered body, as shown in FIG. 108, a fragile layer 108 which is a non-sintered body may be employed. The brittle layer 108 contains Al, for example. The brittle layer 108 containing Al has a smaller Young's modulus and/or yield stress than the source electrode 40S (underlying electrode 42). Therefore, like the fragile layer 107, element damage can be suppressed. The thermal conductivity of the brittle layer 108 containing Al is also 200 W/m·K or more. FIG. 108 is a cross-sectional view showing a modification, and corresponds to FIG.

Although the multilayer bonding material 101C has shown an example of a three-layer structure, it is not limited to this. For example, it may have a structure of four or more layers. Also, as shown in FIG. 109, a two-layer structure may be employed. The multilayer bonding material 101C has a sintered layer 106 on the conductive spacer 70 side and a fragile layer 107 on the source electrode 40S side. In this manner, the fragile layer 107 is arranged at a position close to the semiconductor element 40 . Therefore, the effect of suppressing element damage can be enhanced. FIG. 109 is a cross-sectional view showing a modification, and corresponds to FIG.

In the example shown in FIG. 110, the multilayer bonding material 101C has the sintered layer 106 on the source electrode 40S side and the fragile layer 107 on the conductive spacer 70 side. A sintered layer 106 which is a pressurized sintered body and has better heat dissipation than the fragile layer 107 is arranged at a position closer to the semiconductor element 40 . Therefore, heat dissipation can be improved. FIG. 110 is a cross-sectional view showing a modification, and corresponds to FIG.

Although an example in which the second wiring member to which the source electrode 40S is connected includes the substrate 60, which is a wiring board, and the conductive spacer 70, the present invention is not limited to this. Instead of the conductive spacer 70, the surface metal body 62 may be provided with a convex portion. In other words, the second wiring member may have only the substrate 60 without the conductive spacer 70 . In this case, the multilayer bonding material 101C is interposed between the tip surface of the projection of the surface metal body 62 and the source electrode 40S (connection electrode 43).

Although an example of the substrate 50 is shown as the first wiring member, the present invention is not limited to this. A metal plate (lead frame) may be employed instead of the substrate 50 . Although an example of the substrate 60 is shown as the second wiring member, the present invention is not limited to this. A metal plate (lead frame) may be employed instead of the substrate 60 . The second wiring member may have the metal plate and the conductive spacer 70, or instead of the conductive spacer 70, the metal plate may be provided with a convex portion.

Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been shown, the present invention is not limited to this. Only the semiconductor element 40 forming one of the arms may be provided. The semiconductor device 20 may include only one semiconductor element 40, for example.

The configurations described in this embodiment are the first, second, third, fourth, fifth, sixth, seventh, eighth, and third embodiments. Combinations with any of the configurations described in the ninth embodiment, tenth embodiment, eleventh embodiment, and modifications are possible.

(13th embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. Each arm may be composed of one semiconductor element 40 as described in this embodiment.

<Power converter>
First, based on FIG. 111, the circuit configuration of the power conversion device 4 to which the semiconductor device 20 is applied will be described. FIG. 111 is a diagram showing an equivalent circuit of the power conversion device 4. As shown in FIG.

The power conversion device 4 shown in FIG. 111 is also used in the drive system 1 of the vehicle. The configuration of the power conversion device 4 is substantially the same as the configuration described in the preceding embodiment (see FIG. 1). A different point is that each arm has only one MOSFET 11 . The upper and lower arm circuits 9 for one phase are composed of two MOSFETs 11 . The upper and lower arm circuits 9 for one phase are provided by one semiconductor device 20 .

<Semiconductor device>
Next, the semiconductor device will be described with reference to FIGS. 112 to 121. FIG. 112 is a perspective view of the semiconductor device 20. FIG. 113 is a plan view showing the semiconductor device 20. FIG. FIG. 113 is a transparent view showing the internal structure. 114 is a plan view showing a state in which the semiconductor element 40 is mounted on the substrate 50. FIG. In FIG. 114, FIG. 10 shows the lead frame 94 for convenience. 115 is a plan view showing the circuit pattern of the substrate 50. FIG. FIG. 115 shows a state in which the semiconductor element 40 and the joint portion 81 are mounted on the substrate 50 . In FIG. 115, the P terminal 91P, the output terminal 92, and the guide frame 94c, which are joined to the surface metal body 52, are also illustrated by broken lines.

116 is a plan view showing the circuit pattern of the substrate 60. FIG. In FIG. 116, semiconductor element 40, joint portion 81, and N terminal 91N that are joined to surface metal body 62 are also illustrated by dashed lines. 117 is a cross-sectional view along line CXVII-CXVII of FIG. 113. FIG. 118 is a cross-sectional view taken along line CXVIII-CXVIII in FIG. 113. FIG. 119 is a cross-sectional view taken along line CXIX-CXIX in FIG. 113. FIG. 120 is a cross-sectional view taken along line CXX-CXX in FIG. 113. FIG. FIG. 121 is an enlarged view of the region CXXI indicated by the dashed-dotted line in FIG. 120. FIG.

In this embodiment, as in the preceding embodiment, the thickness direction of the semiconductor element 40 (semiconductor substrate) is the Z direction, and the direction in which the semiconductor elements 40H and 40L are arranged is the Y direction. A direction perpendicular to both the Z direction and the Y direction is defined as the X direction. Unless otherwise specified, a planar shape is defined as a planar shape viewed from the Z direction, in other words, a planar shape along the XY plane defined by the X and Y directions. Hereinafter, the terms “inner” and “outer” indicate relative positional relationships with the center of the semiconductor element 40 as a reference position. The side closer to the center is the inner side, and the farther side is the outer side.

The semiconductor device 20 of this embodiment constitutes one of the upper and lower arm circuits 9, that is, the upper and lower arm circuits 9 for one phase, as in the previous embodiment. The semiconductor device 20 has elements similar to those of the configuration described in the previous embodiment (see FIGS. 2 to 13). As shown in FIGS. 112 to 121, the semiconductor device 20 includes a sealing body 30, a semiconductor element 40, substrates 50 and 60, conductive spacers 70, arm connecting portions 80, and external connection terminals 90. there is In the following, mainly the parts that differ from the configuration described in the preceding embodiment will be described.

The encapsulant 30 encloses part of other elements that constitute the semiconductor device 20, as in the previous embodiment. As shown in FIGS. 112 and 113, the sealing body 30 has a substantially rectangular planar shape. The sealing body 30 has one surface 30a and a back surface 30b in the Z direction. The side surface connecting the one surface 30a and the back surface 30b includes two side surfaces 30f and 30g from which the external connection terminals 90 protrude. The side surface 30g is a surface opposite to the side surface 30f in the X direction.

The semiconductor element 40 is formed by forming a switching element on a semiconductor substrate. A semiconductor element 40 of the present embodiment is formed by forming an n-channel MOSFET 11 on a semiconductor substrate made of SiC, as in the previous embodiment. The semiconductor element 40 has, as main electrodes, a drain electrode 40D on one surface and a source electrode 40S on the back surface. The semiconductor element 40 has pads 40P on its back surface.

The semiconductor element 40 includes one semiconductor element 40H forming the upper arm 9H and one semiconductor element 40L forming the lower arm 9L. The configurations of the semiconductor elements 40H and 40L are common to each other. As shown in FIGS. 113 and 114, the semiconductor elements 40H and 40L are arranged in the Y direction. Each semiconductor element 40 is arranged at substantially the same position in the Z direction. A drain electrode 40</b>D of each semiconductor element 40 faces the substrate 50 . A source electrode 40</b>S of each semiconductor element 40 faces the substrate 60 .

The substrates 50 and 60 are arranged so as to sandwich the plurality of semiconductor elements 40 in the Z direction. The substrates 50 and 60 are arranged so that at least parts of them face each other in the Z direction. The substrates 50, 60 include all of the plurality of semiconductor elements 40 (40H, 40L) in plan view.

The substrate 50 is arranged on the drain electrode 40D side. The substrate 60 is arranged on the source electrode 40S side. The substrate 50 is electrically connected to the drain electrode 40D and provides a wiring function. A substrate 60 is electrically connected to the source electrode 40S and provides a wiring function. The substrates 50 and 60 provide a heat dissipation function for dissipating heat generated by the semiconductor element 40 .

The substrate 50 includes an insulating base material 51 , a front metal body 52 and a back metal body 53 . The substrate 60 includes an insulating base material 61 , a front metal body 62 and a back metal body 63 . The substrate 60 is a substrate in which an insulating base material 61 and metal bodies 62 and 63 are laminated. The surface metal bodies 52 and 62 and the back metal bodies 53 and 63 may be simply referred to as metal bodies 52, 53, 62 and 63 below.

The insulating base material 51 electrically separates the front metal body 52 and the back metal body 53 . Similarly, the insulating base material 61 electrically isolates the front metal body 62 and the back metal body 63 . In this embodiment, resin-based insulating base materials 51 and 61 are employed, and the material configuration is common.

Metal bodies 52, 53, 62, 63 are provided, for example, as metal plates or metal foils. The surface metal bodies 52, 62 are patterned. The surface metal bodies 52 and 62 may have a plating film of Ni or Au on the metal surface. Below, the pattern of the surface metal bodies 52 and 62 may be referred to as a circuit pattern. The surface metal body 52 has a P wiring 54 and a relay wiring 55 as in the previous embodiment. The P wiring 54 and the relay wiring 55 are electrically separated by a predetermined interval (gap). This gap is filled with a sealing body 30 .

The P wiring 54 is connected to the P terminal 91P and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 electrically connects the P terminal 91P and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 has a substantially rectangular planar shape with the X direction as the longitudinal direction. The relay wiring 55 is connected to the drain electrode 40</b>D of the semiconductor element 40</b>L, the arm connecting portion 80 and the output terminal 92 . The relay wiring 55 has a substantially rectangular planar shape.

The P wiring 54 and the relay wiring 55 are arranged side by side in the Y direction. The semiconductor element 40</b>L is mounted biased toward one end side of the relay wiring 55 in the Y direction, specifically, the side farther from the P wiring 54 . The joint portion 81 constituting the arm connection portion 80 is mounted biased toward the other end side of the relay wiring 55 in the Y direction, specifically, the side closer to the P wiring 54 . The P terminal 91P is connected to the vicinity of one end of the P wiring 54 in the X direction. The output terminal 92 is connected near one end in the X direction of the relay wiring 55 . P terminal 91P and output terminal 92 are arranged on the same side of semiconductor element 40 in the X direction.

The surface metal body 62 has an N wiring 64 and a relay wiring 65 as in the previous embodiment. The N wiring 64 and the relay wiring 65 are electrically separated by a predetermined interval (gap). This gap is filled with a sealing body 30 . The N wiring 64 is connected to the N terminal 91N and the source electrode 40S of the semiconductor element 40L. The relay wiring 65 is connected to the source electrode 40S and the arm connecting portion 80 of the semiconductor element 40H.

The N wiring 64 has a base portion 644 and an extension portion 645 . The N wiring 64 has a substantially L-shaped plane. The base 644 has a substantially rectangular shape in plan view. The base 644 includes the semiconductor element 40L in plan view. The extended portion 645 is connected to one side of a base portion 644 having a substantially rectangular planar shape. The extended portion 645 extends from the side of the base portion 644 facing the relay wiring 65 toward the base portion 654 in the Y direction.

The relay wiring 65 has a base portion 654 and an extension portion 655 . The relay wiring 65 has a substantially L-shaped plane. The base 654 has a substantially rectangular shape in plan view. The base 654 includes the semiconductor element 40H in plan view. The extended portion 655 is connected to one side of a base portion 654 having a substantially rectangular planar shape. The extended portion 655 extends from the side of the base portion 654 facing the N wiring 64 toward the base portion 644 in the Y direction. At least a portion of the extended portion 655 overlaps the relay wiring 55 in plan view.

The N wiring 64 and the relay wiring 65 are arranged side by side in the Y direction. The bases 644, 654 are aligned in the Y direction. A source electrode 40S of the semiconductor element 40L is electrically connected to the base 644. As shown in FIG. A source electrode 40S of the semiconductor element 40H is electrically connected to the base 654. As shown in FIG. The extensions 645 and 655 are arranged in the X direction. The N terminal 91N is connected to the extended portion 645 . The joint portion 81 is connected to the extension portion 655 .

The back metal bodies 53 , 63 are electrically separated from the front metal bodies 52 , 62 by insulating base materials 51 , 61 . The back metal bodies 53 and 63 of the present embodiment are so-called solid conductors that are arranged on almost the entire back surface of the insulating bases 51 and 61 . The back metal body 53 is exposed from one surface 30a of the sealing body 30, and the back metal body 63 is exposed from the back surface 30b. The exposed surface of the back metal body 53 is substantially flush with the one surface 30a. The exposed surface of the back metal body 63 is substantially flush with the back surface 30b.

A conductive spacer 70 is interposed between the source electrode 40S of the semiconductor element 40 and the substrate 60 . The conductive spacers 70 are individually connected to the source electrodes 40S of the semiconductor elements 40 . The semiconductor device 20 has two conductive spacers 70 . One of the conductive spacers 70 electrically connects the source electrode 40S of the semiconductor element 40H and the relay wiring 65 . Another one of the conductive spacers 70 electrically connects the source electrode 40S of the semiconductor element 40L and the N wiring 64 .

The arm connecting portion 80 electrically connects the relay wirings 55 and 65 . The arm connecting portion 80 is provided between the semiconductor element 40H and the semiconductor element 40L in the Y direction. The arm connection portion 80 is provided in an overlapping region between the relay wiring 55 and the relay wiring 65 (extending portion 655) in plan view. The arm connecting portion 80 of this embodiment includes a joint portion 81 and a bonding material 103 as in the preceding embodiment. The joint portion 81 is a metal columnar body. In the Z direction, a bonding material 103 is interposed between one end of the joint portion 81 and the relay wiring 55 , and a bonding material 103 is interposed between the other end and the relay wiring 65 .

Alternatively, the joint portion 81 may be integrally connected to at least one of the surface metal bodies 52 and 62 . In other words, the joint portion 81 may be provided integrally with the surface metal bodies 52 and 62 as part of the substrates 50 and 60 . The arm connecting portion 80 may be configured without the joint portion 81 . In other words, the arm connecting portion 80 may be configured to include only the bonding material 103 .

The external connection terminal 90 includes a power terminal 91 , an output terminal 92 and a signal terminal 93 . The power terminal 91 has a P terminal 91P and an N terminal 91N. Hereinafter, the P terminal 91P, the N terminal 91N, and the output terminal 92 may be referred to as main terminals 91P, 91N, and 92, respectively. The signal terminals 93 include a signal terminal 93H on the upper arm 9H side and a signal terminal 93L on the lower arm 9L side.

The P terminal 91P is connected near one end of the P wiring 54 in the X direction. The P terminal 91P extends outward in the X direction from the connection portion 91a with the P wiring 54 . A portion of the P terminal 91</b>P including the connection portion 91 a is covered with the sealing body 30 , and the remaining portion protrudes from the sealing body 30 . The P terminal 91P protrudes outside the sealing body 30 from the vicinity of the center in the Z direction on the side surface 30f.

The N terminal 91N is connected near one end of the N wiring 64 in the X direction. The N terminal 91N extends outward in the X direction from the connection portion 91b with the N wiring 64 . A portion of the N terminal 91N including the connection portion 91b is covered with the sealing body 30, and the remaining portion protrudes from the sealing body 30. As shown in FIG. The N terminal 91N protrudes outside the sealing body 30 from the vicinity of the center in the Z direction on the side surface 30f.

The output terminal 92 is connected near one end of the relay wiring 55 in the X direction. The output terminal 92 extends outward in the X direction from a connecting portion 92 a to the relay wiring 55 . A portion of the output terminal 92 including the connection portion 92 a is covered with the sealing body 30 , and the remaining portion protrudes from the sealing body 30 . The output terminal 92 protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30f.

The three main terminals 91P, 91N, 92 are arranged side by side in the Y direction. The main terminals 91P, 91N, and 92 are arranged in the order of the P terminal 91P, the N terminal 91N, and the output terminal 92 in the Y direction. P-terminal 91P and N-terminal 91N, which are power supply terminals 91, face each other at a portion including a portion protruding from sealing body 30. As shown in FIG.

The signal terminal 93 is electrically connected to the corresponding pad 40P of the semiconductor element 40 via a connecting member such as a bonding wire 110. As shown in FIG. The signal terminal 93H is connected via a bonding wire 110 to a pad 40P of the semiconductor element 40H. The signal terminal 93L is connected via a bonding wire 110 to a pad 40P of the semiconductor element 40L. The signal terminal 93 extends outward in the X direction and protrudes outside the sealing body 30 from the vicinity of the center in the Z direction on the side surface 30g. The signal terminal 93 extends on the side opposite to the main terminals 91P, 91N, 92 in the X direction.

The lead frame 94 includes external connection terminals 90, tie bars 94a, and an outer frame 94b, similarly to the configuration described in the preceding embodiment. The lead frame 94 of this embodiment further includes a guide frame 94c. As described in the previous embodiment, the tie bars 94a and the outer frame 94b are removed as unnecessary parts during the manufacturing process of the semiconductor device 20. FIG. On the other hand, the guide frame 94c remains as an element of the semiconductor device 20 together with the external connection terminals 90. FIG.

The lead frame 94, as shown in FIG. 114, has two guide frames 94c. One of the guide frames 94c is connected to the P terminal 91P. The guide frame 94c connects the P terminal 91P and the outer frame 94b before removing unnecessary portions. Another one of the guide frames 94 c is connected to the output terminal 92 . The guide frame 94c connects the output terminal 92 and the outer frame 94b before removing unnecessary portions.

As shown in FIGS. 114 and 119 to 121, the guide frame 94c has a connecting portion 940, a first connecting portion 941, and a second connecting portion 942. As shown in FIG. The connection portion 940 is a connection portion with the surface metal body 52 in the guide frame 94c. A guide frame 94 c connected to the P terminal 91 P is connected to the P wiring 54 . Specifically, the connection portion 940 is connected to the vicinity of the end portion of the P wiring 54 opposite to the connection portion of the P terminal 91P and on the side opposite to the relay wiring 55 in the Y direction. . The connecting portion 940 is connected to one of the four corners of the P wiring 54 having a substantially rectangular planar shape.

The first connecting portion 941 connects the P terminal 91</b>P and the connecting portion 940 . The first connecting portion 941 extends from the connection portion 91a of the P terminal 91P toward the side surface 30g in the X direction. The first connecting portion 941 does not overlap the P wiring 54 (surface metal body 52) in plan view. The first connecting portion 941 extends along the outer peripheral edge of the surface metal body 52 outside the surface metal body 52 . The second connecting portion 942 connects the connecting portion 940 and the outer peripheral frame 94b. The second connecting portion 942 extends outward in the X direction from the connecting portion 940 .

A guide frame 94 c connected to the output terminal 92 is connected to the relay wiring 55 . Specifically, the connection portion 940 is connected to the vicinity of the end portion of the relay wiring 55 opposite to the connection portion of the output terminal 92 and opposite to the P wiring 54 in the Y direction. . The connecting portion 940 is connected to one of the four corners of the relay wiring 55 having a substantially rectangular planar shape.

The first connection portion 941 connects the output terminal 92 and the connection portion 940 . The first connecting portion 941 extends from the connecting portion 92a of the output terminal 92 toward the side surface 30g in the X direction. The first connecting portion 941 does not overlap the relay wiring 55 (surface metal body 52) in plan view. The first connecting portion 941 extends along the outer peripheral edge of the surface metal body 52 outside the surface metal body 52 . The second connecting portion 942 connects the connecting portion 940 and the outer peripheral frame 94b. The second connecting portion 942 extends outward in the X direction from the connecting portion 940 .

The guide frame 94c can have a connection structure (joint structure) similar to that of the main terminals 91P, 91N, and 92. FIG. The guide frame 94c is connected to the surface metal body 52 via a bonding material 104, for example. As the bonding material 104, solder or a sintered member can be used as described in the previous embodiments. The guide frame 94c may be joined directly to the surface metal body 52 without the joining material 104 interposed. For example, it may be directly joined to the surface metal body 52 by ultrasonic welding, friction stir welding, laser welding, or the like.

As described above, in the semiconductor device 20 of the present embodiment, the plurality of semiconductor elements 40 forming the upper and lower arm circuits 9 for one phase are sealed with the sealing body 30 . The sealing body 30 integrally seals the plurality of semiconductor elements 40 , a portion of the substrate 50 , a portion of the substrate 60 , a plurality of conductive spacers 70 , arm connection portions 80 , and portions of the external connection terminals 90 . is stopping. The sealing body 30 seals the insulating substrates 51 , 61 and the surface metal bodies 52 , 62 in the substrates 50 , 60 .

The semiconductor element 40 is arranged between the substrates 50, 60 in the Z direction. The semiconductor element 40 is sandwiched between the substrates 50 and 60 arranged opposite to each other. Thereby, the heat of the semiconductor element 40 can be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50 b of the substrate 50 is substantially flush with the one surface 30 a of the sealing body 30 . The back surface 60 b of the substrate 60 is substantially flush with the back surface 30 b of the sealing body 30 . Since the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be enhanced.

<Summary of the thirteenth embodiment>
The configuration described in this embodiment can be combined with the configuration except some of the various configurations described in the preceding embodiments. The above-mentioned part includes a configuration in which a power supply terminal is connected to each of the pair of extended portions of the surface metal body (see FIGS. 15 and 23), and a structure in which a plurality of semiconductor elements connected in parallel are separated from each other by the surface metal body. It is a configuration in which a slit is provided (see FIG. 28, etc.). That is, the configuration described in this embodiment includes the first embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, the eighth embodiment, and the ninth embodiment. Combinations with any of the configurations described in the embodiment, the tenth embodiment, the eleventh embodiment, the twelfth embodiment, and the modifications are possible.

Although an example in which the semiconductor device 20 includes the conductive spacers 70 has been shown, the present invention is not limited to this. Instead of the conductive spacer 70, the surface metal body 62 may be provided with a convex portion.

Although an example of the substrate 50 is shown as a wiring member connected to the drain electrode 40D, the wiring member is not limited to this. In a configuration not limited to the substrate 50, a metal plate (lead frame) may be employed instead of the substrate 50. FIG. Although an example of the substrate 60 is shown as a wiring member connected to the source electrode 40S, the wiring member is not limited to this. In a configuration not limited to the substrate 60, a metal plate (lead frame) may be employed instead of the substrate 60. FIG.

(Other embodiments)
The disclosure in this specification, drawings, etc. is not limited to the illustrated embodiments. The disclosure encompasses the illustrated embodiments and variations thereon by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and/or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses omitting parts and/or elements of the embodiments. The disclosure encompasses permutations or combinations of parts and/or elements between one embodiment and another. The disclosed technical scope is not limited to the description of the embodiments. The disclosed technical scope is indicated by the description of the claims, and should be understood to include all changes within the meaning and range of equivalents to the description of the claims.

The disclosure in the specification, drawings, etc. is not limited by the description in the claims. The disclosure in the specification, drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and broader technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure of the specification, drawings, etc., without being bound by the scope of claims.

When an element or layer is referred to as being "overlying," "coupled with," "connected to," or "coupled with," it refers to other elements or layers. may be coupled, connected or bonded directly on, and there may be intervening elements or layers. In contrast, an element is "directly on", "directly coupled to", "directly connected to" or "directly coupled to" another element or layer. When referred to, there are no intervening elements or layers present. Other terms used to describe relationships between elements are used in a similar fashion (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). ) should be interpreted. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The spatially relative terms "inside", "outside", "behind", "below", "low", "above", "high", etc., refer to an element or feature as illustrated. It is used here to facilitate the description describing its relationship to other elements or features. Spatially-relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, when the device in the figures is turned over, elements described as "below" or "beneath" other elements or features are oriented "above" the other elements or features. Thus, the term "bottom" can encompass both an orientation of up and down. The device may be oriented in other directions (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly. .

The vehicle drive system 1 is not limited to the configuration described above. For example, although the example provided with one motor generator 3 was shown, it is not limited to this. A plurality of motor generators may be provided. Although an example in which the power conversion device 4 includes the inverter 6 as a power conversion circuit is shown, the present invention is not limited to this. For example, the configuration may include a plurality of inverters. At least one inverter and a converter may be provided. Only a converter may be provided.

Although an example in which the semiconductor element 40 has the MOSFET 11 as a switching element is shown, the present invention is not limited to this. For example, IGBTs can be employed. IGBT is an abbreviation for Insulated Gate Bipolar Transistor.

DESCRIPTION OF SYMBOLS 1... Drive system, 2... DC power supply, 3... Motor generator, 4... Power converter, 5... Smoothing capacitor, 6... Inverter, 7... P line, 8... N line, 9... Upper and lower arm circuit, 9H... Upper arm , 9L...lower arm, 10...output line, 11...MOSFET, 12...diode, 20...semiconductor device, 30...sealing body, 30a...first surface, 30b...back surface, 30c, 30d, 30e, 30f, 30g...side surface, 31... Gap 40, 40H, 40L... Semiconductor element 40D... Drain electrode 40S... Source electrode 40P... Pad 400, 401... Side 402... Peripheral edge 41... Semiconductor substrate 41a... One surface 41b... Back surface , 42 Base electrode 420 Periphery 43 Connection electrode 44 Protective film 440, 441 Opening 442 Inner peripheral surface 50 Substrate 50a Opposite surface 50b Back surface 50c, 50d End 50sc Center 500 Laminated body 501 First inclined portion 501a Cutting mark 502 Second inclined portion 502a Cutting mark 503 Intermediate portion 503a Uneven portion 51 Insulation Substrate 51a Front surface 51b Back surface 510 Exposed portion 52 Surface metal body 52a Top surface 52b Edge 52c Side surface 52d Bottom surface 52G Inter-wiring gap 520 Uneven oxide film , 520a... Convex part 520X... Thick film part 520Y... Thin film part 521... Base material 522... Metal film 522p... Plating film 523... Concave part 524... First region 525... Second region 526... Peripheral region 527 Roughened portion 528 Non-roughened portion 529a Mounting portion 529b Peripheral portion 529c Intermediate portion 53 Back surface metal body 53a Opposed surface 53b Exposed surface 54P Wiring 540 Notch 541 Base 542 Extension 55 Relay wiring 550 Notch 551 Base 551a Opposing side 552 Extension 553 Slit 554 Chamfer , 56... Laminated body 60... Substrate 60a... Opposite surface 60b... Back surface 60c... End part 60sc... Center 600... Laminated body 601... First inclined part 602... Second inclined part 603... Middle Part 61... Insulating base material 61a... Front surface 61b... Back surface 610... Exposed part 62... Surface metal body 62a... Top surface 62c... Side surface 62d... Bottom surface 62G... Gap between wirings 620... Uneven oxide film , 624 First region 625 Second region 626 Peripheral region 627 Roughened portion 628 Non-roughened portion 63 Backside metal body 63a Opposing surface 63b Exposed surface 64N wiring, 640, 644 Base portion 640a Opposite side 640b Arrangement area 640c End portion 641, 645 Extended portion 641a Widened portion 641b Constant width portion 641c Widened portion 641d Tip 642 Cut Notch 643 Slit 65 Relay wiring 650, 652 End 651a Reduced width portion 651b Constant width portion 651c Reduced width portion 653 Slit 654 Base 655 Extending portion 70 Conductive spacer 700 Concavo-convex oxide film 71 Base material 72 Metal film 80 Arm connection portion 81 Joint portion 81a, 81b End portion 81c, 81d Side surface 810 Opposing surface 811...Accommodating part 811a...Side surface 811b...Bottom surface 90...External connection terminal 91...Power supply terminal 91a, 91b...Connecting part 91N...N terminal 91P...P terminal 92...Output terminal 92a...Connecting part , 920... Opposing surface 920a... First opposing part 920b... Second opposing part 921... Accommodating part 921a... Side surface 921b... Bottom surface 921c... Opening 922... Tip surface 923, 924... Side surface 93, 93H, 93L Signal terminals 93a Tie bar traces 93b Joining portion 93c Tip portion 93d Bending portion 93e Extension portion 93f Press R surface 93g Burr surface 93h First extension Part 93i Second extension part 93j Bending part 93k Protruding part 930 Overlapping part 930a Main part 930b Protruding part 931 Non-overlapping part 94 Lead frame 94a Tie bar 94b...peripheral frame, 94c...guide frame, 940...connecting portion, 941...first connecting portion, 941a...first extending portion, 941b...second extending portion, 942...second connecting portion, 100, 101, 102 , 103, 104... Joining material 101A... Sintered member 101B... Solder 101C... Multilayer joining material 105... Sintered sheet 106... Sintered layer 107, 108... Fragile layer 110... Bonding wire 111... Jig 112 Tool 120 Cooler 121 Heat exchange unit 130 Thermal conduction member 140 Semiconductor module 150 Intermediate board 151 Insulating base material 151a One surface 151b Back surface 151c Non-layout region 151d Placement region 151e Exposed portion 152 Conductor portion 152a, 152b Land 152c Wiring 152d Via conductor 152e Fixing land 153 Solder resist 154 Joining material

Claims (3)

a semiconductor substrate (41); a first main electrode (40D) provided on one surface of the semiconductor substrate; a second main electrode (40S) provided on the back surface opposite to the one surface in the plate thickness direction; a semiconductor element (40) having a protective film (44) provided on the back surface and provided with an opening (440) exposing the second main electrode so as to be able to be bonded;
a first wiring member (50) electrically connected to the first main electrode;
a second wiring member (60, 70) arranged so as to sandwich the semiconductor element between itself and the first wiring member in the plate thickness direction, and to which the second main electrode is connected;
a sintered member (101A) interposed between the second main electrode and the second wiring member and joining the second main electrode and the second wiring member;
A sealing body (30) that seals the semiconductor element, the first wiring member, the second wiring member, and the sintered member,
The second main electrode includes a base electrode (42) formed on the back surface of the semiconductor substrate and having a peripheral portion covered with the protective film, and a connection electrode formed on the base electrode in the opening. (43) and
The sintered member has a predetermined distance from the inner peripheral surface (442) of the protective film that defines the opening, and joins the connection electrode and the second wiring member. semiconductor device. 2. The semiconductor device according to claim 1, wherein a distance between said sintered member and said inner peripheral surface of said protective film is 5 [mu]m or more. The second wiring member has a wiring board (60) and a conductive spacer (70) interposed between the semiconductor element and the wiring board,
Claim 1 or Claim 2, wherein the inner peripheral surface of the protective film includes the conductive spacer in plan view in the plate thickness direction, and the conductive spacer coincides with the sintered member or includes the sintered member. The semiconductor device according to .

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