JP2017143657A - Switching power supply circuit, load driving device and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching power supply circuit which reduces a switching loss.SOLUTION: A switching power supply circuit 100 comprises: a switching output part 110 which uses an output transistor N1 to generate an output voltage Vo from an input voltage Vi; and a switching control part 120 which performs ON/OFF control of the output transistor N1. The switching control part 120 includes a driver 12D which generates a gate signal S4 of the output transistor N1. The driver 12D generates a gate signal S4 by a first current capability in a linear region of a switch voltage Vsw that appears in one end of the output transistor N1, and generates the gate signal S4 by a second current capability that is higher than the first current capability, in at least a portion of a nonlinear region of the switch voltage Vsw.SELECTED DRAWING: Figure 8

Description

  The present invention relates to a switching power supply circuit, a load driving device, and a liquid crystal display device.

  Conventionally, switching power supply circuits have been widely used as power supply means for various applications.

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP 2004-357495 A

  However, the conventional switching power supply circuit has room for further improvement in the switching loss.

  In view of the above-mentioned problems found by the inventors of the present application, the invention disclosed in the present specification provides a switching power supply circuit with little switching loss, and a load driving device and a liquid crystal display device using the same. With the goal.

  The switching power supply circuit disclosed in the present specification includes a switching output unit that generates an output voltage from an input voltage using an output transistor, and a switching control unit that performs on / off control of the output transistor, The switching control unit includes a driver that generates a gate signal of the output transistor, and the driver generates the gate signal with a first current capability in a linear region of a switch voltage that appears at one end of the output transistor; In at least a part of the nonlinear region of the switch voltage, the gate signal is generated with a second current capability higher than the first current capability (first configuration).

  In the switching power supply circuit having the first configuration, the driver includes: a gate signal generation unit that generates the gate signal using a plurality of buffers connected in parallel to each other; and an enable control unit that performs enable control of each buffer. It may be configured to include (second configuration).

  In the switching power supply circuit having the second configuration, the enable control unit compares the gate signal or the switch voltage with a predetermined threshold voltage to perform enable control of each buffer (third configuration). Good.

  In the switching power supply circuit having any one of the first to third configurations, the driver may be configured to periodically change the first current capability (fourth configuration).

  In the switching power supply circuit having the first configuration, the output transistor is a PMOSFET having a source connected to the input voltage application terminal, and the driver has a source connected to the input voltage application terminal and a drain connected to the input voltage application terminal. A first PMOSFET connected to the gate of the output transistor and having a gate connected to a pulse signal application terminal; and a second PMOSFET having a source connected to the input voltage application terminal and a gate connected to the pulse signal application terminal. A third PMOSFET having a source connected to the drain of the second PMOSFET and a gate and drain connected to the gate of the output transistor; a drain connected to the gate of the output transistor and a source connected to the ground terminal; NMOSFE connected to the pulse signal application end When, better to configure comprising (fifth configuration).

  In the switching power supply circuit having the first to fifth configurations, the switching control unit generates an error voltage according to a difference value between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage. A slope voltage generation unit that generates a slope voltage, a comparator that compares the error voltage and the slope voltage to determine an on-duty of the output transistor, and a set that generates a set signal pulse at a predetermined pulse period A signal generation unit; and an RS flip-flop that receives a reset signal according to a comparison result of the set signal and the comparator and outputs a pulse width modulation signal; and the driver is configured to output the pulse width modulation signal. A configuration (sixth configuration) may be employed that receives an input and generates the gate signal.

  In the switching power supply circuit having the sixth configuration, the switching control unit includes a maximum duty setting unit that generates a pulse of a maximum duty setting signal when a maximum on-time elapses after a pulse is generated in the set signal; A configuration (seventh configuration) may further include a logic gate that logically synthesizes the comparison signal of the comparator and the maximum duty setting signal to generate the reset signal.

  In the switching power supply circuit having any one of the first to seventh configurations, the switching output unit may be configured to be a step-up type, a step-down type, or a step-up / down type (eighth configuration).

  Further, a load driving device disclosed in the present specification includes a switching power supply circuit having any one of the first to eighth configurations, a driver that receives power supply from the switching power supply circuit, and drives a load; It is set as the structure (9th structure) which has.

  In addition, a liquid crystal display device disclosed in the present specification includes a load driving device having the ninth configuration and a liquid crystal display panel driven as a load of the load driving device (a tenth configuration). Composition).

  According to the invention disclosed in this specification, it is possible to provide a switching power supply circuit with little switching loss, and a load driving device and a liquid crystal display device using the same.

Block diagram showing one configuration example of a liquid crystal display device Circuit diagram showing a first embodiment of a switching power supply circuit Timing chart showing an example of duty control Switching characteristics diagram of output transistor Waveform diagram of gate signal and switch voltage Timing chart showing switching loss at ON transition Timing chart showing switching loss during off-transition Circuit diagram showing a second embodiment of the switching power supply circuit Circuit diagram showing a first embodiment of the driver Timing chart showing switching loss reduction at ON transition Timing chart showing switching loss reduction during off-transition Circuit diagram showing one configuration example of enable control unit Circuit diagram showing a specific example of a driver Circuit diagram showing a second embodiment of the driver Circuit diagram showing a third embodiment of the switching power supply circuit Timing chart showing switching loss reduction at ON transition Timing chart showing switching loss reduction during off-transition Circuit diagram showing a third embodiment of the driver External view of tablet terminal

<Liquid crystal display device>
FIG. 1 is a block diagram illustrating a configuration example of a liquid crystal display device. The liquid crystal display device 1 of this configuration example includes a liquid crystal driving device 10 and a liquid crystal display panel 20. The liquid crystal drive device 10 is a load drive device that performs drive control of the liquid crystal display panel 20 based on a video signal Sin and various commands input from a host device (such as a microcomputer) (not shown). The liquid crystal display panel 20 is video output means using liquid crystal elements as pixels, and is driven as a load of the liquid crystal driving device 10.

<Liquid crystal driving device>
The liquid crystal driving device 10 will be described in detail with reference to FIG. The liquid crystal driving device 10 of this configuration example includes a system power supply unit 11, a timing control unit 12, a level shifter 13, a gate driver 14, a source driver 15, a gamma voltage generation unit 16, a common voltage generation unit 17, including.

  The system power supply unit 11 operates by receiving an input voltage VIN (for example, + 12V), an analog power supply voltage AVDD (for example, + 17V), and a logic power supply voltage VDD (for example, + 3.3V, + 1.8V, + 1.2V). , A positive power supply voltage VGH (for example, + 28V) and a negative power supply voltage VGL (for example, −12V) are generated and supplied to each part of the apparatus.

  The timing control unit 12 operates upon receiving the supply of the logic system power supply voltage VDD, and controls the timing of the liquid crystal driving device 10 (vertical synchronization control of the gate driver 14 and source driver based on commands and data input from the host device. 15 horizontal synchronization control, etc.).

  The level shifter 13 operates by receiving the supply of the positive power supply voltage VGH and the negative power supply voltage VGL, and transmits the timing control signal (vertical synchronization signal) input from the timing control unit 12 to the gate driver 14 after level shifting.

  The gate driver 14 operates by receiving the supply of the positive power supply voltage VGH and the negative power supply voltage VGL, and the gate signals G (1) to G (y) of the liquid crystal display panel 20 based on the vertical synchronization signal input from the level shifter 13. ) Is generated. The gate signals G (1) to G (y) are the liquid crystal elements of the liquid crystal display panel 20 (when the liquid crystal display panel 20 is an active matrix type, the gate terminals of the active elements connected to the liquid crystal elements). To be supplied.

  The source driver 15 operates in response to the supply of the analog power supply voltage AVDD, and converts the digital (m-bit) video signal Sin input from a host device (not shown) into analog source signals S (1) to S (x). And is supplied to the liquid crystal elements of the liquid crystal display panel 20 (when the liquid crystal display panel 20 is an active matrix type, the source terminals of the active elements respectively connected to the liquid crystal elements).

The gamma voltage generation unit 16 operates in response to the supply of the analog power supply voltage AVDD, generates n (n = 2 ^m −1) gradation voltages V (0) to V (n), and generates a source driver. 15 is supplied. Note that the gradation voltages V (0) to V (n) correspond one-to-one with the data values “0” to “2 ^m −1” of the video signal Sin, respectively.

  The common voltage generation unit 17 generates a predetermined common voltage VC and the liquid crystal elements of the liquid crystal display panel 20 (when the liquid crystal display panel 20 is an active matrix type, the drain terminals of the active elements connected to the liquid crystal elements, respectively) ).

<Switching power supply circuit (first embodiment)>
FIG. 2 is a circuit diagram showing a first embodiment of the switching power supply circuit built in the system power supply unit 11. The switching power supply circuit 100 of the present embodiment is a circuit unit that generates a desired output voltage Vo (for example, corresponding to the analog power supply voltage AVDD) from the input voltage Vi (for example, corresponding to the input voltage VIN), and the switching output unit 110 and a switching control unit 120.

  The switching output unit 110 is a step-up switching output stage that boosts the input voltage Vi by driving the coil current IL by turning on / off the output transistor N1 to generate the output voltage Vo. In the example, an N channel MOS (metal oxide semiconductor) field effect transistor), a coil L1, a rectifier diode D1, an output capacitor Co1, and a sense resistor Rs are included.

  The first end of the coil L1 is connected to the input end of the input voltage Vi. The second end of the coil L1 is connected to the drain of the output transistor N1 and the anode of the rectifier diode D1. The source of the output transistor N1 is connected to the first end of the sense resistor Rs. The second end of the sense resistor Rs is connected to the ground terminal. The sense resistor Rs is a current / voltage conversion element for taking out the switch current Is flowing therethrough (= corresponding to the coil current IL flowing during the ON period of the output transistor N1) as the sense voltage V2 (= Is × Rs). The gate of the output transistor N1 is connected to the output terminal (= the output terminal of the gate signal S4) of the switching control unit 120. The cathode of the rectifier diode D1 is connected to the output terminal of the output voltage Vo and the first terminal of the output capacitor Co1. The second terminal of the output capacitor Co1 is connected to the ground terminal.

  However, the rectification method of the switching output unit 110 may be a synchronous rectification method instead of the diode rectification method. In that case, the rectifier diode D1 may be replaced with a synchronous rectifier transistor, which may be turned on / off complementarily with the output transistor N1.

  The switching control unit 120 is an output feedback circuit unit that performs on / off control of the output transistor N1 so that the feedback voltage Vfb corresponding to the output voltage Vo matches a predetermined reference voltage Vref, and the digital / analog conversion unit 121. A feedback voltage generation unit 122, an error amplifier 123, a phase compensation unit 124, a clock signal generation unit 125, a set signal generation unit 126, a maximum duty setting unit 127, a reference slope voltage generation unit 128, a voltage An adder 129, a comparator 12A, an OR gate 12B, an RS flip-flop 12C, and a driver 12D are included.

  The digital / analog converter 121 generates an analog reference voltage Vref from the digital reference voltage setting signal REF.

  The feedback voltage generator 122 includes resistors R1 and R2 connected in series between the output terminal of the output voltage Vo and the ground terminal, and a feedback voltage obtained by dividing the output voltage Vo from a connection node between the resistor R1 and the resistor R2. Vfb (= {R2 / (R1 + R2)} × Vo) is output. However, when the output voltage Vo is within the input dynamic range of the switching control unit 120 (particularly, the error amplifier 123), the feedback voltage generation unit 122 may be omitted and the output voltage Vo may be directly received as the feedback voltage Vfb. I do not care.

  The error amplifier 123 is a current output type transconductance amplifier (so-called gm amplifier). The error amplifier 123 includes a capacitor C1 that forms the phase compensation unit 124 according to a difference value between the feedback voltage Vfb input to the inverting input terminal (−) and the reference voltage Vref input to the non-inverting input terminal (+). The error voltage Verr is generated by charging and discharging. When the feedback voltage Vfb is lower than the reference voltage Vref, current flows from the error amplifier 123 toward the capacitor C1, so that the error voltage Verr rises. On the other hand, when the feedback voltage Vfb is higher than the reference voltage Vref, current is drawn from the capacitor C1 toward the error amplifier 123, so that the error voltage Verr decreases.

  The phase compensation unit 124 is a time constant circuit including a resistor R3 and a capacitor C1 connected in series between the output terminal of the error amplifier 123 and the ground terminal, and performs phase compensation of the error voltage Verr.

  The clock signal generator 125 generates the clock signal CLK at a predetermined reference frequency f0 (= 1 / T0).

  The set signal generation unit 126 generates a pulse of the set signal S1 in synchronization with the clock signal CLK. For example, the set signal generation unit 126 generates a pulse of the set signal S1 for every m pulses of the clock signal CLK. Therefore, the pulse period T of the set signal S1 (= the switching period T of the output transistor N1) is m × T0.

  The maximum duty setting unit 127 generates a pulse of the maximum duty setting signal S2b in synchronization with the clock signal CLK. For example, the maximum duty setting unit 127 generates a pulse of the maximum duty setting signal S2b at the nth pulse (where n <m) of the clock signal CLK, calculated from the pulse generation timing of the set signal S1. That is, the maximum duty setting unit 127 generates a pulse in the maximum duty setting signal S2b when the maximum on-time Ton (max) (= n × T0) elapses after the pulse is generated in the set signal S1.

  The reference slope voltage generator 128 generates a reference slope voltage V1 in synchronization with the clock signal CLK. For example, the reference slope voltage V1 starts to rise at the pulse generation timing of the set signal S1 (= the first pulse of the clock signal CLK), and at the pulse generation timing of the maximum duty setting signal S2b (= the nth pulse of the clock signal CLK). A sawtooth analog voltage that is reset to zero. However, the configuration of the reference slope voltage generation unit 128 is not limited to this. For example, the reference slope voltage generation unit 128 is configured to generate the reference slope voltage V1 in synchronization with both the set signal S1 and the pulse width modulation signal S3. Also good.

  The voltage adding unit 129 adds the reference slope voltage V1 and the sense voltage V2 to generate the slope voltage Vslp. In this way, the slope voltage Vslp is generated by adding the reference slope voltage V1 and the sense voltage V2, and the on-duty of the output transistor N1 is determined by using this to determine both the output voltage Vo and the coil current IL. It is possible to realize the current mode control according to the response.

  The comparator 12A compares the error voltage Verr input to the inverting input terminal (−) and the slope voltage Vslp input to the non-inverting input terminal (+) to generate the comparison signal S2a. The comparison signal S2a is at a low level when the error voltage Verr is higher than the slope voltage Vslp, and is at a high level when the error voltage Verr is lower than the slope voltage Vslp.

  The OR gate 12B outputs a logical sum signal of the comparison signal S2a and the maximum duty setting signal S2b as the reset signal S2. Accordingly, the reset signal S2 is at a high level when at least one of the comparison signal S2a and the maximum duty setting signal S2b is at a high level, and is at a low level when both the comparison signal S2a and the maximum duty setting signal S2b are at a low level. It becomes.

  The RS flip-flop 12C outputs a pulse width modulation signal S3 from the output terminal (Q) according to the set signal S1 input to the set terminal (S) and the reset signal S2 input to the reset terminal (R). For example, the pulse width modulation signal S3 is set to a high level at the rising edge of the set signal S1, and is reset to a low level at the rising edge of the reset signal S2.

  The driver 12D receives the input of the pulse width modulation signal S3 and generates a gate signal S4 (corresponding to an on / off control signal of the output transistor N1) of the output transistor N1 by enhancing the current capability thereof, and outputs the gate signal S4. Output to the gate of N1. The output transistor N1 is turned on when the gate signal S4 is at a high level and turned off when the gate signal S4 is at a low level.

<Basic operation (step-up operation)>
First, the basic operation (boost operation) of the switching power supply circuit 100 will be described. When the output transistor N1 is turned on, the coil current IL (= switch current Is) flows to the coil L1 toward the ground terminal via the output transistor N1, and the electrical energy is stored. At this time, the switch voltage Vsw appearing at the anode of the rectifier diode D1 is substantially reduced to the ground voltage via the output transistor N1. Therefore, since the rectifier diode D1 is in the reverse bias state, no current flows from the output capacitor Co1 toward the output transistor N1.

  On the other hand, when the output transistor N1 is turned off, the electric energy accumulated therein is released as a current by the back electromotive force generated in the coil L1. At this time, since the rectifier diode D1 is in a forward bias state, the coil current IL flowing through the rectifier diode D1 is output from the output terminal of the output voltage Vo to the load (source driver 15 or gamma voltage generator 16) as the output current Iout. At the same time, it flows into the ground terminal via the output capacitor Co1, and the output capacitor Co1 is charged. By repeating the above operation, the output voltage Vo obtained by boosting the input voltage Vi is supplied to the load.

<Duty control>
FIG. 3 is a timing chart showing an example of duty control according to the error voltage Verr. In order from the top, the clock signal CLK, the set signal S1, the error voltage Verr and the slope voltage Vslp, the comparison signal S2a, and the maximum duty setting signal S2b. , The reset signal S2 and the pulse width modulation signal S3 are depicted.

  In the example of this figure, a pulse of the set signal S1 is generated every 16 pulses of the clock signal CLK. When the set signal S1 rises to a high level, the pulse width modulation signal S3 is set to a high level, so that the output transistor N1 is turned on. At this time, the slope voltage Vslp starts to rise with a predetermined slope.

  Thereafter, when the slope voltage Vslp becomes higher than the error voltage Verr, the comparison signal S2a rises to a high level, and then the reset signal S2 rises to a high level. As a result, since the pulse width modulation signal S3 is reset to a low level, the output transistor N1 is turned off.

  Note that the higher the error voltage Verr, the later the crossing timing with the slope voltage Vslp. Accordingly, the high level period of the pulse width modulation signal S3 (= the ON period Ton of the output transistor N1) becomes longer, and consequently, the ON duty Don of the output transistor N1 (= the ratio of the ON period Ton to the switching period T, Don = Ton / T) increases.

  Conversely, the lower the error voltage Verr, the earlier the timing of crossing with the slope voltage Vslp. Therefore, the high level period of the pulse width modulation signal S3 is shortened, and consequently the on-duty Don of the output transistor N1 is decreased.

  Thus, in the switching power supply circuit 100, the desired output voltage Vo is generated from the input voltage Vi by determining the on-duty Don of the output transistor N1 according to the comparison result between the error voltage Verr and the slope voltage Vslp. .

  However, if the maximum duty setting signal S2b is generated before the comparison signal S2a rises to the high level as a result of the error voltage Verr becoming too high, the reset signal S2 is at the high level at that time. The output transistor N1 is turned off. That is, a predetermined upper limit value (= maximum on-time Ton (max)) is set in the on-period Ton of the output transistor N1.

<Switching loss>
FIG. 4 is a switching characteristic diagram of the output transistor N1. In the upper part of the figure, the relationship between the gate-source voltage Vgs of the output transistor N1 and the on-resistance Ron is depicted. In the upper part of the figure, a solid line indicates a general Ron characteristic, and a broken line indicates an ideal Ron characteristic. In the lower part of the figure, the gate-source voltage Vgs and gate charge Qg of the output transistor N1 (= total amount of charges stored in the gate-drain capacitance Cgd and the gate-source capacitance Cgs, respectively) and The relationship is depicted.

  As shown in the lower part of the figure, when the gate-source voltage Vgs rises from 0 V, the input capacitance (Cgd + Cgs) is charged. When the gate-source voltage Vgs reaches x0, the input capacitance (Cgd + Cgs) is equivalently increased due to the mirror effect of the output transistor N1. As a result, the input capacitance (Cgs + Cgd) is charged while the gate-source voltage Vgs hardly increases. Thereafter, when the input capacitance (Cgd + Cgs) is sufficiently charged, the gate-source voltage Vgs starts to rise again.

  Here, as shown in the upper part of the figure, the general Ron characteristic (solid line) of the output transistor N1 is duller than the ideal Ron characteristic (broken line). That is, the difference between the on-resistance Ron1 when Vgs = x1 (> x0) and the on-resistance Ron2 when Vgs = x2 (> x1) is large, and this difference leads to switching loss. Hereinafter, the reason will be described.

  FIG. 5 is a waveform diagram of the gate signal S4 and the switch voltage Vsw. When the gate signal S4 is raised from the low level (≈ground voltage GND) to the high level (≈input voltage Vi) at time t1, the output transistor N1 is turned on. Therefore, the switch voltage Vsw falls from the high level (≈output voltage Vo) to the low level (≈ground voltage GND).

  On the other hand, when the gate signal S4 falls from the high level (≈input voltage Vi) to the low level (≈ground voltage GND) at time t2, the output transistor N1 is turned off. Accordingly, the switch voltage Vsw rises from a low level (≈ground voltage GND) to a high level (≈output voltage Vo).

  In this way, the switch voltage Vsw is driven in a rectangular wave shape in accordance with the on / off of the output transistor N1. Note that the switching loss of the output transistor N1 occurs both during the on transition (time t1) and during the off transition (time t2).

  FIG. 6 is a timing chart (corresponding to an enlarged view of the vicinity of time t1 in FIG. 5) showing the switching loss at the time of ON transition of the output transistor N1, and depicts the gate signal S4 (solid line) and the switch voltage Vsw (broken line). Has been.

  The gate signal S4 does not rise uniformly from the low level (≈ground voltage GND) to the high level (≈input voltage Vi) when the output transistor N1 is turned on, but by the mirror effect of the output transistor N1. An on transition period TT1 (= time t11 to t12) in which the rise temporarily stagnates is exhibited.

  The switch voltage Vsw decreases linearly during the on-transition period TT1, but the linearity is lost in other periods (= before time t11 and after time t12). Switching loss occurs (see hatched area in the figure).

  For example, after time t12, even if the gate signal S4 starts to rise again after the on-transition period TT1, the on-resistance Ron of the output transistor N1 does not fall easily, and the switch voltage Vsw is low (≈ground voltage GND). The state of not falling down is depicted. In such a situation, the amount of voltage drop at the output transistor N1 becomes large, which becomes a switching loss. Such switching loss becomes more prominent as the Ron characteristic of the output transistor N1 (see the upper stage of FIG. 4 described above) becomes dull.

  FIG. 7 is a timing chart (corresponding to an enlarged view of the vicinity of time t2 in FIG. 5) showing the switching loss at the time of the output transistor N1 being turned off. Has been.

  The gate signal S4 does not decrease uniformly from the high level (≈input voltage Vi) to the low level (≈ground voltage GND) when the output transistor N1 is turned off, but by the mirror effect of the output transistor N1, An off transition period TT2 (= time t21 to t22) in which the decrease temporarily stagnates is shown.

  The switch voltage Vsw increases linearly during the off-transition period TT2, but the linearity is lost in other periods (= before time t21 and after time t22). Switching loss occurs (see hatched area in the figure).

  For example, before time t21, as a result of the on-resistance Ron of the output transistor N1 increasing before reaching the off-transition period TT2 with the decrease of the gate signal S4, the switch voltage Vsw is changed from the low level (≈ground voltage GND). The state of rising is depicted. In such a situation, the amount of voltage drop at the output transistor N1 becomes large, which becomes a switching loss. Such switching loss becomes more prominent as the Ron characteristic of the output transistor N1 (see the upper stage of FIG. 4 described above) becomes dull.

  One method for reducing the switching loss is to increase the current capability of the driver 12D and change the gate signal S4 (and thus the switch voltage Vsw) more steeply. However, if the switch voltage Vsw is changed too steeply, unintentional ringing or noise increases. Thus, since the reduction of switching loss and the reduction of ringing or noise are in a trade-off relationship, the current capability of the driver 12D cannot always be increased. Below, 2nd Embodiment which can eliminate said trade-off is proposed.

<Switching power supply circuit (second embodiment)>
FIG. 8 is a circuit diagram showing a second embodiment of the switching power supply circuit 100. The switching power supply circuit 100 of the present embodiment is characterized in that the driver 12D is newly devised while being based on the first embodiment (FIG. 2). Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 2, and redundant descriptions are omitted. In the following, the characteristic portions of the present embodiment are mainly described.

  The driver 12D has a function of monitoring the gate signal S4 (or the switch voltage Vsw) and changing its current capability. More specifically, the driver 12D generates the gate signal S4 with the first current capability in the linear region of the switch voltage Vsw, and more than the first current capability in at least a part of the nonlinear region of the switch voltage Vsw. The gate signal S4 is generated with a high second current capability. Hereinafter, a specific circuit configuration for realizing this function and the technical significance of implementing this function will be described in detail.

<Driver (first embodiment)>
FIG. 9 is a circuit diagram showing a first embodiment of the driver 12D. The driver 12D of the present embodiment includes a gate signal generation unit A10 and an enable control unit A20.

  The gate signal generation unit A10 includes buffers A11 and A12 connected in parallel to each other between the input terminal of the pulse width modulation signal S3 and the output terminal of the gate signal S4, and using these, the gate signal is generated from the pulse width modulation signal S3. S4 is generated.

  The buffer A11 always performs an output operation. Note that the slew rate of the switch voltage Vsw can be appropriately adjusted according to the current capability of the buffer A11.

  The buffer A12 is a 3-state buffer in which output operation is enabled / disabled according to the control signal SA10. For example, the buffer A12 is enabled when the control signal SA10 is at a low level, and disabled when the control signal SA10 is at a high level.

  Accordingly, when the buffer A12 is disabled, the gate signal S4 is generated only with the current capability of the buffer A11 (= corresponding to the first current capability). On the other hand, when the buffer A12 is enabled, the gate signal S4 is generated with the current capability (= corresponding to the second current capability) obtained by adding the current capabilities of both the buffers A11 and A12. The current capabilities of the buffers A11 and A12 may be the same or different.

  The enable control unit A20 controls the buffer A12 by monitoring the gate signal S4 (or the switch voltage Vsw) and generating the control signal SA10.

  FIG. 10 is a timing chart (corresponding to an enlarged view of the vicinity of time t1 in FIG. 5) showing the switching loss reduction at the time of ON transition of the output transistor N1. The voltage Vsw (broken line) and the control signal SA10 are depicted.

  As described above, the gate signal S4 does not increase uniformly from the low level (≈ground voltage GND) to the high level (≈input voltage Vi) when the output transistor N1 is turned on. Due to the mirror effect of the output transistor N1, an on-transition period TT1 (= time t31 to t32) in which the rise temporarily stagnates is exhibited.

  The switch voltage Vsw decreases linearly during the on-transition period TT1, but the linearity is lost during other periods (= before time t31 and after time t32). In the example of this figure, the time before time t31 corresponds to the nonlinear region (11) of the switch voltage Vsw, the times t31 to t32 correspond to the linear region (12) of the switch voltage Vsw, and the nonlinearity of the switch voltage Vsw after time t32. Corresponds to region (13).

  Here, the enable control unit A20 performs the enable control of the buffer A12 by comparing the gate signal S4 or the switch voltage Vsw with a predetermined threshold voltage and generating the control signal SA10 according to the comparison result.

  For example, the enable control unit A20 compares the gate signal S4 with the threshold voltages Vth1L and Vth1H. When S4 <Vth1L, or when Vth1H ≦ S4, the control signal SA10 is set to the low level, and Vth1L ≦ S4 < What is necessary is just to comprise so that control-signal SA10 may be made into a high level when it is Vth1H.

  In the case of adopting the above configuration, the threshold voltage Vth1L may be appropriately set to a voltage value at which the rise of the gate signal S4 starts to stagnate (= voltage value at which the on-transition period TT1 starts). The threshold voltage Vth1H may be set as appropriate to a voltage value at which the stagnation of the gate signal S4 is resolved and starts to rise again (= voltage value at which the on-transition period TT1 ends).

  Alternatively, the enable control unit A20 compares the switch voltage Vsw with the threshold voltages Vth2L and Vth2H, and when Vsw <Vth2L, or when Vth2H ≦ Vsw, sets the control signal SA10 to the low level, and Vth2L ≦ Vsw < The control signal SA10 may be set to a high level when Vth2H.

  In the case of adopting the above configuration, the threshold voltage Vth2H may be appropriately set to a voltage value at which the switch voltage Vsw shifts from the nonlinear region (11) to the linear region (12). The threshold voltage Vth2L may be appropriately set to a voltage value at which the switch voltage Vsw shifts from the linear region (12) to the nonlinear region (13).

  By adopting any one of the above configurations, the buffer A12 is enabled in the nonlinear regions (11) and (13) of the switch voltage Vsw, so that the current capability (= The gate signal S4 is generated in the second current capability. Therefore, in the nonlinear regions (11) and (13) of the switch voltage Vsw, the rise of the gate signal S4 is steeper than in the first embodiment (FIG. 6).

  As a result, in the non-linear region (11) of the switch voltage Vsw, the switch voltage Vsw can be lowered more quickly from the high level (≈output voltage Vo). Further, in the non-linear region (13) of the switch voltage Vsw, the switch voltage Vsw can be pulled down to the low level (≈ground voltage GND) more quickly. Therefore, it is possible to reduce the switching loss that occurs in the nonlinear regions (11) and (13) of the switch voltage Vsw as compared with the first embodiment (FIG. 6). Further, since the timing at which the output transistor N1 is fully turned on is advanced, the timing at which the detection of the switch current Is is started can also be advanced.

  On the other hand, since the buffer A12 is disabled in the linear region (12) of the switch voltage Vsw, the gate signal S4 is generated only with the current capability of the buffer A11 (= corresponding to the first current capability). Therefore, in the linear region (12) of the switch voltage Vsw, the switch voltage Vsw decreases relatively slowly over the same ON transition period TT1 as in the first embodiment (FIG. 6). No ringing or noise increases.

  FIG. 11 is a timing chart (corresponding to an enlarged view of the vicinity of time t2 in FIG. 5) showing switching loss reduction when the output transistor N1 is turned off. The gate signal S4 (solid line) and the switch are sequentially displayed from the top of the drawing. The voltage Vsw (broken line) and the control signal SA10 are depicted.

  As described above, the gate signal S4 does not uniformly decrease from the high level (≈input voltage Vi) to the low level (≈ground voltage GND) when the output transistor N1 is turned off. Due to the mirror effect of the output transistor N1, an off-transition period TT2 (= time t41 to t42) in which the decrease temporarily stagnates is exhibited.

  The switch voltage Vsw increases linearly during the off-transition period TT2, but the linearity is lost during other periods (= before time t41 and after time t42). In the example of this figure, the time before time t41 corresponds to the non-linear region (21) of the switch voltage Vsw, the times t41 to t42 correspond to the linear region (22) of the switch voltage Vsw, and the non-linearity of the switch voltage Vsw after time t42. This corresponds to the region (23).

  Here, the enable control unit A20 performs the enable control of the buffer A12 by comparing the gate signal S4 or the switch voltage Vsw with a predetermined threshold voltage and generating the control signal SA10 according to the comparison result.

  For example, the enable control unit A20 compares the gate signal S4 with the threshold voltages Vth3L and Vth3H. When S4 <Vth3L or when Vth3H ≦ S4, the enable control unit A20 sets the control signal SA10 to the low level, and Vth3L ≦ S4 < What is necessary is just to comprise so that control-signal SA10 may be made into a high level when it is Vth3H.

  In the case of adopting the above configuration, the threshold voltage Vth3H may be appropriately set to a voltage value at which the decrease in the gate signal S4 starts to stagnate (= voltage value at which the off transition period TT2 starts). The threshold voltage Vth3L may be set as appropriate to a voltage value at which the stagnation of the gate signal S4 is resolved and starts to decrease again (= voltage value at which the off transition period TT2 ends).

  Alternatively, the enable control unit A20 compares the switch voltage Vsw with the threshold voltages Vth4L and Vth4H, and when Vsw <Vth4L, or when Vth4H ≦ Vsw, sets the control signal SA10 to the low level, and Vth4L ≦ Vsw < The control signal SA10 may be set to a high level when Vth4H.

  Note that when the above configuration is adopted, the threshold voltage Vth4L may be appropriately set to a voltage value at which the switch voltage Vsw shifts from the nonlinear region (21) to the linear region (22). Further, the threshold voltage Vth4H may be appropriately set to a voltage value at which the switch voltage Vsw shifts from the linear region (22) to the nonlinear region (23).

  By adopting any one of the above configurations, the buffer A12 is enabled in the nonlinear regions (21) and (23) of the switch voltage Vsw, so that the current capability (= The gate signal S4 is generated in the second current capability. Therefore, in the nonlinear regions (21) and (23) of the switch voltage Vsw, the falling of the gate signal S4 is steeper than in the first embodiment (FIG. 7).

  As a result, in the non-linear region (21) of the switch voltage Vsw, the switch voltage Vsw can be pulled up from the low level (≈ground voltage GND) more quickly. Further, in the nonlinear region (23) of the switch voltage Vsw, the switch voltage Vsw can be raised to a high level (≈output voltage Vo) more quickly. Therefore, it is possible to reduce the switching loss that occurs in the nonlinear regions (21) and (23) of the switch voltage Vsw as compared with the first embodiment (FIG. 7).

  On the other hand, since the buffer A12 is disabled in the linear region (22) of the switch voltage Vsw, the gate signal S4 is generated only with the current capability of the buffer A11 (= corresponding to the first current capability). Therefore, in the linear region (22) of the switch voltage Vsw, the switch voltage Vsw rises relatively slowly over the same off transition period TT2 as in the first embodiment (FIG. 7). No ringing or noise increases.

  10 and 11, the nonlinear region (11) and (13) of the switch voltage Vsw when the output transistor N1 is turned on, and the nonlinear region (21) of the switch voltage Vsw when the output transistor N1 is turned off. In each of (23) and (23), the current capability of the driver 12D is increased. However, it is not always necessary to increase the current capability of the driver 12D in all nonlinear regions, and the driver 12D is required to reduce the switching loss. It is sufficient to increase the current capacity of the.

  FIG. 12 is a circuit diagram illustrating a configuration example of the enable control unit A20. The enable control unit A20 of this configuration example includes a comparator A21 and resistors A22 to A25 (resistance values: RA22 to RA25).

  The resistors A22 and A23 are connected in series between the application end of the input voltage Vi and the ground end, and output a threshold voltage Va (= {RA23 / (RA22 + RA23)} × Vi) from a connection node between them. .

  The resistors A24 and A25 are connected in series between the application terminal of the gate signal S4 and the ground terminal, and the divided gate signal Vb (= {RA25 / (RA24 + RA25)} × S4) is obtained from the connection node between them. Output.

  The comparator A21 compares the threshold voltage Va input to the non-inverting input terminal (+) and the divided gate signal Vb input to the inverting input terminal (−) to generate the control signal SA10. The control signal SA10 is at a low level when the divided gate signal Vb is higher than the threshold voltage Va, and is at a high level when the divided gate signal Vb is lower than the threshold voltage Va.

  For example, referring to FIG. 10, the resistance values of the resistors A22 to A25 are appropriately adjusted so that Vb <Va when S4 <Vth1H and Vb ≧ Va when S4 ≧ Vth1H. Thus, the logic level of the control signal SA10 can be appropriately switched between the linear region (12) and the nonlinear region (13).

  Further, for example, referring to FIG. 11, the resistance values of the resistors A22 to A25 are appropriately set so that Vb <Va when S4 <Vth3H and Vb ≧ Va when S4 ≧ Vth3H. By adjusting, the logic level of the control signal SA10 can be appropriately switched between the non-linear region (21) and the linear region (22).

  In order to appropriately switch the logic level of the control signal SA10 between the nonlinear region (11) and the linear region (12) or between the linear region (22) and the nonlinear region (23), a comparator is used. The resistance values of the resistors A22 to A25 may be adjusted as appropriate after reversing the input polarity of A21.

  FIG. 13 is a circuit diagram showing a specific example of the driver 12D. The driver 12D of this specific example includes a bootstrap unit BS in addition to the gate signal generation unit A10 and the enable control unit A20 described above. Further, with the implementation of the circuit, some changes have been made to the configurations of the gate signal generation unit A10 and the enable control unit A20 with respect to FIGS. 9 and 12 described above. Hereinafter, each will be described in detail.

  Bootstrap unit BS includes a diode BS1 and a capacitor BS2. The anode of the diode BS1 is connected to the application terminal for the input voltage Vi. The cathode of the diode BS1 and the first terminal of the capacitor BS2 are connected to the output terminal of the bootstrap voltage VB. The second end of the capacitor BS2 is connected to the application end of the switch voltage Vsw. With this configuration, the bootstrap voltage VB is generated by adding the switch voltage Vsw to the voltage across the capacitor BS2 (= Vi−Vf, where Vf is the forward voltage drop of the diode BS1). Note that the bootstrap unit BS may be formed using discrete components in the same manner as the switching output unit 110.

  The gate signal generation unit A10 includes inverters A13 and A14, a P-channel MOS field effect transistor A15, and an N-channel MOS field effect transistor A16.

  The inverters A13 and A14 are connected in parallel to each other between the input terminal of the pulse width modulation signal S3 and the gates of the transistors A15 and A16. The source of the transistor A15 is connected to the application terminal for the input voltage Vi. The drains of the transistors A15 and A16 are connected to the gate of the output transistor N1. The source of the transistor A16 is connected to the ground terminal.

  The inverter A13 always performs an output operation. On the other hand, the inverter A14 is a three-state inverter in which output operation is enabled / disabled according to the control signal SA10. For example, the inverter A14 is enabled when the control signal SA10 is at a low level, and disabled when the control signal SA10 is at a high level.

  The enable control unit A20 includes a resistor A26 and a P-channel MOS field effect transistor A27 in addition to the comparator A21 and the resistors A22 to A25. Also, the connection relationship between the components is slightly different from that of FIG. This will be specifically described below.

  The resistor A26, the resistor A22, and the resistor A23 are connected in series between the application terminal of the input voltage Vi and the internal power supply, and output the threshold voltage Vc from a connection node between the resistor A22 and the resistor A23.

  The resistors A24 and A25 are connected in series between the application end of the bootstrap voltage VB and the internal power supply, and output the divided bootstrap voltage Vd from the connection node between them. Note that the bootstrap voltage VB varies according to the switch voltage Vsw. Therefore, the divided bootstrap voltage Vd also varies according to the switch voltage Vsw.

  The comparator A21 compares the threshold voltage Vc input to the inverting input terminal (−) and the divided bootstrap voltage Vd input to the non-inverting input terminal (+) to generate the control signal SA10. The control signal SA10 is at a high level when the divided bootstrap voltage Vd is higher than the threshold voltage Vc, and is at a low level when the divided bootstrap voltage Vd is lower than the threshold voltage Vc.

  For example, referring to FIG. 10, the resistance values of the resistors A22 to A26 are appropriately adjusted so that Vd <Vc when Vsw <Vth2L and Vd ≧ Vc when Vsw ≧ Vth2L. Thus, the logic level of the control signal SA10 can be appropriately switched between the linear region (12) and the nonlinear region (13).

  The transistor A27 is connected in parallel to the resistor A26, and the control signal SA10 is input to the gate thereof. Accordingly, the transistor A27 is turned off when the control signal SA10 is at a high level, and the transistor A27 is turned on when the control signal SA10 is at a low level. When the transistor A27 is off, the resistor A26 functions as a part of the voltage dividing circuit, so that the voltage dividing ratio is lowered and the threshold voltage Vc is lowered. On the contrary, when the transistor A27 is on, the resistor A26 does not function as a part of the voltage dividing circuit, so that the voltage dividing ratio is increased and the threshold voltage Vc is raised. Thus, by adding the resistor A26 and the transistor A27, it is possible to impart hysteresis characteristics to the threshold voltage Vc.

<Driver (second embodiment)>
FIG. 14 is a circuit diagram showing a second embodiment of the driver 12D. The driver 12D of the present embodiment includes a gate signal generation unit A30 and an enable control unit A40.

  The gate signal generation unit A30 includes i (i ≧ 3) buffers A31 to A3i connected in parallel to each other between the input end of the pulse width modulation signal S3 and the output end of the gate signal S4. A gate signal S4 is generated from the pulse width modulation signal S3.

  Buffer A3 * (where * = 1 to i, and so on) is a three-state buffer in which output operation is enabled / disabled in response to control signal SA30 (*). For example, the buffer A3 * is enabled when the control signal SA30 (*) is at a low level, and disabled when the control signal SA30 (*) is at a high level.

  Accordingly, among j buffers A31 to A3i, if j buffers (where 1 ≦ j <i) are enabled and the remaining buffers are disabled, j current capacity (= The gate signal S4 is generated at the first current capability). When k (where j <k ≦ 1) buffers are enabled and the remaining buffers are disabled among the buffers A31 to A3i, the k current capacity (= The gate signal S4 is generated in the second current capability. The current capabilities of the buffers A31 to A3i may be the same or different.

  The enable control unit A40 individually performs enable control of the buffers A31 to A3i by monitoring the gate signal S4 (or switch voltage Vsw) and generating control signals SA30 (1) to SA30 (i), respectively. For example, the enable control unit A40 enables the j buffers in the linear region of the switch voltage Vsw and enables the k buffers in the non-linear region of the switch voltage Vsw (control signals SA30 (1) to SA30 ( i) is generated respectively.

  With the driver 12D of the present embodiment, the first current capability and the second current capability can be adjusted arbitrarily as compared with the previous first embodiment (FIG. 9 or FIG. 13). Note that it is desirable that the enable numbers j and k of the buffers A31 to A3i can be arbitrarily adjusted by the user, for example, by register settings.

  In the driver 12D of the present embodiment, the first current capability in the linear region of the switch voltage Vsw can be periodically changed. When it is desired to have such a function, the enable control unit A40 sets the enable number (j ± x) in the linear region of the switch voltage Vsw so as to have a predetermined fluctuation range ± x with the enable number j as a reference value. What is necessary is just to set it as the structure changed periodically.

  For example, when j = 2 and x = 1, the number of buffers A31 to A3i enabled (j ± x) in the linear region of the switch voltage Vsw is 1 → 2 → 3 → 2 → for each switching period → It changes periodically such as 1 → 2 → 3, or 1 → 2 → 3 → 1 → 2 → 3.

  Thus, since the frequency of the switching noise can be dispersed by periodically changing the first current capability in the linear region of the switch voltage Vsw, it is possible to reduce adverse effects on the peripheral circuits. .

  In the second embodiment, the driver 12D for driving the output transistor N1 is provided with a variable current capability function. However, when the switching output unit 110 is of the synchronous rectification type, the driver for driving the synchronous rectification transistor is used. However, it is possible to provide the same function as necessary.

<Switching Power Supply Circuit (Third Embodiment)>
FIG. 15 is a circuit diagram showing a third embodiment of the switching power supply circuit 100. The present embodiment is characterized in that the output format of the switching output unit 110 is changed to a step-down type while being based on the second embodiment (FIG. 8). Therefore, the same components as those in the second embodiment are denoted by the same reference numerals as those in FIG. 8, and redundant descriptions are omitted. In the following, the characteristic portions of the present embodiment are mainly described.

  The switching output unit 110 drives the coil current IL using the output transistor P1 to obtain a desired output voltage Vo (for example, corresponding to the logic power supply voltage VDD) from the input voltage Vi (for example, corresponding to the input voltage VI). A step-down switching output stage to be generated, which includes an output transistor P1 (in the example of this figure, a P-channel MOS field effect transistor), a coil L2, a rectifier diode D2, and an output capacitor Co2.

  The source of the output transistor P1 is connected to the application terminal for the input voltage Vi. The drain of the output transistor P1 is connected to the first end of the coil L2 and the cathode of the rectifier diode D2. The gate of the output transistor P1 is connected to the output terminal of the switching control unit 120 (the output terminal of the gate signal S4). The anode of the rectifier diode D2 is connected to the ground terminal. The second end of the coil L2 is connected to the output end of the output voltage Vo and the first end of the output capacitor Co2. The second end of the output capacitor Co2 is connected to the ground end.

  As a rectification method for the switching output unit 110, a synchronous rectification method may be employed instead of the diode rectification method. In that case, the rectifier diode D2 may be replaced with a synchronous rectifier transistor, which may be turned on / off complementarily with the output transistor P1.

  As described above, the output format of the switching output unit 110 is not limited to the step-up type in the first embodiment (FIG. 2), and a step-down type may be employed. Moreover, although illustration is omitted, it is arbitrary also about making the output format of the switching output part 110 into a buck-boost type.

  FIG. 16 is a timing chart showing switching loss reduction at the time of ON transition of the output transistor P1, in which the gate signal S4 (solid line) and the switch voltage Vsw (broken line) are depicted.

  The gate signal S4 does not decrease uniformly from the high level (≈input voltage Vi) to the low level (≈ground voltage GND) when the output transistor P1 is turned on, but by the mirror effect of the output transistor P1. An ON transition period TT3 (= time t51 to t52) in which the decrease temporarily stagnates is exhibited.

  The switch voltage Vsw rises linearly during the on-transition period TT3, but the linearity is lost during other periods (= before time t51 and after time t52). In the example of this figure, the time before time t51 corresponds to the nonlinear region (31) of the switch voltage Vsw, the times t51 to t52 correspond to the linear region (32) of the switch voltage Vsw, and the nonlinearity of the switch voltage Vsw after time t52. This corresponds to the region (33).

  Here, the driver 12D compares the gate signal S4 with the threshold voltages Vth5L and Vth5H. When Vth5L ≦ S4 <Vth5H, the driver 12D generates the gate signal S4 with the first current capability, and S4 <Vth5L or Vth5H ≦ What is necessary is just to comprise so that the gate signal S4 may be produced | generated by 2nd current capability larger than 1st current capability when it is S4.

  In the case of adopting the above configuration, the threshold voltage Vth5H may be appropriately set to a voltage value at which the decrease of the gate signal S4 starts to stagnate (= voltage value at which the on-transition period TT3 starts). Further, the threshold voltage Vth5L may be appropriately set to a voltage value at which the stagnation of the gate signal S4 is resolved and starts to decrease again (= voltage value at which the on-transition period TT3 ends).

  Alternatively, the driver 12D compares the switch voltage Vsw with the threshold voltages Vth6L and Vth6H, and generates the gate signal S4 with the first current capability when Vth6L ≦ Vsw <Vth6H, and Vsw <Vth6L or Vth4H ≦ Vsw. In this case, the gate signal S4 may be generated with a second current capability larger than the first current capability.

  Note that when the above configuration is adopted, the threshold voltage Vth6L may be appropriately set to a voltage value at which the switch voltage Vsw shifts from the nonlinear region (31) to the linear region (32). The threshold voltage Vth6H may be appropriately set to a voltage value at which the switch voltage Vsw shifts from the linear region (32) to the nonlinear region (33).

  By adopting any one of the above configurations, the fall of the gate signal S4 becomes steep in the nonlinear regions (31) and (33) of the switch voltage Vsw. As a result, in the non-linear region (31) of the switch voltage Vsw, the switch voltage Vsw can be pulled up from the low level (≈ground voltage GND) more quickly. In the non-linear region (33) of the switch voltage Vsw, the switch voltage Vsw can be raised to the high level (≈input voltage Vi) more quickly. Accordingly, it is possible to reduce the switching loss that occurs in the nonlinear regions (31) and (33) of the switch voltage Vsw. Further, since the timing at which the output transistor P1 is fully turned on is advanced, the timing at which the detection of the switch current Is is started can also be advanced.

  On the other hand, in the linear region (32) of the switch voltage Vsw, the gate signal S4 is generated with the first current capability smaller than the second current capability. Therefore, since the switch voltage Vsw rises relatively slowly, unintended ringing and noise increase can be avoided.

  FIG. 17 is a timing chart showing the switching loss reduction when the output transistor P1 is turned off, in which the gate signal S4 (solid line) and the switch voltage Vsw (broken line) are depicted.

  The gate signal S4 does not rise uniformly from the low level (≈ground voltage GND) to the high level (≈input voltage Vi) when the output transistor P1 is turned off, but by the mirror effect of the output transistor P1, It presents an off-transition period TT4 (= time t61 to t62) in which the rise temporarily stagnates.

  The switch voltage Vsw decreases linearly during the off-transition period TT4, but the linearity is lost during other periods (= before time t61 and after time t62). In the example of this figure, the time before time t61 corresponds to the non-linear region (41) of the switch voltage Vsw, the time t61 to t62 corresponds to the linear region (42) of the switch voltage Vsw, and the time after t62 is the non-linearity of the switch voltage Vsw. This corresponds to the region (43).

  Here, the driver 12D compares the gate signal S4 with the threshold voltages Vth7L and Vth7H. When Vth7L ≦ S4 <Vth7H, the driver 12D generates the gate signal S4 with the first current capability, and S4 <Vth7L or Vth7H ≦ What is necessary is just to comprise so that the gate signal S4 may be produced | generated by 2nd current capability larger than 1st current capability when it is S4.

  In the case of adopting the above configuration, the threshold voltage Vth7L may be appropriately set to a voltage value at which the rise of the gate signal S4 starts to stagnate (= voltage value at which the off transition period TT4 starts). The threshold voltage Vth7H may be set as appropriate to a voltage value at which the stagnation of the gate signal S4 is resolved and starts to rise again (= voltage value at which the off transition period TT4 ends).

  Alternatively, the driver 12D compares the switch voltage Vsw with the threshold voltages Vth8L and Vth8H, and generates a gate signal S4 with the first current capability when Vth8L ≦ Vsw <Vth8H, and Vsw <Vth8L or Vth8H ≦ Vsw. In this case, the gate signal S4 may be generated with a second current capability larger than the first current capability.

  In the case of adopting the above configuration, the threshold voltage Vth8H may be appropriately set to a voltage value at which the switch voltage Vsw shifts from the nonlinear region (41) to the linear region (42). The threshold voltage Vth8L may be appropriately set to a voltage value at which the switch voltage Vsw shifts from the linear region (42) to the nonlinear region (43).

  By adopting any of the above configurations, the fall of the gate signal S4 becomes steep in the nonlinear regions (41) and (43) of the switch voltage Vsw. As a result, in the non-linear region (41) of the switch voltage Vsw, the switch voltage Vsw can be lowered from the high level (≈input voltage Vi) more quickly. Further, in the non-linear region (43) of the switch voltage Vsw, the switch voltage Vsw can be lowered more quickly to the low level (≈ground voltage GND). Therefore, it is possible to reduce the switching loss that occurs in the nonlinear regions (41) and (43) of the switch voltage Vsw.

  On the other hand, in the linear region (42) of the switch voltage Vsw, the gate signal S4 is generated with the first current capability smaller than the second current capability. Therefore, since the switch voltage Vsw decreases relatively slowly, unintended ringing and noise increase can be avoided.

  16 and 17, the non-linear regions (31) and (33) of the switch voltage Vsw when the output transistor P1 is on, and the non-linear region (41) of the switch voltage Vsw when the output transistor P1 is off. In each of (43) and (43), the current capability of the driver 12D is increased. However, it is not always necessary to increase the current capability of the driver 12D in all nonlinear regions, and the driver 12D is required to reduce the switching loss. It is sufficient to increase the current capacity of the.

<Driver (third embodiment)>
FIG. 18 is a circuit diagram showing a third embodiment of the driver 12D. The driver 12D of this embodiment includes buffers B11 and B12, P-channel MOS field effect transistors B13 to B15, and an N-channel MOS field effect transistor B16.

  Both the input end of the buffer B11 and the input end of the buffer B12 are connected to the input end of the pulse width modulation signal S3.

  The source and back gate of the transistor B13 are connected to the application terminal for the input voltage Vi. The drain of the transistor B13 is connected to the gate of the output transistor P1. The gate of the transistor B13 is connected to the output terminal of the buffer B11 (= corresponding to the application terminal of the pulse width modulation signal S3).

  The source and back gate of the transistor B14 are connected to the application terminal for the input voltage Vi. The gate of the transistor B14 is connected to the output terminal of the buffer B11.

  The source of the transistor B15 is connected to the drain of the transistor B14. The gate and drain of the transistor B15 are connected to the gate of the output transistor P1. The back gate of the transistor B15 is connected to the application terminal for the input voltage Vi.

  The drain of the transistor B16 is connected to the gate of the output transistor P1. The source and back gate of the transistor B16 are connected to the ground terminal. The gate of the transistor B16 is connected to the output terminal of the buffer B12 (= corresponding to the application terminal of the pulse width modulation signal P3).

  In the driver 12D of this configuration example, when the pulse width modulation signal S3 is at a high level, the transistor B13 is turned off and the transistor B16 is turned on. Therefore, the gate signal S4 becomes low level, and the output transistor P1 is turned on. At this time, since the transistor B14 is turned off, the current path from the application end of the input voltage Vi to the gate of the output transistor P1 through the transistors B14 and B15 is cut off. This state corresponds to a state in which the current capability of the driver 12D is set to “first current capability”.

  Thereafter, when the pulse width modulation signal S3 falls from the high level to the low level, the transistor B13 is turned on and the transistor B16 is turned off. Accordingly, the gate signal S4 is raised from the low level to the high level, and the output transistor P1 is turned off.

  At this time, since the transistor B14 is turned on, the input voltage Vi is applied to the source of the transistor B15. On the other hand, the gate signal S4 of the output transistor P1 is applied to the gate and drain of the transistor B15. Therefore, the gate-source voltage of the transistor B15 matches the voltage value (= Vi−S4) obtained by subtracting the gate signal S4 from the input voltage Vi, and is higher than the on-threshold voltage Vth (B15) of the transistor B15. Transistor B15 is turned on.

  That is, while the gate signal S4 rises from the low level to the high level, the current from the application end of the input voltage Vi to the gate of the output transistor P1 through the transistor B13 while S4 <Vi−Vth (B15). In addition to the path, the current path from the application end of the input voltage Vi to the gate of the output transistor P1 through the transistors B14 and B15 is brought into conduction. This state corresponds to a state in which the current capability of the driver 12D is increased to the “second current capability”.

  Thus, it can be said that the driver 12D of this configuration example is configured to compare the gate signal S4 and the threshold voltage (Vi−Vth (B15)) and switch the current capability. For example, referring to FIG. 17, the threshold voltage (Vi−Vth (B15)) corresponds to the threshold voltage Vth7L.

  On the other hand, when the output transistor P1 is turned off, the voltage value at which the stagnation of the gate signal S4 is resolved and starts to rise again (= the voltage value at which the off transition period TT4 ends) is from the input voltage Vi to the on threshold voltage of the output transistor P1. It can be obtained as a voltage value obtained by subtracting Vth (P1) (= Vi−Vth (P1)).

  Therefore, the driver 12D is connected between the nonlinear region (41) and the linear region (42) by keeping the pair characteristics of the output transistor P1 and the transistor B15 so that Vth (P1) = Vth (B15). It is possible to appropriately switch the current capability of the.

<Application to tablet devices>
FIG. 19 is an external view of a tablet terminal. The tablet terminal X has a liquid crystal display X1 having a touch panel function. The liquid crystal display X1 is an example of the liquid crystal display device 1 described so far, and the above-described switching power supply circuit 100 can be suitably used as the power supply means. However, the mounting target of the liquid crystal display device 1 is not limited to the tablet terminal, and can be mounted on various electronic devices (such as a notebook computer).

<Other variations>
The various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. That is, the above-described embodiment is to be considered in all respects as illustrative and not restrictive, and the technical scope of the present invention is indicated not by the description of the above-described embodiment but by the scope of the claims. It should be understood that all modifications that fall within the meaning and range equivalent to the terms of the claims are included.

  The switching power supply circuit disclosed in this specification can be used as a power supply means for an application (such as a battery-driven electronic device) that requires power saving.

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 10 Liquid crystal drive device 11 System power supply part 12 Timing control part 13 Level shifter 14 Gate driver 15 Source driver 16 Gamma voltage generation part 17 Common voltage generation part 20 Liquid crystal display panel 100 Switching power supply circuit 110 Switching output part 120 Switching control part 121 Digital / Analog Conversion Unit 122 Feedback Voltage Generation Unit 123 Error Amplifier 124 Phase Compensation Unit 125 Clock Signal Generation Unit 126 Set Signal Generation Unit 127 Maximum Duty Setting Unit 128 Reference Slope Voltage Generation Unit 129 Voltage Addition Unit 12A Comparator 12B OR Gate 12C RS Flip-flop 12D driver N1 output transistor (N-channel MOS field effect transistor)
P1 output transistor (P-channel MOS field effect transistor)
L1, L2 Coil D1, D2 Rectifier diode Co1, Co2 Output capacitor Rs Sense resistor R1-R3 Resistor C1 Capacitor A10, A30 Gate signal generator A11, A12, A31-A3i Buffer A13, A14 Inverter A15 P-channel MOS field effect transistor A16 N channel type MOS field effect transistor A20, A40 Enable control part A21 Comparator A22-A26 Resistance A27 P channel type MOS field effect transistor BS Bootstrap part BS1 Diode BS2 Capacitor B11, B12 Buffer B13-B15 P channel type MOS field effect transistor B16 N-channel MOS field effect transistor X Tablet terminal X1 Liquid crystal display

Claims (10)

A switching output unit that generates an output voltage from an input voltage using an output transistor;
A switching control unit for performing on / off control of the output transistor;
Have
The switching control unit includes a driver that generates a gate signal of the output transistor,
The driver generates the gate signal with a first current capability in a linear region of the switch voltage appearing at one end of the output transistor, and generates at least a part of the nonlinear region of the switch voltage from the first current capability. Generating the gate signal with a higher second current capability,
A switching power supply circuit. The driver is
A gate signal generation unit that generates the gate signal using a plurality of buffers connected in parallel to each other;
An enable control unit for enabling control of each buffer;
The switching power supply circuit according to claim 1, comprising:   3. The switching power supply circuit according to claim 2, wherein the enable control unit performs enable control of each buffer by comparing the gate signal or the switch voltage with a predetermined threshold voltage.   4. The switching power supply circuit according to claim 1, wherein the driver periodically changes the first current capability. 5. The output transistor is a PMOSFET having a source connected to an input voltage application terminal,
The driver is
A first PMOSFET having a source connected to the input voltage application end, a drain connected to the gate of the output transistor, and a gate connected to the pulse signal application end;
A second PMOSFET having a source connected to the input voltage application end and a gate connected to the pulse signal application end;
A third PMOSFET having a source connected to the drain of the second PMOSFET and a gate and drain connected to the gate of the output transistor;
An NMOSFET having a drain connected to the gate of the output transistor, a source connected to the ground terminal, and a gate connected to the application terminal of the pulse signal;
The switching power supply circuit according to claim 1, comprising: The switching controller is
An error amplifier that generates an error voltage according to a difference value between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage;
A slope voltage generator for generating a slope voltage;
A comparator that determines the on-duty of the output transistor by comparing the error voltage and the slope voltage;
A set signal generator for generating a set signal pulse at a predetermined pulse period;
An RS flip-flop that receives an input of a reset signal according to a comparison result of the set signal and the comparator and outputs a pulse width modulation signal;
Further including
The switching power supply circuit according to any one of claims 1 to 5, wherein the driver receives the input of the pulse width modulation signal and generates the gate signal. The switching controller is
A maximum duty setting unit for generating a pulse of a maximum duty setting signal when a maximum on-time has elapsed since a pulse was generated in the set signal;
A logic gate for logically synthesizing the comparison signal of the comparator and the maximum duty setting signal to generate the reset signal;
The switching power supply circuit according to claim 6, further comprising:   The switching power supply circuit according to any one of claims 1 to 7, wherein the switching output unit is a step-up type, a step-down type, or a step-up / step-down type. The switching power supply circuit according to any one of claims 1 to 8,
A driver for receiving a power supply from the switching power supply circuit and driving a load;
A load driving device comprising: A load driving device according to claim 9,
A liquid crystal display panel driven as a load of the load driving device;
A liquid crystal display device comprising:

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