JP2015230585A - Series regulator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a series regulator circuit capable of performing a stable operation regardless of load current.SOLUTION: A series regulator circuit (100) includes: a first differential amplifier circuit (11) in which each of monitor voltage (VM) of an output terminal (OUT) and first reference voltage (VREF1) are supplied to a differential input terminal; an output transistor (MPD) in which a first main electrode is connected to a first power supply terminal (VDD), a second main electrode is connected to an output terminal, and a control electrode is connected to the output terminal (OUT) of the first differential amplifier circuit (11); a second differential amplifier circuit (12) in which one differential input terminal is connected to the output terminal (OUT) of the first differential amplifier circuit (11), and second reference voltage (VREF2) is supplied to the other differential input terminal; a control transistor (MNB) in which the control electrode is connected to an output terminal of the second differential amplifier circuit (12); and a current generation element (RB) which is connected in series with the control transistor (MNB) so as to generate current (IBIAS) flowing from an output terminal to a second power supply terminal.

Description

  The present invention relates to a series regulator circuit, for example, a low-saturation series regulator circuit with a small potential difference between input and output.

  Conventionally, a series regulator circuit is known as a circuit for stably supplying power to a load. In recent years, a low-loss / low-saturation series regulator circuit (hereinafter also referred to as “LDO: Low drop out”) in which the potential difference between the input and output is small has attracted attention. The prior art is disclosed.

T. Wakimoto, “LDO Design Methodology and an Intelligent Power Management Sub-System IC for CDMA Handsets”, IEICE TRANS.ELECTRON., VOL.E93-C, NO.10 OCTOBER 2010.

  However, the series regulator circuit represented by the conventional LDO has a problem that the series regulator circuit becomes unstable depending on the operating state of the load. Hereinafter, this problem will be described in detail with reference to the drawings.

FIG. 26 is a diagram showing a configuration of a conventional series regulator circuit.
The series regulator circuit 90 outputs a constant output voltage VOUT from the output terminal OUT and supplies a load current ILOAD to the load LD. As shown in the figure, the series regulator circuit 90 includes a P-channel output transistor MP9, voltage monitoring resistors R1 and R2, an OP amplifier 91, and an output capacitor COUT.

  FIG. 27 shows an equivalent circuit of the series regulator circuit 90. As shown in the figure, the OP amplifier 91 can be represented by a Gm amplifier 92, a resistor R9, and a capacitor C9. The output transistor MP9 can be represented by parasitic capacitances CGS and CGD, a drain-source resistance RDS, and a P-channel transistor MPX. The load LD can be represented by a constant current source 93.

  As shown in FIG. 27, the series regulator circuit 90 is a two-stage amplifier circuit including an amplifier stage composed of an OP amplifier 91 and an amplifier stage composed of an output transistor MP9, and has two poles. The first pole P1 is generated at the output node OP of the OP amplifier 91, and the second pole P2 is generated at the output terminal OUT (the drain electrode of the output transistor MP800).

FIG. 28 shows the simulation results of the open loop gain characteristics and phase characteristics of the series regulator circuit 90.
In the figure, the horizontal axis represents frequency [Hz], and the vertical axis represents gain [dB] and phase [deg. ] Is represented. Also, the figure shows an open loop gain characteristic 900 and a phase characteristic 901 when the load current ILOAD is 1 μA, and an open loop gain characteristic 910 and a phase characteristic 911 when the load current ILOAD is 40 mA. Yes. Further, in FIG. 28, reference numeral 902 represents the first pole P1 when the load current ILOAD is 1 μA, reference numeral 903 represents the second pole P2 when the load current ILOAD is 1 μA, Reference numeral 912 represents the first pole P1 when the load current ILOAD is 40 mA, and reference numeral 913 represents the second pole P2 when the load current ILOAD is 40 mA.

  As indicated by reference numerals 902 and 912, the first pole P1 is generated in the vicinity of several kHz regardless of the load current ILOAD. However, the second pole P2 occurs near 1 MHz when the load current ILOAD = 1uA as indicated by reference numeral 903, and near 200 MHz when the load current ILOAD = 40 mA as indicated by reference numeral 913. That is, the second pole P2 depends on the load current ILOAD, and the frequency increases as the load current ILOAD increases.

  When the first pole P1 and the second pole P2 are present as in the series regulator circuit 90, the signal phase is shifted by 90 degrees at the first pole P1, and the signal phase is further shifted at the second pole P2. Therefore, the phase of the signal propagating through the negative feedback path of the series regulator circuit 90 is always displaced by 180 degrees. If the gain (amplification factor) of the series regulator circuit 90 is 0 dB or more when the phase of the signal is displaced by 180 degrees, the series regulator circuit 90 becomes unstable and the circuit may oscillate.

  In general, “phase margin” is known as an index for determining the stability of a negative feedback circuit (series regulator circuit). Here, the phase margin is an index defined as “180 + θ”, where θ is the phase at a frequency where the gain is 0 dB. The stability of the negative feedback circuit is ensured as the phase margin increases, and the circuit becomes unstable and the possibility that the circuit oscillates increases as the phase margin approaches zero. In general, a phase margin of 45 degrees or more is required to ensure stable operation of the negative feedback circuit.

FIG. 29 shows the characteristics of the phase margin with respect to the load current of the series regulator circuit 90. In the figure, the vertical axis represents the phase margin [deg. The horizontal axis represents the load current [A].
For example, in the case of the series regulator circuit 800, when the load current ILOAD is 40 mA, the first pole P1 (near several kHz) and the second pole P2 (near 200 MHz) are separated as shown in FIG. Therefore, the phase margin is about 92 degrees as shown in FIG. In contrast, when the load current ILOAD is 1 μA, the first pole P1 (near several kHz) and the second pole P2 (near 1 MHz) are generated at positions close to each other as shown in FIG. As shown, the phase margin is about 8 degrees, which is smaller than 45 degrees.

  As can be understood from FIGS. 28 and 29, in order to increase the phase margin of the series regulator circuit 90, the load current ILOAD, that is, the second pole P2 is separated from the first pole P1 on the frequency axis. It is necessary to increase the current flowing through the output transistor MP9. For example, in order to secure a phase margin of 45 degrees or more in the series regulator circuit 90, it is necessary to flow a load current ILOAD of about 2.3 mA or more.

  However, when the load LD of the series regulator circuit 90 is a CMOS (Complementary Metal Oxide Semiconductor) circuit, the load current ILOAD changes by three digits or more depending on the operating state of the CMOS circuit, so the load current ILOAD is smaller than 2.3 mA. There is a case. Therefore, in the conventional series regulator circuit 90, the phase margin may be smaller than 45 degrees depending on the operating state of the load LD, and the operation of the series regulator circuit 90 may become unstable.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a series regulator circuit capable of stable operation irrespective of load current.

  The series regulator circuit (100 to 800) according to the present invention includes a first power supply terminal (VCC) to which a first DC voltage is supplied and a second power supply to which a second DC voltage lower than the first DC voltage is supplied. A difference including a terminal (VSS), an output terminal (OUT), a resistance voltage dividing circuit (13) connected between the output terminal and the second power supply terminal, and a positive phase input terminal and a negative phase input terminal; The first reference voltage (VREF1) is supplied to one of the differential input terminals, and the voltage (VM) divided by the resistance voltage dividing circuit is supplied to the other differential input terminal. A first differential amplifier circuit (11), a first main electrode is connected to the first power supply terminal, a second main electrode is connected to the output terminal, and a control electrode is an output of the first differential amplifier circuit Output transistors (MPD, MND) connected to the terminals; A differential input terminal pair including a phase input terminal and a reverse phase input terminal, one differential input terminal connected to the output terminal of the first differential amplifier circuit, and the other differential input terminal connected to the first differential input terminal; The second differential amplifier circuit (12, 22, 42, 62, 82) to which a second reference voltage (VREF2) different from the reference voltage is supplied is connected between the output terminal and the second power supply terminal. A current generation circuit (14) for generating a current (IBIAS) flowing from the output terminal to the second power supply terminal in accordance with an output signal of the second differential amplifier circuit, and the current generation circuit is controlled The electrode includes a control transistor (MNB, MPB) connected to an output terminal of the second differential amplifier circuit, and a current generating element (RB, 15) connected in series with the control transistor. .

In the series regulator circuit (200, 400, 600, 800), the second differential amplifier circuit (22, 42, 62, 82) may have a hysteresis characteristic.
In the series regulator circuit (100, 200), the output transistor is a P-channel field effect transistor (MPD), the control transistor is an N-channel field effect transistor (MNB), and the first transistor The voltage divided by the resistor voltage divider circuit is supplied to the positive phase input terminal of the differential amplifier circuit, the first reference voltage is supplied to the negative phase input terminal of the first differential amplifier circuit, and the second The positive phase input terminal of the differential amplifier circuit may be connected to the output terminal of the first differential amplifier circuit, and the second reference voltage may be supplied to the negative phase input terminal of the second differential amplifier circuit.

  In the series regulator circuit (300, 400), the output transistor is an N-channel field effect transistor (MND), the control transistor is an N-channel field effect transistor (MNB), and the first transistor A voltage divided by the resistance voltage dividing circuit is supplied to the negative phase input terminal of the differential amplifier circuit, the first reference voltage is supplied to the positive phase input terminal of the first differential amplifier circuit, and the second The negative phase input terminal of the differential amplifier circuit may be connected to the output terminal of the first differential amplifier circuit, and the second reference voltage may be supplied to the positive phase input terminal of the second differential amplifier circuit.

  In the series regulator circuit (500, 600), the output transistor is an N-channel field effect transistor (MND), the control transistor is a P-channel field effect transistor (MPB), and the first transistor A voltage divided by the resistance voltage dividing circuit is supplied to the negative phase input terminal of the differential amplifier circuit, the first reference voltage is supplied to the positive phase input terminal of the first differential amplifier circuit, and the second The positive phase input terminal of the differential amplifier circuit may be connected to the output terminal of the first differential amplifier circuit, and the second reference voltage may be supplied to the negative phase input terminal of the second differential amplifier circuit.

  In the series regulator circuit (700, 800), the output transistor is a P-channel field effect transistor (MPD), the control transistor is a P-channel field effect transistor (MPB), and the first transistor The voltage divided by the resistor voltage divider circuit is supplied to the positive phase input terminal of the differential amplifier circuit, the first reference voltage is supplied to the negative phase input terminal of the first differential amplifier circuit, and the second The negative phase input terminal of the differential amplifier circuit may be connected to the output terminal of the first differential amplifier circuit, and the second reference voltage may be supplied to the positive phase input terminal of the second differential amplifier circuit.

  In the series regulator circuit, the current generation element may be a resistance element (RB).

  In the series regulator circuit, the current generating element may be a constant current source (15).

  In the above description, the reference numerals with parentheses merely exemplify what are included in the concept of the constituent elements with the reference numerals in the drawings.

  According to the present invention, it is possible to provide a series regulator circuit capable of stable operation regardless of load current.

FIG. 1 is a diagram illustrating a configuration of a series regulator circuit according to the first embodiment. FIG. 2 is a diagram illustrating another configuration example of the series regulator circuit according to the first embodiment. FIG. 3 is a diagram showing the characteristics of the bias current (IBIAS) and the voltage of the main node with respect to the load current of the series regulator circuit according to the first embodiment. FIG. 4 is a diagram illustrating a phase margin characteristic with respect to a load current of the series regulator circuit according to the first embodiment. FIG. 5 is a diagram illustrating a configuration of a series regulator circuit according to the second embodiment. FIG. 6 is a diagram illustrating another configuration example of the series regulator circuit according to the second embodiment. FIG. 7 is a diagram illustrating a configuration of a series regulator circuit according to the third embodiment. FIG. 8 is a diagram illustrating another configuration example of the series regulator circuit according to the third embodiment. FIG. 9 is a diagram showing the characteristics of the bias current and the voltage of the main node with respect to the load current of the series regulator circuit according to the third embodiment. FIG. 10 is a diagram illustrating a phase margin characteristic with respect to a load current of the series regulator circuit according to the third embodiment. FIG. 11 is a diagram illustrating a configuration of a series regulator circuit according to the fourth embodiment. FIG. 12 is a diagram illustrating another configuration example of the series regulator circuit according to the fourth embodiment. FIG. 13 is a diagram illustrating a configuration of a series regulator circuit according to the fifth embodiment. FIG. 14 is a diagram illustrating another configuration example of the series regulator circuit according to the fifth embodiment. FIG. 15 is a diagram illustrating the characteristics of the bias current and the voltage of the main node with respect to the load current of the series regulator circuit according to the fifth embodiment. FIG. 16 is a diagram showing the characteristics of the phase margin with respect to the load current of the series regulator circuit according to the fifth embodiment. FIG. 17 is a diagram illustrating a configuration of a series regulator circuit according to the sixth embodiment. FIG. 18 is a diagram illustrating another configuration example of the series regulator circuit according to the sixth embodiment. FIG. 19 is a diagram illustrating a configuration of a series regulator circuit according to the seventh embodiment. FIG. 20 is a diagram illustrating another configuration example of the series regulator circuit according to the seventh embodiment. FIG. 21 is a diagram showing the characteristics of the bias current and the voltage of the main node with respect to the load current of the series regulator circuit according to the seventh embodiment. FIG. 22 is a diagram illustrating a phase margin characteristic with respect to a load current of the series regulator circuit according to the seventh embodiment. FIG. 23 is a diagram showing a configuration of a series regulator circuit according to the eighth embodiment. FIG. 24 is a diagram illustrating another configuration example of the series regulator circuit according to the eighth embodiment. FIG. 25 is a diagram illustrating a configuration of a series regulator circuit including a constant current source instead of a resistor as a current generating element. FIG. 26 is a diagram showing a configuration of a conventional series regulator circuit. FIG. 27 is a diagram showing an equivalent circuit of a conventional series regulator circuit. FIG. 28 is a diagram showing simulation results of open loop gain characteristics and phase characteristics of a conventional series regulator circuit. FIG. 29 is a diagram showing the characteristics of the phase margin with respect to the load current of the conventional series regulator circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<< Embodiment 1 >>
FIG. 1 shows the configuration of a series regulator circuit according to Embodiment 1 of the present invention.
The series regulator circuit 100 shown in the figure outputs a constant output voltage VOUT from an output terminal OUT and supplies a load current ILOAD to a load LD connected between the output terminal OUT and a ground node. . Examples of the load LD include various circuits such as a digital circuit (CMOS circuit) such as a microcontroller and an analog circuit.

  The series regulator circuit 100 can be realized, for example, as a semiconductor integrated circuit formed on a semiconductor substrate by a known CMOS manufacturing process. The series regulator circuit 100 may be realized as a semiconductor device in which all circuit elements are formed on one chip, or as a semiconductor device having a multi-chip configuration in which some circuit elements are formed on another chip. The configuration of the semiconductor device is not particularly limited.

  Specifically, the series regulator circuit 100 includes differential amplifier circuits 11 and 12, an output transistor MPD, a resistance voltage dividing circuit 13, a current generation circuit 14, a control transistor MNB, and a plurality of external terminals. In the figure, as the external terminals, a first power supply terminal to which a power supply voltage VCC is supplied, a second power supply terminal to which a power supply voltage VSS lower than the power supply voltage is supplied, and an output terminal OUT are shown as an example. ing. Note that reference numerals “VCC” and “VSS” representing power supply voltages also represent a first power supply terminal and a second power supply terminal to which those power supply voltages are supplied. In the following description, the case where the power supply voltage VSS is the ground voltage (0 V) will be described as an example, but is not particularly limited.

  An output capacitor COUT is connected to the output terminal OUT in parallel with the load LD. The output capacitance COUT is, for example, a capacitance component of the load LD (for example, an input capacitance of a CMOS circuit), and is illustrated outside the load LD in FIG. 1 for convenience of explanation. In addition to the capacitance component of the load LD, the output capacitance COUT may include a parasitic capacitance of the output transistor MPD and a parasitic capacitance of the output terminal OUT, or a capacitance externally provided as a stabilization capacitor separately from the load LD. May also be included.

  The resistance voltage dividing circuit 13 is connected between the output terminal OUT and the second power supply terminal VSS, and monitors the output voltage VOUT. The resistance voltage dividing circuit 13 includes, for example, a resistor R1 and a resistor R2 connected in series between the output terminal OUT and the second power supply terminal VSS, and the output voltage VOUT according to the resistance ratio of the resistors R1 and R2. Is divided. Hereinafter, a voltage obtained by dividing the output voltage VOUT by the resistance voltage dividing circuit 13 is referred to as a monitor voltage VM.

  The differential amplifier circuit 11 has a differential input terminal pair including a positive phase input terminal (+ terminal) and a negative phase input terminal (− terminal). The reference voltage VREF1 is supplied to the negative phase input terminal, and a positive phase input is provided. A monitor voltage VM by the resistance voltage dividing circuit 13 is supplied to the terminal. The internal configuration of the differential amplifier circuit 11 is not particularly limited. For example, the differential amplifier circuit 11 may be a one-stage amplifier circuit configured by a basic differential pair that amplifies the difference between signals input to the positive phase input terminal and the negative phase input terminal. A multi-stage amplifier circuit (for example, a two-stage amplifier circuit) that amplifies and outputs the signal amplified by the differential pair by another amplifier circuit may be used.

  The reference voltage VREF1 is a DC voltage. The magnitude of the reference voltage VREF1 is determined by the resistance value of the resistors R1 and R2, the target value of the output voltage VOUT of the series regulator circuit 100, the voltage range that can be input to the differential amplifier circuit 11, and the like.

  The output transistor MPD is, for example, a P-channel field effect transistor (for example, a MOS transistor), the source electrode as the first main electrode is connected to the first power supply terminal VCC, and the drain electrode as the second main electrode is the output terminal. Connected to OUT, a gate electrode as a control electrode is connected to an output terminal of the differential amplifier circuit 11. The gate voltage VOP1 of the output transistor MPD is controlled by the differential amplifier circuit 11 so that the monitor voltage VM becomes equal to the reference voltage VREF1. As a result, the output voltage VOUT is controlled to be constant regardless of the load current ILOAD.

  The differential amplifier circuit 12 has a differential input terminal pair including a positive phase input terminal (+ terminal) and a negative phase input terminal (− terminal). The reference voltage VREF2 is supplied to the negative phase input terminal, and a positive phase input is provided. The terminal is connected to the output terminal of the differential amplifier circuit 11 (the gate electrode of the output transistor MPD). The differential amplifier circuit 12 may be a single-stage amplifier circuit composed of a basic differential pair or a multi-stage amplifier circuit, for example, like the differential amplifier circuit 11. The internal configuration of is not particularly limited. The reference voltage VREF2 will be described in detail later.

  The current generation circuit 14 is connected between the output terminal OUT and the second power supply terminal VSS, and generates a current that flows from the output terminal OUT toward the second power supply terminal VSS according to the output signal of the second differential amplifier circuit. To do. Hereinafter, the current generated by the current generation circuit 14 is referred to as a bias current IBIAS.

  The current generation circuit 14 includes a resistor RB as a current generation element and a control transistor MNB. The control transistor MNB is, for example, an N channel type field effect transistor (for example, a MOS transistor). The control transistor MNB has a drain electrode connected to the output terminal OUT, a source electrode connected to one end of the resistor RB, and a gate electrode connected to the output terminal of the differential amplifier circuit 12. The other end of the resistor RB is connected to the second power supply terminal VSS.

  The control transistor MNB and the resistor RB need only be connected in series between the output terminal OUT and the second power supply terminal VSS, and the positional relationship between the control transistor MNB and the resistor RB is not particularly limited. For example, as shown in FIG. 2, the resistor RB may be connected to the output terminal OUT side, and the control transistor MNB may be connected to the second power supply voltage VSS side.

  By turning on / off the control transistor MNB, supply and stop of the bias current IBIAS to the output transistor MPD are controlled. Hereinafter, supply control of the bias current IBIAS to the output transistor MPD will be described in detail.

  For example, consider a situation where the load current ILOAD is small. In this situation, since the gate-source voltage of the output transistor MPD is relatively small, the gate voltage VOP1 of the output transistor MPD is high. At this time, if the gate voltage VOP1 is higher than the reference voltage VREF2, the differential amplifier circuit 12 increases the gate voltage VOP2 of the control transistor MNB to turn on the control transistor MNB. As a result, the bias current IBIAS flows in the output transistor MPD in addition to the load current ILOAD.

  Thereafter, when the load current ILOAD increases, the gate voltage VOP1 of the output transistor MPD decreases in order to increase the gate-source voltage of the output transistor MPD. When the gate voltage VOP1 of the output transistor MPD becomes lower than the reference voltage VREF2, the differential amplifier circuit 12 decreases the gate voltage VOP2 of the control transistor MNB and turns off the control transistor MNB. As a result, the supply of the bias current IBIAS to the output transistor MPD is stopped, and only the load current ILOAD (including the current flowing through the resistors R1 and R2) flows through the output transistor MPD.

  That is, as described above, by controlling on / off of the control transistor MNB in accordance with the magnitude of the gate voltage VOP1 of the output transistor MPD, a desired current flows through the output transistor MPD even when the load current ILOAD is small. It becomes possible.

  The magnitude of the reference voltage VREF2 may be determined based on the value of the load current ILOAD when starting to supply the bias current IBIAS to the output transistor MPD. For example, as in the above-described example, in order to ensure the stability of the series regulator circuit 100, when it is desired to pass a current of 2.3 mA or more to the output transistor MPD during the operation of the series regulator circuit 100, for example, the load current ILOAD The value of the reference voltage VREF2 is determined so that the control transistor MNB is turned on when the current becomes 2.3 mA or less. More specifically, the gate voltage VOP1 of the output transistor MPD when the load current ILOAD is 2.3 mA is calculated by simulation or the like, and the reference voltage VREF2 is determined based on the calculated gate voltage VOP1. According to this, when the load current ILOAD becomes 2.3 mA or less, the bias current IBIAS can be supplied to the output transistor MPD. The magnitude of the bias current IBIAS is mainly determined by the resistor RB and the output voltage VOUT (IBIAS≈VOUT / RB).

  The series regulator circuit 100 has a first pole P1 generated at the output terminal of the differential amplifier circuit 11 and a second pole P2 generated at the output terminal OUT, as in the conventional series regulator circuit 800 described above. The second pole P2 depends on the current flowing through the output transistor MPD. As described above, in the series regulator circuit 100, even if the load current ILOAD decreases, the current flows through the output transistor MPD. Therefore, the second pole P2 is higher on the frequency axis than the series regulator circuit 90. Placed in. As a result, the first pole P1 and the second pole P2 of the series regulator circuit 100 are arranged at locations separated from each other on the frequency axis, so that a phase margin is ensured compared to the conventional series regulator circuit 90. It becomes easy.

3 and 4 show simulation results of the series regulator circuit 100. FIG.
FIG. 3 shows a simulation result of the characteristics of the bias current IBIAS and the voltage of the main node with respect to the load current ILOAD of the series regulator circuit 100 of FIG. 1, and FIG. 4 shows the load current ILOAD of the series regulator circuit 100 of FIG. The simulation result of the characteristic of the phase margin with respect to is shown.

  As shown in FIG. 3, when the load current ILOAD is 4 mA or less, the gate voltage VOP1 of the output transistor MPD becomes larger than the reference voltage VREF2, and a bias current IBIAS of about 3.3 mA flows. As a result, the second pole P2 generated at the output terminal OUT moves to the high frequency side. Therefore, as shown in FIG. 4, even when the load current ILOAD is 4 mA or less, the phase is 45 degrees or more. A margin can be secured.

  On the other hand, in a section where the load current ILOAD is larger than 4 mA, as shown in FIG. 3, the gate voltage VOP1 of the output transistor MPD becomes smaller than the reference voltage VREF2, and the bias current IBIAS does not flow, but the load current ILOAD is 4 mA or more. Flowing. As a result, as shown in FIG. 4, a phase margin of 45 degrees or more can be secured even in a section where the load current ILOAD is 4 mA or more.

  As described above, according to the series regulator circuit of the present invention, when the load current ILOAD supplied to the load LD is smaller than the predetermined value, the bias current IBIAS is supplied to the output transistor MPD. Regardless of the current, a desired current can be passed through the output transistor MPD. As a result, even when the load current ILOAD is small, the two poles of the series regulator circuit can be arranged at a distance on the frequency axis, so that a phase margin of 45 degrees or more can be secured. Become. Therefore, according to the series regulator circuit of the present invention, stable operation is possible regardless of the load current.

  Further, according to the series regulator circuit of the present invention, when the load current ILOAD is larger than a predetermined value, the supply of the bias current IBIAS to the output transistor MPD is stopped, so that the power consumption in the situation where the load current ILOAD is large. Increase can be suppressed.

<< Embodiment 2 >>
FIG. 5 shows a configuration of a series regulator circuit 200 according to the second embodiment.
The series regulator circuit 200 shown in the figure is different from the series regulator circuit 100 according to the first embodiment in that the differential amplifier circuit for controlling on / off of the control transistor MNB has a hysteresis characteristic. The same as the series regulator circuit 100 in FIG. In the series regulator circuit 200, the same components as those in the series regulator circuit 100 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The series regulator circuit 200 includes a differential amplifier circuit 22 instead of the differential amplifier circuit 12. The differential amplifier circuit 22 has a hysteresis characteristic. For example, when a large load current ILOAD flows and the gate voltage VOP1 of the output transistor MPD is lower than the voltage VA, the differential amplifier circuit 22 decreases the gate voltage VOP2 of the control transistor MNB and turns off the control transistor MNB. Thereafter, when the load current ILOAD decreases and the gate voltage VOP1 rises and becomes higher than the voltage VA, the differential amplifier circuit 22 raises the gate voltage VOP2 of the control transistor MNB to turn on the control transistor MNB. Thereafter, when the load current ILOAD increases again and the gate voltage VOP1 decreases and becomes lower than the voltage VB (<VA), the differential amplifier circuit 22 increases the gate voltage VOP2 of the control transistor MNB to increase the control transistor MNB. Turn off.

  As a technique for providing the differential amplifier circuit 22 with hysteresis characteristics, for example, the two voltages VA and VB are generated as VREF2 outside the differential amplifier circuit 22, and the gate voltage VOP2 of the control transistor MNB is set. A method is conceivable in which two voltages VA and VB are switched and input to the differential amplifier circuit 22 in accordance with the switching of the polarity. As another method, one reference voltage VREF2 is input to the differential amplifier circuit 22, and the above two voltages VA and VB are obtained by dividing the reference voltage VREF2 by resistance in the differential amplifier circuit 22. The two voltages VA and VB may be switched and input to the differential pair in accordance with switching of the polarity of the gate voltage VOP2 of the control transistor MNB.

  According to this, even if the gate voltage VOP1 of the output transistor MPD fluctuates in the vicinity of the reference voltage VREF2 due to the fluctuation of the load current ILOAD, it is possible to prevent the control transistor MNB from being turned on / off unnecessarily. The stability of the supply control of the bias current IBIAS for the output transistor MPD can be improved.

  As described above, according to the series regulator circuit 200, as in the series regulator circuit 100 according to the first embodiment, stable operation is possible regardless of the load current. In addition, since the differential amplifier circuit 22 that controls on / off of the control transistor MNB has a hysteresis characteristic, the stability of supply control of the bias current IBIAS to the output transistor MPD can be improved.

  In the series regulator circuit 200, as long as the control transistor MNB and the resistor RB are connected in series as in the series regulator circuit 100 according to the first embodiment, their positional relationship is not particularly limited. For example, as shown in FIG. 6, the resistor RB may be connected to the output terminal OUT side, and the control transistor MNB may be connected to the second power supply voltage VSS side.

<< Embodiment 3 >>
FIG. 7 shows a configuration of series regulator circuit 300 according to the third embodiment.
The series regulator circuit 300 shown in the figure is different from the series regulator circuit 100 according to the first embodiment in that an output transistor composed of an N channel type field effect transistor is controlled instead of a P channel type field effect transistor. The other points are the same as those of the series regulator circuit 100. In the series regulator circuit 300, the same components as those in the series regulator circuit 100 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The series regulator circuit 300 includes an output transistor MND. The output transistor MND is an N-channel field effect transistor. In the differential amplifier circuit 11, the reference voltage VREF1 is supplied to the positive phase input terminal, and the monitor voltage VM from the resistance voltage dividing circuit 13 is supplied to the negative phase input terminal. In the differential amplifier circuit 12, the reference voltage VREF2 is supplied to the positive phase input terminal, and the negative phase input terminal is connected to the output terminal of the differential amplifier circuit 11 (the gate electrode of the output transistor MND).

  Since the output transistor MND is an N-channel field effect transistor, when the load current ILOAD increases, the gate voltage VOP1 of the output transistor MND increases. When the gate voltage VOP1 of the output transistor MND is smaller than the reference voltage VREF2, the differential amplifier circuit 12 turns on the control transistor MNB and supplies the bias current IBIAS to the output transistor MPD. On the other hand, when the gate voltage VOP1 of the output transistor MND is higher than the reference voltage VREF2, the differential amplifier circuit 12 turns off the control transistor MNB and stops supplying the bias current IBIAS to the output transistor MPD.

  In the series regulator circuit 300, as long as the control transistor MNB and the resistor RB are connected in series as in the series regulator circuit 100 according to the first embodiment, there is no particular limitation on the positional relationship between them. For example, as shown in FIG. 8, the resistor RB may be connected to the output terminal OUT side, and the control transistor MNB may be connected to the second power supply voltage VSS side.

9 and 10 show simulation results of the series regulator circuit 300. FIG.
9 shows a simulation result of the characteristics of the bias current IBIAS and the voltage of the main node with respect to the load current ILOAD of the series regulator circuit 300 of FIG. 7, and FIG. 10 shows the load current ILOAD of the series regulator circuit 300 of FIG. The simulation result of the characteristic of the phase margin with respect to is shown.

  As shown in FIG. 9, when the load current ILOAD is 1 mA or less, the gate voltage VOP1 of the output transistor MPD becomes smaller than the reference voltage VREF2, and the bias current IBIAS of about 230 μA flows. As a result, the second pole P2 generated at the output terminal OUT moves to the high frequency side, and as shown in FIG. 10, even when the load current ILOAD is 1 mA or less, the phase is 45 degrees or more. A margin can be secured.

  On the other hand, in a section where the load current ILOAD is larger than 1 mA, as shown in FIG. 9, the gate voltage VOP1 of the output transistor MND becomes larger than the reference voltage VREF2, and the bias current IBIAS does not flow, but the load current ILOAD is 1 mA or more. Flowing. As a result, as shown in FIG. 10, a phase margin of 45 degrees or more can be secured even in a section where the load current ILOAD is 1 mA or more.

  As described above, according to the series regulator circuit 300, as in the series regulator circuit 100 according to the first embodiment, a stable operation is possible regardless of the load current.

<< Embodiment 4 >>
FIG. 11 shows a configuration of a series regulator circuit 400 according to the fourth embodiment.
The series regulator circuit 400 shown in the figure is different from the series regulator circuit 300 according to the third embodiment in that the differential amplifier circuit that controls on / off of the control transistor MNB has a hysteresis characteristic. This is the same as the series regulator circuit 300. In the series regulator circuit 400, the same components as those in the series regulator circuit 300 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The series regulator circuit 400 includes a differential amplifier circuit 42 having hysteresis characteristics instead of the differential amplifier circuit 12. In the differential amplifier circuit 42, the reference voltage VREF2 is supplied to the positive phase input terminal, and the negative phase input terminal is connected to the output terminal of the differential amplifier circuit 11 (the gate electrode of the output transistor MND). The specific configuration of the differential amplifier circuit 42 is the same as that of the differential amplifier circuit 22 of the second embodiment.

  As described above, according to the series regulator circuit 400, as in the series regulator circuit 300 according to the third embodiment, stable operation is possible regardless of the load current. Further, according to the series regulator circuit 300, since the differential amplifier circuit 42 that controls the on / off of the control transistor MNB has a hysteresis characteristic, stability of supply control of the bias current IBIAS to the output transistor MND is improved. be able to.

  In the series regulator circuit 400, as long as the control transistor MNB and the resistor RB are connected to each other in series as in the series regulator circuit 100 according to the first embodiment, their positional relationship is not particularly limited. For example, as shown in FIG. 12, the resistor RB may be connected to the output terminal OUT side, and the control transistor MNB may be connected to the second power supply voltage VSS side.

<< Embodiment 5 >>
FIG. 13 shows a configuration of a series regulator circuit 500 according to the fifth embodiment.
The series regulator circuit 500 shown in the figure is different from the series regulator circuit 300 according to the third embodiment in that it controls a control transistor composed of a P-channel field effect transistor instead of an N-channel field effect transistor. The other points are the same as those of the series regulator circuit 300. In the series regulator circuit 500, the same components as those in the series regulator circuit 300 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The series regulator circuit 500 includes a control transistor MPB. The control transistor MPB is a P-channel type field effect transistor. In the differential amplifier circuit 12, the reference voltage VREF2 is supplied to the negative phase input terminal, and the positive phase input terminal is connected to the output terminal of the differential amplifier circuit 11 (the gate electrode of the output transistor MND).

  When the gate voltage VOP1 of the output transistor MND is smaller than the reference voltage VREF2, the differential amplifier circuit 12 turns on the control transistor MPB by reducing the gate voltage VOP2 of the control transistor MPB, and causes the output transistor MND to have a bias current IBIAS. Supply. On the other hand, when the gate voltage VOP1 of the output transistor MND is larger than the reference voltage VREF2, the differential amplifier circuit 12 turns off the control transistor MPB by increasing the gate voltage VOP2 of the control transistor MPB, thereby biasing the output transistor MND. The supply of current IBIAS is stopped.

  In series regulator circuit 500, as long as control transistor MPB and resistor RB are connected in series as in series regulator circuit 300 according to the third embodiment, there is no particular limitation on their positional relationship. For example, as shown in FIG. 14, the resistor RB may be connected to the output terminal OUT side, and the control transistor MPB may be connected to the second power supply voltage VSS side.

  15 and 16 show simulation results of the series regulator circuit 500. FIG. FIG. 15 shows a simulation result of the characteristics of the bias current IBIAS and the voltage of the main node with respect to the load current ILOAD of the series regulator circuit 500 of FIG. 13, and FIG. 16 shows the load current ILOAD of the series regulator circuit 500 of FIG. The simulation result of the characteristic of the phase margin with respect to is shown.

  As shown in FIGS. 15 and 16, like the series regulator circuit 300 according to the above-described third embodiment, even when the load current ILOAD is small, the bias current IBIAS flows, so that a phase margin of 45 degrees or more is obtained. Can be secured.

  As described above, according to the series regulator circuit 500, as in the series regulator circuit 300 according to the third embodiment, stable operation is possible regardless of the load current.

<< Embodiment 6 >>
FIG. 17 shows a configuration of series regulator circuit 600 according to the sixth embodiment.
The series regulator circuit 600 shown in the figure is different from the series regulator circuit 500 according to the fifth embodiment in that the differential amplifier circuit for controlling on / off of the control transistor MPB has hysteresis characteristics. This is the same as the series regulator circuit 500. In the series regulator circuit 600, the same components as those in the series regulator circuit 500 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The series regulator circuit 600 includes a differential amplifier circuit 62 having hysteresis characteristics instead of the differential amplifier circuit 12. In the differential amplifier circuit 62, the reference voltage VREF2 is supplied to the negative phase input terminal, and the positive phase input terminal is connected to the output terminal of the differential amplifier circuit 11 (the gate electrode of the output transistor MND). The specific configuration of the differential amplifier circuit 62 is the same as that of the differential amplifier circuit 22 of the second embodiment.

  As described above, according to the series regulator circuit 600, as in the case of the series regulator circuit 500 according to the fifth embodiment, stable operation is possible regardless of the load current. Further, since the differential amplifier circuit 62 that controls on / off of the control transistor MPB has a hysteresis characteristic, it is possible to improve the stability of supply control of the bias current IBIAS to the output transistor MND.

  In series regulator circuit 600, as long as control transistor MPB and resistor RB are connected in series as in series regulator circuit 100 according to the first embodiment, there is no particular limitation on their positional relationship. For example, as shown in FIG. 18, the resistor RB may be connected to the output terminal OUT side, and the control transistor MPB may be connected to the second power supply voltage VSS side.

<< Embodiment 7 >>
FIG. 19 shows a configuration of a series regulator circuit 700 according to the seventh embodiment.
The series regulator circuit 700 shown in the figure is different from the series regulator circuit 100 according to the first embodiment in that it controls a control transistor composed of a P-channel field effect transistor instead of an N-channel field effect transistor. The other points are the same as those of the series regulator circuit 100. In the series regulator circuit 700, the same components as those in the series regulator circuit 100 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The series regulator circuit 700 includes a control transistor MPB. The control transistor MPB is a P-channel type field effect transistor. In the differential amplifier circuit 12, the reference voltage VREF2 is supplied to the positive phase input terminal, and the negative phase input terminal is connected to the output terminal of the differential amplifier circuit 11 (the gate electrode of the output transistor MPD).

  When the gate voltage VOP1 of the output transistor MPD is larger than the reference voltage VREF2, the differential amplifier circuit 12 turns on the control transistor MPB by lowering the gate voltage VOP2 of the control transistor MPB, and causes the output transistor MPD to have a bias current IBIAS. Supply. On the other hand, when the gate voltage VOP1 of the output transistor MPD is smaller than the reference voltage VREF2, the differential amplifier circuit 12 turns off the control transistor MPB by increasing the gate voltage VOP2 of the control transistor MPB, thereby biasing the output transistor MPD. The supply of current IBIAS is stopped.

  In series regulator circuit 700, as long as control transistor MPB and resistor RB are connected in series as in series regulator circuit 100 according to the first embodiment, there is no particular limitation on their positional relationship. For example, as shown in FIG. 20, the resistor RB may be connected to the output terminal OUT side, and the control transistor MPB may be connected to the second power supply voltage VSS side.

  21 and 22 show simulation results of the series regulator circuit 700. FIG. FIG. 21 shows a simulation result of the characteristics of the bias current IBIAS and the voltage of the main node with respect to the load current ILOAD of the series regulator circuit 700 of FIG. 19, and FIG. 22 shows the load current ILOAD of the series regulator circuit 700 of FIG. The simulation result of the characteristic of the phase margin with respect to is shown.

  As shown in FIG. 21 and FIG. 22, like the series regulator circuit 100 according to the first embodiment described above, even when the load current ILOAD is small, the bias current IBIAS flows, so that a phase margin of 45 degrees or more is obtained. Can be secured.

  As described above, according to the series regulator circuit 700, as in the series regulator circuit 100 according to the first embodiment, stable operation is possible regardless of the load current.

<< Embodiment 8 >>
FIG. 23 shows a configuration of a series regulator circuit 800 according to the eighth embodiment.
The series regulator circuit 800 shown in the figure is different from the series regulator circuit 700 according to the seventh embodiment in that the differential amplifier circuit that controls on / off of the control transistor MPB has a hysteresis characteristic. This is the same as the series regulator circuit 700. In the series regulator circuit 800, the same components as those in the series regulator circuit 700 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The series regulator circuit 800 includes a differential amplifier circuit 82 having hysteresis characteristics instead of the differential amplifier circuit 12. In the differential amplifier circuit 82, the reference voltage VREF2 is supplied to the positive phase input terminal, and the negative phase input terminal is connected to the output terminal of the differential amplifier circuit 11 (the gate electrode of the output transistor MPD). The specific configuration of the differential amplifier circuit 82 is the same as that of the differential amplifier circuit 22 of the second embodiment.

  As described above, according to the series regulator circuit 800, as in the series regulator circuit 700 according to the seventh embodiment, stable operation is possible regardless of the load current. In addition, since the differential amplifier circuit 82 that controls on / off of the control transistor MPB has a hysteresis characteristic, the stability of supply control of the bias current IBIAS to the output transistor MPD can be improved.

  In the series regulator circuit 800, the control transistor MPB and the resistor RB are not particularly limited as long as they are connected in series as in the series regulator circuit 100 according to the first embodiment. For example, as shown in FIG. 24, the resistor RB may be connected to the output terminal OUT side, and the control transistor MPB may be connected to the second power supply voltage VSS side.

  Although the invention made by the present inventors has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. Yes.

  For example, in the series regulator circuits 100 to 800 according to the first to eighth embodiments, the output transistors MPD and MND and the control transistors MPB and MNB are P-channel or N-channel field effect transistors (MOS transistors). However, the present invention is not limited to this. For example, the output transistors MPD and MND and the control transistors MPB and MNB may be NPN transistors and PNP transistors including an HBT (Heter Junction Bipolar Transistor), or may be an N-channel or P-channel junction FET or a compound semiconductor. It may be an N-channel type or P-channel type FET including a HEMT (High Electron Mobility Transistor).

  In the series regulator circuits 100 to 800 according to the first to eighth embodiments, the configuration using the resistor RB as the current generating element is illustrated, but the present invention is not limited to this, and as illustrated in FIG. It is also possible to use the source 15.

  DESCRIPTION OF SYMBOLS 100-800 ... Series regulator circuit, 11, 12 ... Differential amplifier circuit, 22, 42, 62, 82 ... Differential amplifier circuit which has a hysteresis characteristic, 13 ... Resistance voltage dividing circuit, 14 ... Current generation circuit, 15 ... Constant Current source, MPD, MND ... output transistor, MNB, MPB ... control transistor, R1, R2, RB ... resistor, VREF1, VREF2 ... reference voltage, COUT ... output capacitance, LD ... load, VOUT ... output voltage, ILOAD ... load current , IBIAS: bias current, OUT: output terminal, VCC: first power supply terminal, VSS: second power supply terminal.

Claims (8)

A first power supply terminal to which a first DC voltage is supplied;
A second power supply terminal to which a second DC voltage lower than the first DC voltage is supplied;
An output terminal;
A resistive voltage divider connected between the output terminal and the second power supply terminal;
A differential input terminal pair including a positive phase input terminal and a negative phase input terminal is provided, a first reference voltage is supplied to one of the differential input terminals, and the other differential input terminal is divided by the resistor voltage dividing circuit. A first differential amplifier circuit to which the adjusted voltage is supplied;
An output transistor having a first main electrode connected to the first power supply terminal, a second main electrode connected to the output terminal, and a control electrode connected to an output terminal of the first differential amplifier circuit;
A differential input terminal pair including a positive phase input terminal and a negative phase input terminal, wherein one differential input terminal is connected to an output terminal of the first differential amplifier circuit, and the other differential input terminal is A second differential amplifier circuit to which a second reference voltage different from the one reference voltage is supplied;
A current generation circuit which is connected between the output terminal and the second power supply terminal and generates a current flowing from the output terminal to the second power supply terminal in accordance with an output signal of the second differential amplifier circuit; And
The current generation circuit includes:
A control transistor having a control electrode connected to an output terminal of the second differential amplifier circuit;
A series regulator circuit comprising: a current generation element connected in series with the control transistor. The series regulator circuit according to claim 1,
The series regulator circuit, wherein the second differential amplifier circuit has a hysteresis characteristic. The series regulator circuit according to claim 1 or 2,
The output transistor is a P-channel field effect transistor,
The control transistor is an N-channel field effect transistor,
The voltage divided by the resistor voltage divider circuit is supplied to the positive phase input terminal of the first differential amplifier circuit, and the first reference voltage is supplied to the negative phase input terminal of the first differential amplifier circuit,
The positive phase input terminal of the second differential amplifier circuit is connected to the output terminal of the first differential amplifier circuit, and the second reference voltage is supplied to the negative phase input terminal of the second differential amplifier circuit. Series regulator circuit characterized by The series regulator circuit according to claim 1 or 2,
The output transistor is an N-channel field effect transistor,
The control transistor is an N-channel field effect transistor,
A voltage divided by the resistance voltage divider circuit is supplied to a negative phase input terminal of the first differential amplifier circuit, and a first reference voltage is supplied to a positive phase input terminal of the first differential amplifier circuit;
The negative phase input terminal of the second differential amplifier circuit is connected to the output terminal of the first differential amplifier circuit, and the second reference voltage is supplied to the positive phase input terminal of the second differential amplifier circuit. Series regulator circuit characterized by The series regulator circuit according to claim 1 or 2,
The output transistor is an N-channel field effect transistor,
The control transistor is a P-channel field effect transistor,
A voltage divided by the resistance voltage divider circuit is supplied to a negative phase input terminal of the first differential amplifier circuit, and a first reference voltage is supplied to a positive phase input terminal of the first differential amplifier circuit;
The positive phase input terminal of the second differential amplifier circuit is connected to the output terminal of the first differential amplifier circuit, and the second reference voltage is supplied to the negative phase input terminal of the second differential amplifier circuit. Series regulator circuit characterized by The series regulator circuit according to claim 1 or 2,
The output transistor is a P-channel field effect transistor,
The control transistor is a P-channel field effect transistor,
The voltage divided by the resistor voltage divider circuit is supplied to the positive phase input terminal of the first differential amplifier circuit, and the first reference voltage is supplied to the negative phase input terminal of the first differential amplifier circuit,
The negative phase input terminal of the second differential amplifier circuit is connected to the output terminal of the first differential amplifier circuit, and the second reference voltage is supplied to the positive phase input terminal of the second differential amplifier circuit. Series regulator circuit characterized by The series regulator circuit according to any one of claims 1 to 6,
The series regulator circuit, wherein the current generation element is a resistance element. The series regulator circuit according to any one of claims 1 to 6,
The series regulator circuit, wherein the current generating element is a constant current source.

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