JP2010217965A - Constant voltage circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a constant voltage circuit that reduces adverse effects on a peripheral circuit and a device body at start-up by setting the peak of rush currents to be lower than limit currents set for a normal operation. <P>SOLUTION: Currents flowing through a power transistor Mpt are detected by a current mirror circuit 13 and a current detection circuit 14. When the currents are equal to or larger than a preset value, a current detection signal Scd corresponding to the currents is supplied to a correction circuit 16. A correction circuit 16 decreases a driving signal Sdrv to be supplied to the power transistor Mpt according to the size of the current detection signal Scd by a correction circuit 16. At start-up, a level switching circuit 15 causes the current detection circuit 14 to increase the level of the current detection signal Scd so that the amount of decreased driving signal Sdrv in the correction circuit 16 can be made larger than that in a normal operation. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a constant voltage circuit for supplying a stable voltage to a load device, and is intended to appropriately carry out suppression of inrush current at start-up and prevention of overcurrent during normal operation with a single overcurrent protection circuit. It is about technology.

  The series regulator type constant voltage circuit has a feedback control loop for obtaining a stable voltage therein, and is widely used as a power source for supplying a stable voltage to a load device with low power consumption. In a circuit device that generates a stable output voltage not only in a constant voltage circuit but in a feedback control loop, when the output voltage decreases due to an output short circuit or the like, an action to increase the output voltage occurs in the feedback control loop. There is a risk of current flowing. Therefore, normally, an overcurrent holding circuit is formed in the constant voltage circuit together with a feedback control loop to protect the circuit device from an excessive current.

FIG. 6 is a circuit diagram of a conventional constant voltage circuit having an overcurrent protection circuit therein.
The constant voltage circuit of FIG. 6 is connected between a power transistor Mpt for current control connected between a circuit input terminal IN and a circuit output terminal OUT, and between the circuit output terminal OUT and a reference potential point (ground) of the circuit. The voltage detection resistors R1 and R2, their output terminals are connected to the power transistor Mpt, their inverting input terminals are connected to the common connection point of the resistors R1 and R2, and their high potential side is an error amplifier. The reference voltage source Vr1 is connected to the non-inverting input terminal of EA1 and the low potential side is connected to the ground, and the overcurrent protection circuit OCP is connected to the output terminal of the error amplifier EA1. Note that the capacitor C1 connected between the circuit output terminal OUT and the ground is a smoothing capacitor externally attached to the constant voltage circuit.

  In the circuit having the configuration shown in FIG. 6, a feedback control loop is formed on the path from the source of the power transistor Mpt to the connection point of the resistors R1 and R2, the inverting input terminal and the output terminal of the error amplifier EA1, and returning to the gate of the power transistor Mpt. Is formed. Since the operation and action for stabilizing the output voltage by the feedback control loop are described in various documents, description thereof is omitted here.

  On the other hand, the overcurrent protection circuit OCP in FIG. 6 detects the drive signal Sdrv supplied from the error amplifier EA1 to the gate of the power transistor Mpt, and when the drive signal Sdrv tries to increase beyond a predetermined value. The drive signal Sdrv is prevented from increasing. A specific configuration example of such an overcurrent protection circuit OCP is shown, for example, in FIG. Some overcurrent protection circuit OCP detects the current flowing through the power transistor Mpt to prevent the drive signal Sdrv from rising. An example of the configuration of such an overcurrent protection circuit is shown in FIG. Is shown in

  Supplementing the explanation of the operation and operation of the overcurrent protection circuit OCP, the overcurrent protection circuit OCP has a power supply so that the output voltage and output current of the constant voltage circuit have a relationship of “droop characteristics” and “f-shaped characteristics”. The magnitude of the drive signal Sdrv supplied to the transistor Mpt is limited. Specifically, when the magnitude of the drive signal Sdrv exceeds a predetermined value, the output of the error amplifier EA1 is reduced according to the magnitude of the drive signal, thereby limiting the current passing through the paratransistor Mpt. Then, a relationship of “droop characteristics” and “f-shaped characteristics” appears in the output voltage and output current. Alternatively, when the passing current of the power transistor Mpt becomes larger than a predetermined value, the output of the error amplifier EA1 is reduced according to the current value, and a relationship of “dripping characteristics” appears between the output voltage and the output current. As a result, the overcurrent protection circuit OCP prevents an excessive current from flowing due to the voltage stabilization action of the feedback control loop.

Japanese Patent Laid-Open No. 03-186909 JP 2006-155099 A

  When actually creating a constant voltage circuit having an overcurrent protection circuit, the value of the output current (hereinafter referred to as the limit current value) at which the overcurrent protection circuit determines that it is in an overcurrent state and starts operating is of course the operation. It must be set higher than the maximum current normally required by the load device. Some load devices require a large amount of current during operation, and in a constant voltage circuit that supplies an output voltage to such a load device, the current limit value of the overcurrent protection circuit must be set high. Absent.

  By the way, the overcurrent protection circuit provided in the constant voltage circuit can be used not only for preventing overcurrent during normal operation, but also for suppressing inrush current during startup. A technique of using the overcurrent protection circuit for suppressing inrush current is disclosed in, for example, cited document 2 and the like. A constant voltage circuit that also uses an overcurrent protection circuit to suppress inrush current. When the limit current is set high as in the previous example, a large inrush that rises from zero to the limit current value in a very short time at startup. Current flows. When such an inrush current flows, there is a possibility that the peripheral circuits and devices of the constant voltage circuit may be adversely affected, such as premature deterioration of the battery or abnormal operation of the preceding circuit.

  Therefore, the present invention provides a constant voltage circuit that uses an overcurrent protection circuit to prevent overcurrent during normal operation and suppress inrush current during start-up, so that the peak of the inrush current is higher than the limit current set for normal operation. It is an object of the present invention to provide a constant voltage circuit that is low and has a low risk of adversely affecting peripheral circuits and devices during startup.

The present invention for solving the above problems is as follows.
In a constant voltage circuit that generates a drive signal according to the output voltage and reference voltage of the circuit in the error amplifier and feedback-controls the operation of the power transistor connected between the input and output terminals of the circuit by the drive signal, passes through the power transistor A current mirror circuit that flows a current proportional to the current, a current detection circuit that detects a current flowing through the current mirror circuit and outputs a current detection signal corresponding to the current, and is connected to the current detection circuit. A level switching circuit to be changed, and a correction circuit for reducing the drive signal supplied to the power transistor according to the magnitude of the detection signal, wherein the level switching circuit is configured such that the level of the current detection signal when the constant voltage circuit is activated. Is set to be relatively large and the level of the current detection signal is relatively small during normal operation. It is characterized by that.

  Since the level of the current detection signal is high until a certain time elapses after starting, the drive signal supplied to the power transistor is greatly reduced compared to the overcurrent state during normal operation. As a result, the peak of the inrush current can be suppressed to a value lower than the limit current, and a constant voltage circuit can be provided that is less likely to adversely affect peripheral circuits and devices during startup.

The block diagram of the constant voltage circuit by this invention. 1 is a circuit diagram of a first embodiment of a constant voltage circuit according to the present invention. The circuit diagram of the 2nd Example of the constant voltage circuit by this invention. The circuit diagram of the 3rd Example of the constant voltage circuit by this invention. The circuit diagram of the 4th Example of the constant voltage circuit by this invention. The circuit diagram of the conventional constant voltage circuit.

An embodiment of a constant voltage circuit according to the present invention will be described with reference to the block diagram of FIG.
1, the connection configuration of the power transistor Mpt, the voltage detection resistors R1 and R2, the error amplifier EA1, and the reference voltage source Vr1 is the same as that of the conventional example of FIG. In a preferred embodiment of the present invention, an overcurrent protection circuit OCP0 that plays a central role in the present invention, an enable reception circuit 11 and a delay circuit 12 are included in the series regulator constituted by the power transistor Mpt to the reference voltage source Vr1. Is installed.

  Here, the overcurrent protection circuit OCP0 detects a current mirror circuit 13 that flows a current proportional to the current flowing through the power transistor Mpt, a current that flows through the current mirror circuit 13, and a current detection signal Scd corresponding to the magnitude of the current. Is supplied from the error amplifier EA1 to the power transistor Mpt in response to the current detection signal Scd, the level switching circuit 15 that is connected to the current detection circuit 14 and changes the signal level of the current detection signal Scd. The correction circuit 16 reduces the drive signal Sdrv.

  An enable reception circuit 11 and a delay circuit 12 are provided in order to cause the overcurrent protection circuit OCP0 to perform a desired operation when the constant voltage circuit is activated and during a steady operation. Here, the enable reception circuit 11 is supplied with an enable signal from the outside via the terminal En when the constant voltage circuit is activated. On the other hand, the delay circuit 12 is in the first state when the enable receiving circuit 11 receives the enable signal, and receives the level command signal Slev that enters the second state after a predetermined time has elapsed after receiving the enable signal. This is supplied to the switching circuit 15.

  In the constant voltage circuit having the above configuration, when a large amount of current flows through the power transistor Mpt, a current proportional to the current flows through the current mirror circuit 13. The current detection circuit 14 detects a current flowing through the current mirror circuit 13 and supplies a current detection signal Scd corresponding to the magnitude of the current to the correction circuit 16 when the current exceeds a preset value. Then, the correction circuit 16 decreases the drive signal Sdrv supplied from the error amplifier EA1 to the power transistor Mpt according to the magnitude of the current detection signal Scd. Accordingly, the overcurrent protection circuit OCP0 provided in the constant voltage circuit of FIG. 1 reduces the amount of current passing through the power transistor Mpt, limits the peak of the inrush current, or prevents the overcurrent from flowing.

Here, as a feature of the present invention, the following operation is performed inside the delay circuit 12 and the overcurrent protection circuit OCP0.
When the enable signal is supplied, the delay circuit 12 sets the level command signal Slev supplied to the level switching circuit 15 to the first state. When the level command signal Slev is in the first state, the level switching circuit 15 increases the level of the current detection signal Scd supplied from the current detection circuit 14 to the correction circuit 16. Then, the amount of decrease in the drive signal Sdrv in the correction circuit 16 increases according to the level of the current detection signal Scd, and the amount of current passing through the power transistor Mpt is further reduced.

  When a predetermined time elapses after the enable signal is supplied, the delay circuit 12 sets the level command signal Slev to the second state. When the level command signal Slev is in the second state, the level switching circuit 15 decreases the level of the current detection signal Scd supplied from the current detection circuit 14 to the correction circuit 16. Then, the decrease amount of the drive signal Sdrv in the correction circuit 16 becomes small according to the level of the current detection signal Scd, and the current passing through the power transistor Mpt is limited to a corresponding magnitude.

  In the operation described above, the constant voltage circuit is activated until a predetermined time elapses after the enable signal is supplied, and the constant voltage is applied after the predetermined time elapses after the enable signal is supplied. This is the period during which the circuit is operating normally. That is, in the overcurrent protection circuit OCP0, the level switching circuit 15 is operated so that the level of the current detection signal Scd becomes relatively large when the constant voltage circuit is activated, and conversely, the level of the current detection signal Scd during normal operation. Is operated to be relatively small. Thereby, the peak of the inrush current at the time of start-up is suppressed to be lower than the limit current value at the time of normal operation by the operation action of the level switching circuit 15.

FIG. 2 is a circuit diagram of a first embodiment of a constant voltage circuit according to the present invention. In the constant voltage circuit of FIG. 2, the overcurrent protection circuit OCP1 forming the central part of the present invention is configured as follows.
(Except for the portion of the overcurrent protection circuit OCP1, the circuits in FIG. 1 and FIG. 2 basically have the same configuration, so detailed description thereof will be omitted. The same applies to other circuit diagrams.)

  First, the power transistor Mpt and the transistor Mmi constituting the current mirror circuit are provided, and the gates and the sources of the transistors Mpt and Mmi are connected in common. The drain of the transistor Mmi is connected to the input terminal IN via a variable resistance circuit RL that changes an electric resistance value according to the state of a signal (level command signal) supplied from the outside (delay circuit 12 in the figure).

  Subsequently, an error amplifier EA2 is provided, and its non-inverting input terminal is connected to one end of the variable resistance circuit RL, that is, the transistor Mmi side terminal. The inverting input terminal of the error amplifier EA2 is connected to one end of the variable resistance RL circuit, that is, the input terminal IN side terminal, via the reference voltage source Vr2. The polarity direction of the reference voltage source Vr2 is set such that the signal supplied to the inverting input terminal of the error amplifier EA2 is reduced by the voltage generated there. The correction circuit 16 is provided, and its two input terminals are connected to the output terminal of the error amplifier EA1 and the output terminal of the error amplifier EA2, respectively, and the output terminal is connected to the common connection point of the gates of the power transistor Mpt and the transistor Mmi. .

  Inside the overcurrent protection circuit OCP1 having the above configuration, a current proportional to the current of the power transistor Mpt flows through the transistor Mmi, and a voltage drop occurs between the terminals of the variable resistance circuit RL according to the current flowing through the transistor Mmi. For example, when the current flowing through the transistor Mmi increases and the voltage drop generated in the variable resistance circuit RL exceeds the reference voltage value generated in the reference voltage source Vr2, the output of the error amplifier EA2 changes from positive to negative. Then, the correction circuit 16 reduces the output of the error amplifier EA1 (corresponding to the drive signal Sdrv of FIG. 1) in accordance with the magnitude of the output of the error amplifier EA2 (corresponding to the current detection signal of FIG. 1).

  Here, the variable resistance circuit RL changes the electric resistance value in accordance with the level command signal Slev supplied from the delay circuit 12. Specifically, when the enable receiving circuit 11 receives the enable signal, the delay circuit 12 sets the level command signal Slev to the first state. The variable resistance circuit RL relatively increases the electric resistance value in response to the level command signal Slev which is the first state. Then, the voltage drop generated in the variable resistance circuit RL becomes large, and the current detection level becomes equivalently high. Then, the drop amount of the voltage supplied to the non-inverting input terminal of the error amplifier EA2 is increased, and the output of the error amplifier EA1 is further reduced by the negative output of the error amplifier EA2 that is increased accordingly.

Note that the delay circuit 12 sets the level command signal Slev to the second state after a predetermined time has elapsed since the enable receiving circuit 11 received the enable signal. The variable resistance circuit RL relatively decreases the electric resistance value in response to the level command signal Slev which is the second state. Then, the voltage drop generated in the variable resistance circuit RL is reduced, and the current detection level is equivalently reduced. As a result, the amount of voltage drop supplied to the non-inverting input terminal of the error amplifier EA2 becomes small, and the amount of decrease in the output of the error amplifier EA1 becomes appropriate.
By performing such an operation inside the overcurrent protection circuit OCP1, it becomes possible to make the peak of the inrush current that occurs when the constant voltage circuit starts up lower than the limit current value during normal operation.

FIG. 3 is a circuit diagram of a second embodiment of the constant voltage circuit according to the present invention. In the constant voltage circuit of FIG. 3, the overcurrent protection circuit OCP2 forming the central part of the present invention is configured as follows.
First, the power transistor Mpt and the transistor Mmi constituting the current mirror circuit are provided, and the gates and the sources of the transistors Mpt and Mmi are connected in common. The drain of the transistor Mmi is connected to the input terminal IN via a variable resistance circuit RL that changes the electric resistance value in accordance with the state of a level command signal supplied from the outside.

  The connection point of the variable resistance circuit RL and the transistor Mmi is connected to the source of the transistor M1 whose drain and gate are short-circuited, and the drain of the transistor M1 is connected to the ground (= the reference potential point of the circuit) via the current source CS1. . The gate of the transistor M2 is connected to the gate of the transistor M1, and the source of the transistor M2 is connected to the input terminal IN through the resistor R3. The drain of the transistor M2 is connected to the ground via the current source CS2.

  The gate of the transistor M3 is connected to the drain of the transistor M2, and the source of the transistor M3 is connected to the ground. A resistor R4 is connected between the output terminal of the error amplifier EA1 and the gate of the power transistor Mpt, and the drain of the transistor M3 is connected to the gate of the power transistor Mpt. Note that the transistors M1 and M2 are p-channel transistors and the transistor M3 is an n-channel transistor.

  Inside the overcurrent protection circuit OCP1 having the above configuration, a constant current can flow through the variable resistance circuit RL by the current source CS1. Here, when a current proportional to the current of the power transistor Mpt flows through the transistor Mmi, the current flowing through the variable resistance circuit RL increases, and the current between the terminals of the variable resistance circuit RL corresponds to the current flowing through the current source CS1 and the transistor Mmi. A voltage drop occurs. Then, a voltage lower than the voltage of the input terminal IN by the voltage drop generated in the variable resistance circuit RL and the transistor M1 is supplied to the gate of the transistor M2.

  For example, as the current of the transistor Mmi is gradually increased, the voltage drop in the variable resistance circuit RL is also increased. As a result, the voltage supplied to the gate of the transistor M2 decreases, and the electrical resistance between the source and drain of the transistor M2 decreases. Then, the voltage supplied to the gate of the transistor M3 increases, and when the voltage exceeds the threshold value of the transistor M3, a current flows from the output terminal of the error amplifier EA1 toward the main current path of the transistor M3. . Since the current flowing in the main current path of the transistor M3 has a magnitude corresponding to the current of the transistor Mmi and eventually the voltage drop of the variable resistance circuit RL, the output of the error amplifier EA1 supplied to the power transistor Mpt is practically The voltage decreases according to the amount of voltage drop of the variable resistance circuit RL.

  Here, the variable resistance circuit RL changes the electric resistance value in accordance with the level command signal Slev supplied from the delay circuit 12 in the same manner as in FIGS. Specifically, when the enable receiving circuit 11 receives the enable signal, the delay circuit 12 sets the level command signal Slev to the first state. The variable resistance circuit RL relatively increases the electric resistance value in response to the level command signal Slev which is the first state. Then, the amount of voltage drop generated in the variable resistance circuit RL increases, and the current flowing through the transistor M3 increases. As a result, the output of the error amplifier EA1 supplied to the power transistor Mpt is further reduced, and the current flowing through the power transistor Mpt is limited to a small value.

Note that the delay circuit 12 sets the level command signal Slev to the second state after a predetermined time has elapsed since the enable receiving circuit 11 received the enable signal. The variable resistance circuit RL relatively decreases the electric resistance value in response to the level command signal Slev which is the second state. Then, the voltage drop generated in the variable resistance circuit RL is reduced, and the current flowing through the transistor M3 is reduced. As a result, the output of the error amplifier EA1 supplied to the power transistor Mpt decreases correspondingly, and the current flowing through the power transistor Mpt is limited to a corresponding value.
By performing such an operation inside the overcurrent protection circuit OCP2, it becomes possible to make the peak of the inrush current that occurs when the constant voltage circuit starts up lower than the limit current value during normal operation.

FIG. 4 is a circuit diagram of a third embodiment of a constant voltage circuit according to the present invention. In the constant voltage circuit of FIG. 4, the overcurrent protection circuit OCP3 is configured as follows.
A power transistor Mpt and a transistor Mmi constituting a current mirror circuit are provided, and the gates and sources of the transistors Mpt and Mmi are connected in common. The drain of the transistor Mmi is connected to the ground through a variable resistance circuit RL that changes the electric resistance value in accordance with the state of a level command signal supplied from the outside.

  An error amplifier EA2 is provided, and its non-inverting input terminal is connected to one end (transistor Mmi side terminal) of the variable resistance circuit RL. The inverting input terminal of the error amplifier EA2 is connected to a reference voltage source Vr1 common to the error amplifier EA1. The correction circuit 16 is provided, and its two input terminals are connected to the output terminal of the error amplifier EA1 and the output terminal of the error amplifier EA2, respectively, and the output terminal is connected to the common connection point of the gates of the power transistor Mpt and the transistor Mmi. . In the embodiment circuit of FIG. 4, the power transistor Mpt and the transistor Mmi are P-channel type.

  The overcurrent protection circuit OCP3 having the above configuration is equivalent to the overcurrent protection circuit OCP1 in FIG. That is, since the power transistor Mpt and the transistor Mmi are P-channel type, the polarity of each part of the overcurrent protection circuit OCP3 is inverted so as to be able to cope with it. The operation performed in the overcurrent protection circuit OCP3 is basically the same as that of the overcurrent protection circuit OCP1 in FIG.

FIG. 5 is a circuit diagram of a fourth embodiment of a constant voltage circuit according to the present invention. In the constant voltage circuit of FIG. 5, the overcurrent protection circuit OCP4 is configured as follows.
A power transistor Mpt and a transistor Mmi constituting a current mirror circuit are provided, and the gates and sources of the transistors Mpt and Mmi are connected in common. Further, another power transistor Mpt and a transistor M4 constituting a current mirror circuit are provided, and the gates and sources of the transistors Mpt and M4 are connected in common.

  The drain of the transistor Mmi is connected to the ground via a resistor R5. On the other hand, the drain of the transistor M4 is connected to a common connection point of the transistor Mmi and the resistor R5 via a switch SW that is turned on / off according to the state of a signal (level command signal) supplied from the outside (delay circuit 12 in the figure). . An error amplifier EA2 is provided, its non-inverting input terminal is connected to one end of the resistor R5 (transistor Mmi side terminal), and its inverting input terminal is connected to the reference voltage source Vr1. A correction circuit 16 is provided, and its two input terminals are connected to the output terminal of the error amplifier EA1 and the output terminal of the error amplifier EA2, respectively, and the output terminal is connected to the gate of the power transistor Mpt. Note that the power transistor Mpt and the transistors Mmi and M4 are P-channel type.

  The overcurrent protection circuit OCP4 having the above configuration changes the current amount of the current mirror circuit (Mmi, M4) instead of changing the electric resistance value of the variable resistance circuit RL like the overcurrent protection circuit OCP3 of FIG. It is comprised so that it may make it. For example, when the enable receiving circuit 11 receives the enable signal, the delay circuit 11 sets the level command signal Slev to the first state. The switch SW is turned on in response to the level command signal Slev which is the first state, and increases the amount of current supplied to the resistor R5. Then, the voltage between the terminals of the resistor R5 rises, and it appears that the current detection level is increased. Then, the voltage supplied to the non-inverting input terminal of the error amplifier EA2 increases, and the output of the error amplifier EA1 further increases due to the positive output of the error amplifier EA2.

  Here, the power transistor Mpt is a P-channel type, and the increase / decrease in the output of the error amplifier EA1 acts oppositely to the N-channel type transistor. Therefore, the increase in the output of the error amplifier EA1 substantially acts as a decrease in the drive signal for the power transistor Mpt in FIG. As a result, the current flowing through the power transistor Mpt is limited to a small value.

  Note that the delay circuit 12 sets the level command signal Slev to the second state after a predetermined time has elapsed since the enable receiving circuit 11 received the enable signal. The switch SW is turned off in response to the level command signal Slev, which is the second state, and reduces the amount of current supplied to the resistor R5. Then, the voltage between the terminals of the resistor R5 decreases, and it appears that the current detection level is lowered. Then, the voltage supplied to the non-inverting input terminal of the error amplifier EA2 is reduced, and the increase in the output of the error amplifier EA1 is made appropriate by the output of the error amplifier EA2.

  By performing such an operation in the overcurrent protection circuit OCP4, it becomes possible to make the peak of the inrush current that occurs when the constant voltage circuit starts up lower than the limit current value during normal operation.

  In the embodiment of the present invention described above, the correction circuit 16 is such that two signals are additively combined, and is most simply composed of a resistance addition circuit. For example, when the output circuit of the error amplifier EA1 is a push-side controlled single-ended type and the error amplifier EA2 is a pull-side controlled single-ended type, the internal configuration of each error amplifier (particularly the output circuit portion) ), The correction circuit 16 may be omitted.

  In the embodiment of the present invention described above, it is assumed that an enable signal is supplied from the outside when the constant voltage circuit is started. However, in the case where no enable signal is supplied, for example, the input terminal IN Alternatively, a circuit for detecting the external power supply may be installed in place of the enable reception circuit 11. However, in this case, the delay circuit 12 sets the level command signal Slev to the first state at the time when the power supply is detected, and the level command signal Slev is set to the second state after a predetermined time has elapsed since the power supply was detected. It is necessary to make the configuration to be in a state.

11: Enable reception circuit 12: Delay circuit 13: Current mirror circuit 14: Current detection circuit 15: Level switching circuit 16: Correction circuit IN: Circuit input terminal OUT: Circuit output terminal OCP0 to OCP4: Overcurrent protection circuit CS1: First current source CS2: second current source EA1: error amplifier EA2: error amplifier (second error amplifier)
Mpt: power transistor Mmi: transistor (current mirror)
M1: first transistor M2: second transistor M3: third transistor R3: first resistor R4: second resistor RL: variable resistance circuit Scd: current detection signal Sdrv: drive signal Slev: level command signal Vr1 : Reference voltage source Vr2: Reference voltage source

Claims (5)

In a constant voltage circuit that generates a drive signal according to the output voltage and reference voltage of the circuit in the error amplifier and feedback-controls the operation of the power transistor connected between the input and output terminals of the circuit by the drive signal.
A current mirror circuit for passing a current proportional to the current passing through the power transistor;
A current detection circuit that detects a current flowing through the current mirror circuit and outputs a current detection signal according to the current;
A level switching circuit that is connected to the current detection circuit and changes a level of the current detection signal;
A correction circuit for reducing the drive signal supplied to the power transistor according to the magnitude of the detection signal;
Comprising
Here, the level switching circuit operates such that the level of the current detection signal is relatively increased when the constant voltage circuit is started, and the level of the current detection signal is relatively decreased during normal operation. Constant voltage circuit. An enable receiving circuit receiving an enable signal from the outside at the time of startup; and
A delay circuit connected to the enable receiving circuit and supplying a level command signal to the level switching circuit;
Further comprising
Here, the delay circuit sets the level command signal to the first state when the enable reception circuit receives the enable signal, and outputs the level command signal after a predetermined time has elapsed after receiving the enable signal. The constant voltage circuit according to claim 1, wherein the constant voltage circuit is in a state of 2. The level switching circuit includes a variable resistance circuit connected in series to the current mirror circuit, and when the level command signal is in a first state, the variable resistance circuit is set to a relatively high resistance state, and the level command 3. The constant voltage circuit according to claim 2, wherein the variable resistance circuit is set in a relatively low resistance state when the signal is in the second state. The current detection circuit is
The variable resistance circuit connected in series to the current mirror circuit;
A second error amplifier that detects a voltage of a predetermined terminal of the variable resistance circuit and generates the detection signal;
The constant current circuit according to claim 3, further comprising: The current detection circuit is
The variable resistance circuit connected in series to the current mirror circuit;
A series circuit of a first transistor and a first constant current source connected to a connection point of the current mirror circuit and the variable resistance circuit;
A second transistor that forms a current mirror circuit with the first transistor, with the first transistor as a current reference side;
A first resistance element and a second constant current source connected in series on both sides of the main current path of the second transistor,
The correction circuit comprises:
A second resistance element connected between the error amplifier and the control terminal of the power transistor;
A third transistor having a main current path connected between the control terminal of the power transistor and a reference potential point of the circuit, and a control terminal connected to a connection point of the second transistor and the second constant current source;
The constant current circuit according to claim 3, further comprising:

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