JP2014016441A - Plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plasma display device capable of reducing power consumption of a data electrode drive circuit while preventing the degradation of image display quality.SOLUTION: The plasma display device includes: a panel having a discharge cell formed at an intersection of a display electrode pair and a data electrode; an image signal processing circuit constituting one field with plural subfields having a prescribed weight for converting image signals into image data representing ON/OFF of each subfield; and a data electrode drive circuit that drives the data electrode based on the image data. The image signal processing circuit calculates the power consumption of a data power drive circuit based on the image data; calculates the pattern load based on the image data; performs data power reduction signal processing to reduce the power consumption of the data power drive circuit when the calculated power consumption exceeds a first threshold value; resets the data power reduction signal processing when the calculated power consumption is lower than a second threshold value lower than the first threshold value; and changes the second threshold value by pattern load.

Description

  The present invention relates to a plasma display apparatus that displays gradation by combining binary control of lighting or non-lighting.

  A plasma display panel (hereinafter abbreviated as “panel”) as a display device that performs binary control of lighting or non-lighting is a front substrate on which a plurality of display electrode pairs each composed of a pair of scan electrodes and sustain electrodes are formed. And a rear substrate on which a plurality of parallel data electrodes are formed are arranged opposite to each other, and a large number of discharge cells are formed therebetween. Then, ultraviolet rays are generated by gas discharge in the discharge cell, and the phosphors of red, green and blue colors are excited and emitted by the ultraviolet rays.

  As a method of displaying gradation by combining binary control of lighting or non-lighting, one field is divided into a plurality of subfields having different lighting luminances, and a desired gradation is displayed by combining the subfields to be lit. The so-called subfield method is common. Each subfield has an address period and a sustain period. In the address period, an address discharge corresponding to an image signal is applied to the data electrode to generate an address discharge in a discharge cell to be lit to form a wall charge. In the sustain period, a sustain discharge is generated in a discharge cell in which a predetermined number of sustain pulses are applied to the display electrode pair composed of the scan electrode and the sustain electrode to form wall charges. Turn on with brightness.

  The plasma display device includes an image signal processing circuit that converts an input image signal into a subfield code indicating lighting / non-lighting for each subfield of the discharge cell. The image signal processing circuit is configured using, for example, a conversion table using a ROM or the like, and one subfield code is output for one input level of the image signal.

  The plasma display device also includes an electrode drive circuit for driving each electrode, and applies a necessary drive voltage waveform to each electrode. Of these, the data electrode drive circuit needs to apply a write pulse for the write operation independently for each of a large number of data electrodes based on the image signal, and therefore usually a dedicated IC (referred to as a “data driver”). It is comprised using. When the panel is viewed from the data electrode driving circuit side, each data electrode is a capacitive load having a stray capacitance between the adjacent data electrode, scan electrode and sustain electrode. Therefore, in order to apply a drive voltage waveform to each data electrode, this capacity must be charged and discharged, and the power consumption becomes non-negligible with the increase in size and definition of the panel. In order to protect the drive circuit, it is necessary to keep power consumption as small as possible.

  As a method for suppressing the power consumption of the data electrode driving circuit (hereinafter referred to as “data power”), a method for limiting the power consumption by various signal processing is disclosed as in Patent Document 1 and Patent Document 2, for example. Yes.

JP 2009-251266 A JP 2010-197903 A

  In order to reduce the data power, the power consumption of each data electrode driving IC is calculated, and image signal processing is performed until the calculation result falls below a set threshold value. In this case, in order to prevent an oscillation operation of signal processing, an image signal processing cancellation threshold value having a certain hysteresis width is set. However, since the optimum value of the hysteresis width varies depending on the image pattern, it has been necessary to ensure an excessive width setting to some extent in order to prevent oscillation. In this case, in order to be canceled after the data power reduction process is activated, it is necessary to input an image signal with sufficiently low data power. During this time, the image signal processing works more than necessary, and the image display quality There has been a problem of lowering.

  The present invention has been made in view of these problems, and an object thereof is to provide a plasma display device having a function of suppressing data power while suppressing a decrease in image display quality.

  To achieve the above object, the present invention comprises a panel in which discharge cells are formed at intersections of display electrode pairs and data electrodes, and a plurality of weighted subfields to form one field, and image signals are A plasma display device comprising: an image signal processing circuit that converts image data indicating lighting or non-lighting of each field; and a data electrode driving circuit that drives the data electrode based on the image data, wherein the image signal processing The circuit calculates power consumption of the data electrode driving circuit based on the image data, calculates a pattern load based on the image data, and when the calculated power consumption exceeds a first threshold value, power consumption of the data electrode driving circuit When the calculated power consumption falls below a second threshold that is lower than the first threshold, the data power reduction signal processing is performed to reduce the data Releasing the power reduction signal processing, characterized by changing the second threshold value by the design load. With this configuration, it is possible to provide a plasma display device that suppresses data power while suppressing deterioration in image display quality.

  According to the present invention, it is possible to provide a plasma display device that includes an image signal processing circuit for reducing data power and further has a function of suppressing data power while suppressing a decrease in image display quality.

1 is an exploded perspective view of a panel of a plasma display device according to an embodiment of the present invention. Electrode arrangement of the plasma display panel Drive voltage waveform diagram applied to each electrode of the panel of the plasma display device The figure which shows an example of the code set at the time of comprising one field period by eight subfields Circuit block diagram of the plasma display device Block diagram of the image signal processing circuit of the plasma display device Circuit block diagram of data power calculation unit of the plasma display device The figure which shows the code set example used in the pattern load calculation part of the plasma display apparatus The figure explaining the control threshold value determination method of the plasma display apparatus The figure explaining the image processing operation of the plasma display device The figure explaining the image processing operation of the plasma display device The figure explaining the image processing operation of the plasma display device

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view of panel 10 of the plasma display device in accordance with the exemplary embodiment of the present invention. On the glass front substrate 11, a plurality of display electrode pairs 14 made up of scanning electrodes 12 and sustaining electrodes 13 are formed. A dielectric layer 15 is formed so as to cover the display electrode pair 14, and a protective layer 16 is formed on the dielectric layer 15. A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is formed thereon. On the side surface of the partition wall 24 and on the dielectric layer 23, a phosphor layer 25 that is lit in each color of red, green, and blue is provided.

  The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by barrier ribs 24, and discharge cells are formed at portions where display electrode pairs 14 and data electrodes 22 intersect. When these discharge cells are turned on, an image is displayed.

  FIG. 2 is an electrode array diagram of panel 10 of the plasma display device in accordance with the exemplary embodiment of the present invention. In the panel 10, n scanning electrodes 12 and n sustain electrodes 13 that are long in the row direction are arranged, and m data electrodes 22 that are long in the column direction are arranged. A discharge cell is formed at a portion where a pair of scan electrode 12 and sustain electrode 13 and one data electrode 22 intersect, and m × n discharge cells are formed in the discharge space.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described. The plasma display device comprises a subfield method, that is, a plurality of subfields having weights (luminance weights) defined, and each of the subfields controls the lighting / non-lighting of each discharge cell to control gradation. indicate.

  Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, an initializing discharge is generated, and an initializing operation for forming wall charges necessary for the subsequent address discharge on each electrode is performed. In the address period, an address operation is performed in which address discharge is selectively generated in the discharge cells to be lit to form wall charges. In the sustain period, a number of sustain pulses corresponding to a predetermined weight for each subfield are alternately applied to the scan electrode 12 and the sustain electrode 13 of the display electrode pair, and maintained in the discharge cell in which the address discharge is generated. Generate a discharge to light up.

  FIG. 3 is a waveform diagram of driving voltage applied to each electrode of panel 10 of the plasma display device in accordance with the exemplary embodiment of the present invention.

  In the first half of the initializing period Ti of the subfield SF1, a voltage 0 (V) is applied to the data electrode 22 and the sustain electrode 13, respectively, and an upward ramp waveform gradually rising from the voltage Vi1 to the voltage Vi2 to the scan electrode 12. Apply voltage. Then, a weak initializing discharge occurs between the scan electrode 12 and the sustain electrode 13, and between the scan electrode 12 and the data electrode 22, respectively. Negative wall voltage is accumulated on scan electrode 12, and positive wall voltage is accumulated on data electrode 22 and sustain electrode 13. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the second half of the initialization period Ti, a positive voltage Ve is applied to the sustain electrode 13, and a downward ramp waveform voltage that gently falls from the voltage Vi3 to Vi4 is applied to the scan electrode 12. Then, a weak initializing discharge occurs between the scan electrode 12 and the sustain electrode 13, and between the scan electrode 12 and the data electrode 22, respectively. Then, the negative wall voltage on scan electrode 12 and the positive wall voltage on sustain electrode 13 are weakened, and the positive wall voltage on data electrode 22 is adjusted to a value suitable for the write operation.

  As the operation in the initialization period, as shown in the initialization period of the subfield SF2, a downward ramp waveform voltage that gently decreases from a predetermined voltage (voltage 0 (V) in FIG. 3) toward the voltage Vi4. May be simply applied to the scan electrode 12. In this case, the initializing discharge is selectively generated only in the discharge cells that have undergone the sustain discharge in the immediately preceding subfield.

  In the subsequent address period Tw, the voltage Ve is applied to the sustain electrode 13 and the voltage Vc is applied to the scan electrode 12.

  Next, a scan pulse of voltage Va is applied to the scan electrode 12 of the first row, and an address pulse of voltage Vd is applied to the data electrode 22 of the discharge cell to be lit in the first row of the data electrodes 22. Then, the voltage difference at the intersection between the data electrode 22 and the scan electrode 12 exceeds the discharge start voltage, and an address discharge is generated between the data electrode 22 and the scan electrode 12 and between the sustain electrode 13 and the scan electrode 12. To do. A positive wall voltage is accumulated on scan electrode 12, a negative wall voltage is accumulated on sustain electrode 13, and a negative wall voltage is also accumulated on data electrode 22.

  In this way, an address operation is performed in which address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, since the voltage at the intersection between the data electrode 22 and the scan electrode 12 to which no address pulse is applied does not exceed the discharge start voltage, the address discharge does not occur. The above address operation is performed until the discharge cell in the n-th row, and the address period Tw ends.

  In the subsequent sustain period Ts, the voltage 0 (V) is applied to the sustain electrode 13 and the sustain pulse of the voltage Vs is applied to the scan electrode 12. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between the scan electrode 12 and the sustain electrode 13 exceeds the discharge start voltage, and a sustain discharge is generated between the scan electrode 12 and the sustain electrode 13, so that the phosphor layer 25 Emits light and the discharge cell lights up. Then, a negative wall voltage is accumulated on scan electrode 12, and a positive wall voltage is accumulated on sustain electrode 13. Further, a positive wall voltage is also accumulated on the data electrode 22.

  However, the sustain discharge does not occur in the discharge cells that did not cause the address discharge in the address period Tw, and the wall voltage at the end of the initialization period Ti is maintained.

  Subsequently, a voltage 0 (V) is applied to the scan electrode 12, and a sustain pulse of the voltage Vs is applied to the sustain electrode 13. Then, the sustain discharge occurs again in the discharge cell in which the sustain discharge has occurred, the negative wall voltage is accumulated on the sustain electrode 13, and the positive wall voltage is accumulated on the scan electrode 12. Thereafter, the number of sustain pulses corresponding to the gradation weight is alternately applied to the scan electrodes 12 and the sustain electrodes 13 to light the discharge cells.

  Then, at the end of the sustain period Ts, after the sustain electrode 13 is returned to the voltage 0 (V), an upward ramp waveform voltage that gradually rises to the voltage Vr is applied to the scan electrode 12. Then, a weak discharge occurs between sustain electrode 13 and scan electrode 12 of the discharge cell in which the sustain discharge has occurred, and the wall voltage between scan electrode 12 and sustain electrode 13 is weakened. Thereafter, the voltage applied to the scan electrode 12 is returned to the voltage 0 (V). Thus, sustain period Ts ends.

  Subsequent subfield SF2 and subsequent subfields operate in substantially the same manner as described above except for the number of sustain pulses.

  In this embodiment, the voltage values applied to the electrodes are, for example, the voltage Vi1 = 140 (V), the voltage Vi2 = 340 (V), the voltage Vi3 = 200 (V), and the voltage Vi4 = −190 (V). , Voltage Vc = −60 (V), voltage Va = −200 (V), voltage Vs = 200 (V), voltage Vr = 200 (V), voltage Ve = 130 (V), voltage Vd = 70 (V) It is. However, these values are merely examples, and it is desirable to set them to optimum values as appropriate in accordance with the characteristics of the panel 10 and the specifications of the plasma display device.

  In this way, in the subfield method, one field is composed of a plurality of subfields with predetermined weights, and gradation is displayed by a combination of subfields that light the discharge cells. Hereinafter, a combination of lighting or non-lighting of each subfield is referred to as “subfield code” or simply “code”.

  FIG. 4 is a diagram illustrating an example of a code set in a case where one field period includes eight subfields SF1 to SF8. Here, the numerical values shown in the leftmost column indicate gradations, and the right side indicates whether or not the discharge cells are lit in each subfield when displaying the gradations, that is, subfield codes. Here, a blank indicates non-lighting, and “1” indicates lighting. For example, in FIG. 4, in order to display the gradation “2”, it is only necessary to light the discharge cell only in the subfield SF2, and the subfield code in this case is “01000000”. In order to display the gradation “14”, the discharge cells may be lit in the subfields SF1, SF2, SF3, and SF5. In this case, the subfield code is “11101000”.

  FIG. 5 is a circuit block diagram of plasma display device 30 in accordance with the exemplary embodiment of the present invention. The plasma display device 30 includes a panel 10, an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 31 converts the image signal into a subfield code indicating a combination of lighting or non-lighting of each subfield. That is, an image signal is input and a display code which is a subfield code for displaying gradation is output.

  The data electrode drive circuit 32 displays an image by controlling lighting or non-lighting of each discharge cell based on the subfield code. That is, the data electrode driving circuit 32 converts the display code output from the image signal processing circuit 31 into an address pulse corresponding to each of the data electrodes D1 to Dm, and applies it to each of the data electrodes D1 to Dm. The electrodes D1 to Dm are driven. Here, the data electrode driving circuit 32 is configured using a plurality of dedicated ICs (hereinafter referred to as “data drivers”). Thus, by making the drive circuit for driving a large number of data electrodes into an IC, the circuit can be made compact, the mounting area can be reduced, and the cost can be reduced. However, since the allowable power loss of the data driver is limited, the power consumption of the data electrode driving circuit 32 must be suppressed so as not to exceed this limit. In addition, the reduction in power consumption plays an important role in terms of power saving in plasma display panels as the panel size and resolution become higher.

  In the present embodiment, it is assumed that m data electrodes are configured to be driven using 16 data drivers 32 (1) to 32 (16). However, the present invention is not limited to the number of data drivers.

  The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal, and supplies them to the respective circuit blocks. The scan electrode drive circuit 33 creates the drive voltage waveform shown in FIG. 3 based on the timing signal and applies it to each of the scan electrodes 12. The sustain electrode drive circuit 34 creates the drive voltage waveform shown in FIG. 3 based on the timing signal and applies it to each sustain electrode 13.

  FIG. 6 is a block diagram of the image signal processing circuit 31 of the plasma display device 30 according to the embodiment of the present invention. The image signal processing circuit 31 includes a data power reduction signal processing unit 41, a data power calculation unit 42, a design load calculation unit 43, and a control unit 44.

  The data power reduction signal processing unit 41 changes the image signal to a display code that suppresses the power consumption of the data electrode driving circuit 32 according to the control of the control unit 44. The data power reduction signal processing unit 41 in the present embodiment reduces the number of tones that can be displayed by limiting the tones by subfield code conversion, and performs conversion to an image with a low spatial frequency by using a two-dimensional low-pass filter. A plurality of signal processing is performed to reduce the level of the image signal and to turn off the data of the subfield. The plurality of signal processes are signal processes for reducing data power. The gain (intensity) of each signal processing increases as the data power increases. Further, regarding the order of control of a plurality of signal processing, the processing may be performed in order from the one in which each signal processing has less influence on image quality.

  The data power calculator 42 calculates the power consumption of each of the data drivers 32 (1) to 32 (16) based on the image data for each subfield generated from the image signal, and outputs the maximum value thereof. The calculation of the power consumption can be performed as follows, for example.

  As for power consumption in the data driver 32, a discharge cell that generates an address discharge (hereinafter referred to as “lighting cell”) and a discharge cell that does not generate an address discharge (hereinafter referred to as “non-lighting cell”) are adjacent to each other. The number increases as the number increases, and the number increases as the number of adjacent lighting cells or non-lighting cells increases. This is because the data driver 32 generates a write pulse by switching a plurality of switching elements included therein, and the greater the number of adjacent lighting cells and non-lighting cells, the more the switching frequency of switching elements increases. This is because the number of switching of the switching elements decreases as the number of the lighting cells or the non-lighting cells adjacent to each other increases.

  The data power calculation unit 42 can use this to calculate the power consumption in the data driver 32. For example, a lighted cell is set to “1”, a non-lighted cell is set to “0”, an exclusive OR operation is performed between adjacent discharge cells, and the results are cumulatively added. Thereby, the number of locations where the lighted cell and the non-lighted cell are adjacent can be counted. If the relationship between the cumulative addition value thus obtained and the power consumption in the data driver 32 is examined in advance and the data is provided to the data power calculation unit 42, the above cumulative addition value can be calculated. The power consumption can be calculated. FIG. 7 is a circuit block diagram of the data power calculation unit 42.

  The data power calculation unit 42 includes driver power calculation units 101 (1) to 101 (16) that calculate power consumption for each of the data drivers 32 (1) to 32 (16), and driver power calculation units 101 (1) to 101 (1) to 101 (16), the driver power accumulation units 102 (1) to 102 (16) that accumulate the respective outputs for a predetermined time, and the driver power accumulation units 102 (1) to 102 (16) respectively. And a maximum power selection unit 104 to be selected. With such a configuration, the data power calculation unit 42 calculates the power consumption of each of the data drivers 32 (1) to 32 (16) and outputs the maximum value thereof.

  The pattern load calculation unit 43 calculates virtual data power when the gradation limit is maximized, and outputs the calculation result as a pattern load. The pattern load changes depending on the image pattern. Depending on the size of the pattern load, it is possible to determine whether the image pattern is a pattern from a natural picture or a geometric pattern such as a checkered pattern. . For example, a checkered pattern has a larger pattern load than a natural picture. Since the data power increases as the number of lit cells and non-lit cells increases, as described above, signal processing such as gradation limitation is effective for patterns such as natural images. On the other hand, tone restriction is hardly effective for a pattern such as a checkered pattern that originally has little tone expression. Using this characteristic, data power is calculated in a state in which gradation limitation is applied as shown in FIG. 8, and the calculation result is output as a pattern load. That is, the image signal is converted into a subfield code for display using the code set of FIG. 8, and the data power calculated using the subfield code is used as a picture load. The calculation of the data power at this time is the same as the method performed by the data power calculation unit 42, the power consumption of each of the data drivers 32 (1) to 32 (16) is calculated, and the maximum value of the data power (picture pattern) is calculated. Load). An image pattern is presumed to be a natural image when the pattern load is small, and a special pattern such as a checkered pattern when the pattern load is large. The code set in FIG. 8 is set so that, in one field, each subfield SF1 to SF8 is set to the last subfield to be lit, and all subfields before that subfield are lit. This is a code set in a case where the gradation displayed by the displayed code and the 0 gradation in which all the subfields SF1 to SF8 are not lit are limited as gradations that can be displayed.

  Based on the data power calculation result, the control unit 44 releases the power reduction processing to the data power reduction signal processing unit 41 when a preset power reduction processing start threshold (hereinafter abbreviated as “start threshold”) is exceeded. Data power reduction signal processing is continued until a threshold value (hereinafter abbreviated as “release threshold”) is exceeded. However, if it falls below the release threshold, the intensity of the data power reduction signal processing is reduced, and control is performed so that the signal processing is gradually returned from the processing having a large influence on the image quality to the processing having a small influence. At this time, the control unit 44 sets a release threshold according to the result (design load) calculated by the design load calculation unit 43. If the estimated pattern is a special pattern such as a checkered pattern, the process of reducing power is easier to work, so there is a high possibility of interrupting the release threshold during the data power reduction signal processing, and there is a concern about processing oscillation. The In order to prevent this oscillation, it is conceivable that the release threshold value is greatly lowered from the start threshold value. In this case, even after switching to an image signal with low data power after the data power reduction signal processing operation, the signal processing is not performed. This will lead to a reduction in image display quality. For this reason, the design load is calculated by the design load calculation unit 43 to estimate the image pattern, and the release threshold optimized according to the image pattern is determined. FIG. 9 is a diagram illustrating a determination method of the release threshold, the horizontal axis indicates the pattern load calculated by the pattern load calculation unit 43, and the vertical axis indicates the reduction amount ΔP from the start threshold to the release threshold. In this way, the pattern load calculated by the pattern load calculation unit 43 and the optimum hysteresis width for the pattern load are examined in advance, and the control unit 44 may have the value.

  Note that FIG. 9 is a straight line graph (a relationship in which the reduction amount ΔP increases at a constant ratio with respect to the increase amount of the pattern load), but this is not the case. As long as the amount of reduction ΔP is greater when the pattern load is larger than when the pattern load is small, for example, the relationship may be such that the amount of decrease ΔP changes stepwise with respect to the pattern load.

  10A, 10B, and 10C are diagrams for explaining the operation of the image signal processing circuit 31 of the plasma display device 30 according to the embodiment of the present invention, where the horizontal axis indicates time and the vertical axis indicates a data power calculation unit. The data power calculated by 42 is shown.

  As shown in FIG. 10A, when the data power exceeds the start threshold (first threshold) (T1), the data power reduction signal processing is started, and the data power decreases. At this time, if the hysteresis width of the threshold is small, it falls below the release threshold (second threshold) (T2), the data power reduction signal processing is canceled and the power rises, and if the start threshold is exceeded (T3), the data power reduction signal again Transition to processing operation. Thereafter, the value again falls below the release threshold value (second threshold value) (T4), and the data power reduction signal processing is released to increase the power. In other words, image processing oscillates and the screen flickers momentarily, leading to a reduction in display quality of the panel. Here, the threshold hysteresis width is a difference between the start threshold and the release threshold, and the release threshold is lower than the start threshold.

  FIG. 10B shows a case where the hysteresis width is increased in order to avoid this. In this case, similarly to FIG. 10A, when the data power exceeds the first threshold (T5), the data power reduction signal processing is started, and the data power decreases. At this time, since the hysteresis width of the threshold is sufficiently large and the data power does not fall below the second threshold (T6), the control is stabilized (T7). However, once the data power reduction signal processing operation is entered, it may be difficult to return from that state. This means that excessive data power reduction signal processing is performed, leading to deterioration of screen display quality.

  FIG. 10C shows a method of determining the release threshold according to the data power calculation result of the picture load calculation unit 43 in order to solve the above-described problem. When the data power exceeds the first threshold (T8), the data power reduction signal processing is started and the data power decreases. At this time, in addition to the preset width ΔP1, the second threshold is further lowered by ΔP2 in accordance with the increase in the added pattern value. Thereby, the data power load value does not fall below the second threshold value, and the control is stabilized (T9). If the input pattern load value decreases, ΔP2 decreases and the second threshold value increases again. At this time, the data power falls below the second threshold (T10), the data power reduction signal processing is canceled again, and the power increases. That is, by setting the hysteresis width according to the input image, it is possible to suppress data power while preventing deterioration in display quality such as excessive image processing and data power reduction signal processing oscillation.

  Note that each circuit block shown in the present embodiment may be configured as an electric circuit that performs the above-described operations, or may be configured using a processor or the like that is programmed to perform the above-described operations. .

  In addition, the specific numerical values used in the present embodiment are merely examples, and it is desirable to appropriately set the optimal values according to the specifications of the plasma display device.

  The present invention has a function of suppressing data power while suppressing deterioration in image display quality, and is useful as a plasma display device.

DESCRIPTION OF SYMBOLS 10 Panel 12 Scan electrode 13 Sustain electrode 22 Data electrode 30 Plasma display apparatus 31 Image signal processing circuit 32 Data electrode drive circuit 41 Data power reduction signal processing part 42 Data power calculation part 43 Picture load calculation part 44 Control part 101 Driver power calculation part 102 Driver power accumulator 104 Maximum power selector

Claims (2)

Image data indicating lighting or non-lighting of each subfield by forming one field with a panel in which discharge cells are formed at intersections between display electrode pairs and data electrodes and a plurality of weighted subfields A plasma display device comprising: an image signal processing circuit for converting to a data electrode; and a data electrode driving circuit for driving the data electrode based on the image data, wherein the image signal processing circuit is based on the image data. Calculating power consumption of the drive circuit, calculating a pattern load based on the image data, performing data power reduction signal processing for reducing the power consumption of the data electrode drive circuit when the calculated power consumption exceeds a first threshold, When the calculated power consumption falls below a second threshold that is lower than the first threshold, the data power reduction signal processing is canceled, and the second A plasma display apparatus characterized by changing the threshold value by the design load. 2. The plasma display device according to claim 1, wherein when the pattern load is large, the second threshold value is set lower than when the pattern load is small.

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